CN112821884B - Signal generation circuit, memory storage device and signal generation method - Google Patents
Signal generation circuit, memory storage device and signal generation method Download PDFInfo
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- CN112821884B CN112821884B CN201911126811.5A CN201911126811A CN112821884B CN 112821884 B CN112821884 B CN 112821884B CN 201911126811 A CN201911126811 A CN 201911126811A CN 112821884 B CN112821884 B CN 112821884B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
Abstract
Exemplary embodiments of the present invention provide a signal generating circuit, a memory storage device and a signal generating method, wherein the signal generating circuit comprises a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is used for generating a phase control signal according to the phase adjustment signal. The bias control circuit is used for generating bias voltage according to the phase control signal. The phase interpolation circuit is used for generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal.
Description
Technical Field
The present invention relates to signal processing technology, and more particularly, to a signal generating circuit, a memory storage device, and a signal generating method.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.
Generally, a clock data recovery circuit is commonly disposed at the signal receiving end to synchronize the data signal with the clock signal. Some clock data recovery circuits implement phase adjustment of the clock signal by a phase interpolation circuit. For example, the phase interpolation circuit can synthesize a clock signal with an arbitrary phase by the IQ clock. However, in practice, the clock signal output by the phase interpolation circuit is often not accurate enough due to the limitation of hardware design.
Disclosure of Invention
The invention provides a signal generating circuit, a memory storage device and a signal generating method, which can generate more accurate clock signals.
An exemplary embodiment of the present invention provides a signal generating circuit, which includes a phase control circuit, a bias control circuit, and a phase interpolation circuit. The phase control circuit is used for generating a phase control signal according to the phase adjustment signal. The bias control circuit is connected to the phase control circuit and is used for generating a bias voltage according to the phase control signal. The phase interpolation circuit is connected to the phase control circuit and the bias control circuit and is used for generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal.
In an exemplary embodiment of the invention, the bias control circuit includes a coding circuit and a bias circuit. The encoding circuit is connected to the phase control circuit and is used for generating a bias control signal according to the phase control signal. The bias circuit is connected to the encoding circuit and is used for generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the invention, the bias control circuit further includes a filter circuit. The filter circuit is connected to the bias circuit and the phase interpolation circuit and is used for filtering the first bias voltage to generate the bias voltage.
In an exemplary embodiment of the present invention, the phase interpolation circuit includes a driving circuit and a phase interpolator. The phase interpolator is connected to the driving circuit. The driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and the phase interpolator is used for generating the clock signal according to the current.
The exemplary embodiment of the invention further provides a memory storage device, which comprises a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The clock data recovery circuit is arranged in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit. The clock data recovery circuit comprises a signal generation circuit. The signal generating circuit is used for generating a phase control signal according to the phase adjustment signal. The signal generating circuit is further used for generating a bias voltage according to the phase control signal. The signal generating circuit is further used for generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal.
In an exemplary embodiment of the invention, the signal generating circuit includes a coding circuit and a bias circuit. The encoding circuit is used for generating a bias control signal according to the phase control signal. The bias circuit is connected to the encoding circuit and is used for generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the invention, the bias circuit includes a current source and at least one switching circuit. The at least one switch circuit is connected in series to the current source and is used for responding to the bias control signal to adjust the conduction state of the at least one switch circuit so as to adjust the bias voltage.
In an exemplary embodiment of the invention, the signal generating circuit further comprises a filtering circuit. The filter circuit is connected to the bias circuit and is used for filtering the first bias voltage to generate the bias voltage.
In an exemplary embodiment of the invention, the signal generating circuit includes a driving circuit and a phase interpolator. The phase interpolator is connected to the driving circuit. The driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and the phase interpolator is used for generating the clock signal according to the current.
In an exemplary embodiment of the present invention, the bias voltage is used to adjust the voltage of the clock signal according to a first amplification ratio in response to a first target phase, and to adjust the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase being different from the second target phase and the first amplification ratio being different from the second amplification ratio.
The exemplary embodiments of the present invention further provide a signal generating method for a memory storage device. The signal generation method comprises the following steps: generating a phase control signal according to the phase adjustment signal; generating a bias voltage according to the phase control signal; and generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal.
In an exemplary embodiment of the present invention, the step of generating the bias voltage according to the phase control signal includes: generating a bias control signal according to the phase control signal; and generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the present invention, the step of generating the first bias voltage according to the bias control signal includes: and adjusting the conduction state of at least one switch circuit to adjust the bias voltage in response to the bias control signal.
In an exemplary embodiment of the present invention, the step of generating the bias voltage according to the phase control signal further includes: the first bias voltage is filtered to produce the bias voltage.
In an exemplary embodiment of the present invention, the step of generating the clock signal according to the phase control signal and the bias voltage includes: providing the current to a phase interpolator based on the phase control signal and the bias voltage; and generating, by the phase interpolator, the clock signal based on the current.
In an exemplary embodiment of the invention, the bias voltage affects a current value of the current.
In an exemplary embodiment of the present invention, the signal generating method further includes: adjusting the voltage of the clock signal according to the bias voltage and a first amplification ratio in response to a first target phase; and adjusting the voltage of the clock signal according to the bias voltage and a second amplification ratio in response to a second target phase. The first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
Based on the above, the phase control circuit may generate a phase control signal according to the phase adjustment signal, and the bias control circuit may generate a bias voltage according to the phase control signal. The bias voltage can be used for adjusting the current of the phase interpolation circuit so as to effectively correct the clock signal generated by the phase interpolation circuit.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a signal generation circuit according to an example embodiment of the invention;
FIG. 2 is a schematic diagram illustrating phase interpolation according to an example embodiment of the invention;
FIGS. 3A and 3B are diagrams illustrating nonlinear distortion of a corrected clock signal according to various exemplary embodiments of the present invention;
FIG. 4 is a schematic diagram of a signal generation circuit according to an example embodiment of the invention;
FIG. 5 is a diagram of a corrected clock signal according to an example embodiment of the invention;
FIG. 6 is a schematic diagram of a bias control circuit according to an example embodiment of the invention;
FIG. 7 is a schematic diagram of a phase interpolation circuit according to an example embodiment of the invention;
FIG. 8 is a schematic diagram of a clock data recovery circuit according to an example embodiment of the invention;
FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
fig. 10 is a flowchart illustrating a signal generation method according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 40: signal generating circuit
11. 41: phase control circuit
12. 42: bias control circuit
13. 43: phase interpolation circuit
301. 302, 303: dotted line
401: coding circuit
402: bias circuit
403: filtering circuit
501: boundary of
601 (1) to 601 (n): switching circuit
I (REF): current source
SW (1) to SW (n): switch
R: resistor
C: capacitance device
N1 (1) to N1 (N), N2 (1) to N2 (m), N3 (1) to N3 (m), N4 (1) to N4 (m): transistor with a high-voltage power supply
80: clock data recovery circuit
81: phase detection circuit
82: phase adjusting circuit
83: signal generating circuit
90: memory storage device
91: connection interface unit
92: memory control circuit unit
93: rewritable nonvolatile memory module
PAS、PCS(1)、PCS(2)、CLK、Y、X I 、X Q Y (1), Y (2), Y (i), VCS: signal signal
V (Bias), V (Bias)': bias voltage
a 1 、a 2 、a 1 (0)、a 1 (1)、a 1 (2)、a 2 (0)、a 2 (1)、a 2 (2): parameters (parameters)
: phase of
S1001: step (generating a phase control signal based on the phase adjustment signal)
S1002: step (generating bias voltage according to the phase control signal)
S1003: generating a clock signal according to the phase control signal and the bias voltage
Detailed Description
The present invention is described below with reference to a number of exemplary embodiments, however, the present invention is not limited to the exemplary embodiments illustrated. Also, suitable combinations are allowed between the exemplary embodiments. The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect means of coupling. For example, if a first device is described herein as being connected to a second device, it should be interpreted that the first device may be directly connected to the second device, or that the first device may be indirectly connected to the second device through other devices or some connection means. Further, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
Fig. 1 is a schematic diagram of a signal generating circuit according to an exemplary embodiment of the invention. Referring to fig. 1, the signal generating circuit 10 may generate a signal (also referred to as a clock signal) CLK according to a signal (also referred to as a phase adjustment signal) PAS. For example, the signal PAS may carry information about the phase of the signal CLK and/or information that may be used to adjust the phase of the signal CLK. According to the signal PAS, the signal generating circuit 10 may generate the signal CLK having a specific phase and/or a specific frequency by means of phase interpolation.
The signal generating circuit 10 includes a phase control circuit 11, a bias control circuit 12, and a phase interpolation circuit 13. The phase control circuit 11 is connected to the bias control circuit 12 and the phase interpolation circuit 13. The phase control circuit 11 receives the signal PAS and generates signals PCS (1) and PCS (2) according to the signal PAS. The signals PCS (1) and PCS (2) may also be collectively referred to as phase control signals. The Bias control circuit 12 receives the signal PCS (1) and generates a Bias voltage V (Bias) according to the signal PCS (1). The voltage value of the Bias voltage V (Bias) is controlled by the signal PCS (1). The Bias voltage V (Bias) can be used to drive the phase interpolation circuit 13. The phase interpolation circuit 13 receives the signal PCS (2) and the Bias voltage V (Bias) and performs phase interpolation according to the signal PCS (2) and the Bias voltage V (Bias) to generate the signal CLK.
It should be noted that the phase of the generated signal CLK is mainly specified by the signals PCS (1) and PCS (2), and the Bias voltage V (Bias) adjusts the current of the phase interpolation circuit 13 according to the specified phase, thereby correcting the error of the signal CLK. For example, this error may refer to a phase error and/or an amplitude error. In other words, the Bias control circuit 12 can fine-tune the Bias voltage V (Bias) according to the signal PCS (1). The phase interpolation circuit 13 can generate a more accurate signal CLK according to the driving of the adjusted Bias voltage V (Bias).
Fig. 2 is a schematic diagram illustrating phase interpolation according to an example embodiment of the invention. Referring to fig. 2, assume that the phase interpolation is performed by signal X I And X is Q Waveform synthesis as a substrate to produce a waveform with phaseSignal Y of (2), signal X I 、X Q And Y can be represented by the following equations (1.1) to (1.3), respectively.
X I ＝Asin(wt) (1.1)
X Q ＝Asin(wt-π/2)＝-Acos(wt) (1.2)
In equations (1.1) to (1.3), A represents signal X I 、X Q And the amplitude of Y. In an ideal state, parameter a 1 And a 2 To meet a 1 2 +a 2 2 A condition of=1 to produce a signal Y with a perfect waveform. It should be noted that the practice is often to use a 1 +a 2 =1 to replace a 1 2 +a 2 2 =1 to reduce the complexity and cost of the circuit design, but also thus causes nonlinear distortion of the phase interpolation. In an exemplary embodiment of fig. 1, the adjustment of the Bias voltage V (Bias) can be used to improve the nonlinear distortion, so that the signal CLK generated by the phase interpolation circuit 13 is closer to the expected perfect waveform.
Fig. 3A and 3B are schematic diagrams illustrating nonlinear distortion of a corrected clock signal according to various exemplary embodiments of the present invention. Referring to FIG. 3A, a dotted line 301 is used to indicate the condition a 1 (0)+a 2 (0) =1, and dashed line 302 is used to represent condition a 1 (1)+a 2 (1) =1+e (1). Under the preset operation of the phase interpolation circuit 13 of fig. 1, the phase interpolation circuit 13 can generate the signal X I And X is Q Waveform synthesis as a substrate to produce a waveform with phaseSignal Y (1) of (2). For example, the signal Y (1) may be the signal CLK of fig. 1.
It should be noted that if the signal Y (1) is not corrected and compensated by adjusting the Bias voltage V (Bias) of fig. 1, the generated signal Y (1) meets the condition (i.e., a) corresponding to the dashed line 301 1 (0)+a 2 (0) =1), and the signal Y (1) has the above-described nonlinear distortion problem. However, in the exemplary embodiment of fig. 3A, if the signal Y (1) is corrected and compensated by adjusting the Bias voltage V (Bias) of fig. 1, the generated signal Y (1) may meet the condition (i.e., a) corresponding to the dashed line 302 1 (1)+a 2 (1) =1+e (1)). For example, the parameter e (1) may be 0.5 (i.e., a 1 (1)+a 2 (1) =1.5). It should be noted that the parameter e (1) is automatically generated by adjusting the Bias voltage V (Bias) to compensate the nonlinear distortion of the signal Y (1). Therefore, the corrected signal Y (1) is more ideal than the uncorrected signal Y (1) 1 (1) 2 +a 2 (1) 2 Condition of =1.
Referring to FIG. 3B, a dotted line 301 is also used to indicate the condition a 1 (0)+a 2 (0) =1, and the dotted line 303 is used to represent the condition a 1 (2)+a 2 (2) =1+e (2). Under the preset operation of the phase interpolation circuit 13 of fig. 1, the phase interpolation circuit 13 can generate the signal X I And X is Q Waveform synthesis as a substrate to produce a waveform with phaseSignal Y (2) of (2). For example, the signal Y (2) may be the signal CLK of fig. 1.
It should be noted that if the signal Y (2) is not corrected and compensated by adjusting the Bias voltage V (Bias) of fig. 1, the generated signal Y (2) meets the condition (i.e., a) corresponding to the dashed line 301 1 (0)+a 2 (0) =1), and the signal Y (2) has the above-described nonlinear distortion problem. However, in the exemplary embodiment of fig. 3B, if the signal Y (2) is corrected and compensated by adjusting the Bias voltage V (Bias) of fig. 1, the generated signal Y (2) can satisfy the condition (i.e., a) corresponding to the dashed line 303 1 (2)+a 2 (2) =1+e (2)). For example, the parameter e (2) may be 0.3 (i.e., a 1 (2)+a 2 (2) =1.3). It should be noted that the parameter e (2) is also automatically generated by adjusting the Bias voltage V (Bias) to compensate the nonlinear distortion of the signal Y (2). In the example embodiment of FIG. 3B, the corrected signal Y (2) is more ideal than the uncorrected signal Y (2) 1 (2) 2 +a 2 (2) 2 Condition of =1. In addition, the Bias voltage V (Bias) for compensating the signal Y (1) in the example embodiment of fig. 3A may be different from the Bias voltage V (Bias) for compensating the signal Y (2) in the example embodiment of fig. 3B.
From another perspective, in an example embodiment of FIG. 3A, the response is to a target phase (also referred to as a first target phase)The generated Bias voltage V (Bias) can be used to adjust the voltage (or the vibration) of the signal Y (1) according to an amplification ratio (also referred to as a first amplification ratio), so as to correct and compensate the signal Y (1). Furthermore, in an example embodiment of FIG. 3B, in response to another target phase (also referred to as a second target phase)/(N)>The generated Bias voltage V (Bias) can be used to adjust the voltage (or the gain) of the signal Y (2) according to another amplification ratio (also referred to as a second amplification ratio), so as to correct and compensate the signal Y (2). The first target phase is different from the second target phase. The first magnification ratio is different from the second magnification ratio.
Fig. 4 is a schematic diagram of a signal generating circuit according to an exemplary embodiment of the invention. Referring to fig. 4, the signal generating circuit 40 includes a phase control circuit 41, a bias control circuit 42 and a phase interpolation circuit 43. The phase control circuit 41 can generate signals PCS (1) and PCS (2) according to the signal PAS. The Bias control circuit 42 may generate a Bias voltage V (Bias) according to the signal PCS (1). The voltage value of the Bias voltage V (Bias) is controlled by the signal PCS (1). The phase interpolation circuit 43 performs phase interpolation according to the signal PCS (2) and the Bias voltage V (Bias) to generate the signal CLK.
In an exemplary embodiment, the bias control circuit 42 includes an encoding circuit 401, a bias circuit 402, and a filtering circuit 403. The bias circuit 402 is connected to the encoding circuit 401 and the filter circuit 403. The encoding circuit 401 may receive the signal PCS (1) and generate a signal (also referred to as a bias control signal) VCS based on the signal PCS (1). For example, the signal VCS may correspond to a digital code. The Bias circuit 402 may receive the signal VCS and generate a Bias voltage (also referred to as a first Bias voltage) V (Bias) according to the signal VCS. The filtering circuit 403 may receive the Bias voltage V (Bias) 'and filter (e.g., low pass filter) the Bias voltage V (Bias)' to generate the Bias voltage V (Bias). It should be noted that the filter circuit 403 may make the change of the Bias voltage V (Bias) more continuous and/or smooth. In another exemplary embodiment, the filter circuit 403 may not be disposed in the signal generating circuit 40, and the Bias voltage V (Bias)' may be directly used to drive the phase interpolation circuit 43. In an exemplary embodiment, the phase interpolation circuit 43 is directly driven by the Bias voltage V (Bias)' to achieve the correction effect similar to that shown in fig. 3A and 3B.
FIG. 5 is a schematic illustration of a corrected clock signal according to an example embodiment of the inventionA drawing. Referring to fig. 5, in the case of setting the filter circuit 403 of fig. 4, when adjusting the phase of the generated signal Y (i), the signal Y (i) can be more similar to the ideal state due to the continuous and/or smooth change of the Bias voltage V (Bias), condition a 1 (i) 2 +a 2 (i) 2 Circular boundary 501 corresponding to=1. It should be noted that in other exemplary embodiments, the signal Y (i) may have phases with other different angles, which is not a limitation of the present invention.
FIG. 6 is a schematic diagram of a bias control circuit according to an example embodiment of the invention. Referring to fig. 6, in an exemplary embodiment, the bias circuit 402 includes a current source I (REF) and switching circuits (also referred to as first switching circuits) 601 (1) to 601 (n). The switch circuit 601 (i) includes a switch SW (i) and a transistor N1 (i). i may be 1 to n. The transistor N1 (i) may be connected across the switch SW (i). In addition, the switching circuits 601 (1) to 601 (n) are connected in series with each other. The specific connection relationships of the switching circuits 601 (1) to 601 (n) can be shown in fig. 6.
In an exemplary embodiment, the signal VCS may be used to control the on state of each of the switches SW (1) -SW (n) to be on or off. Therefore, the switching circuits 601 (1) to 601 (n) can adjust the on states of the switches SW (1) to SW (n) according to the signal VCS to adjust the Bias voltage V (Bias)'. For example, by increasing or decreasing the total number of turned-on ones of the switches SW (1) to SW (n), the voltage value of the Bias voltage V (Bias)' may be changed accordingly. In addition, the filter circuit 403 may include an RC circuit composed of at least one resistor R and at least one capacitor C, as shown in fig. 6. The Bias voltage V (Bias)' may be filtered by the filter circuit 403 to generate the Bias voltage V (Bias).
Fig. 7 is a schematic diagram of a phase interpolation circuit according to an exemplary embodiment of the invention. Referring to fig. 7, in an exemplary embodiment, the phase interpolation circuit 43 includes a driving circuit 71 and a phase interpolator 72. The driving circuit 71 is connected to the phase interpolator 72. The driving circuit 71 receives the signal PCS (2) and the Bias voltage V (Bias) and provides a current I (X) according to the signal PCS (2) and the Bias voltage V (Bias) I ) And I (X) Q ) To phase interpolator 72.
To a range ofIn the example embodiment, the driving circuit 71 includes transistors N2 (0) to N2 (m), N3 (0) to N3 (m), and N4 (0) to N4 (m). The signal PCS (2) may comprise a plurality of sub-signals S (0) -S (m) and Sb (0) -Sb (m). The sub-signals S (0) -S (m) may be provided to the gate terminals of the transistors N3 (0) -N3 (m), respectively, to adjust the on-state of each of the transistors N3 (0) -N3 (m). The sub-signals Sb (0) -Sb (m) may be provided to the gate terminals of the transistors N4 (0) -N4 (m), respectively, to adjust the on state of each of the transistors N4 (0) -N4 (m). In addition, the Bias voltage V (Bias) may be provided to the gate terminals of the transistors N2 (0) to N2 (m) to adjust the on state of each of the transistors N2 (0) to N2 (m). Specific connection relationships of the transistors N2 (0) to N2 (m), N3 (0) to N3 (m), and N4 (0) to N4 (m) may be as shown in fig. 7, and the present invention is not limited thereto. Thus, the driving circuit 71 can adjust the currents I (X) according to the sub-signals S (0) to S (m) and Sb (0) to Sb (m), respectively I ) And I (X) Q ) In addition, the current I (X) can be further increased or decreased according to the variation of the Bias voltage V (Bias) I ) And I (X) Q ) Is set in the above-described range).
Phase interpolator 72 may be used to receive current I (X I ) And I (X) Q ) And according to the current I (X I ) And I (X) Q ) Generating a signal CLK. It should be noted that in the operation of generating the signal CLK, the current I (X I ) And I (X) Q ) Can influence the parameter a in the equation (1.3) respectively 1 And a 2 . For example, parameter a 1 Can be positively correlated with current I (X I ) And parameter a 2 Can be positively correlated with current I (X Q ) Is set in the above-described range). Alternatively, taking FIG. 5 as an example, the current I (X) is adjusted (e.g., increased) by the Bias voltage V (Bias) I ) And I (X) Q ) Parameter a 1 (i) And a 2 (i) Can be automatically adjusted (e.g., enlarged). Thus, the signal Y (i) generated by the phase interpolator 72 can be more approximate to the ideal condition, condition a 1 (i) 2 +a 2 (i) 2 Circular boundary 501 corresponding to=1.
FIG. 8 is a schematic diagram of a clock data recovery circuit according to an example embodiment of the invention. Referring to fig. 8, in an exemplary embodiment, the clock data recovery circuit 80 includes a phase detection circuit 81, a phase adjustment circuit 82, and a signal generation circuit 83. The signal generating circuit 83 may include the signal generating circuit 10 of fig. 1 or the signal generating circuit 40 of fig. 4.
The phase detection circuit 81 may be configured to receive a signal (also referred to as a first signal or a DATA signal) DATA and a signal (also referred to as a clock signal or a restore clock signal) CLK. The phase detection circuit 81 may detect a phase relative relationship (e.g., a phase difference) between the signal DATA and the signal CLK and generate a signal (also referred to as a phase signal) PS. For example, the signal PS may reflect that at some point in time, the phase of the signal DATA is the phase of the leading or trailing signal CLK. For example, the signal PS may include a first signal and a second signal. The first signal may reflect the phase of the signal DATA leading the phase of the signal CLK. The second signal may reflect the phase of the signal DATA and the phase of the signal CLK.
The phase adjustment circuit 82 is connected to the phase detection circuit 81 and the signal generation circuit 83. The phase adjustment circuit 82 may generate a signal (also referred to as a phase control signal) PAS based on the signal PS. For example, the phase adjustment circuit 82 may generate the signal PAS based on the number and/or frequency of occurrences of the first signal and/or the second signal in the signal PS. For example, the signal PAS may be used to instruct the signal generating circuit 83 to generate the signal CLK with a specific phase.
In an exemplary embodiment, the clock DATA recovery circuit 80 gradually synchronizes the phase of the signal CLK with the phase of the signal DATA through the common operation of the phase detection circuit 81, the phase adjustment circuit 82 and the signal generation circuit 83. When the phase of the signal DATA changes, the clock DATA recovery circuit 80 can again keep the phase of the signal CLK in synchronization with the phase of the signal DATA. In an exemplary embodiment, the operation of synchronizing the phase of the signal CLK with the phase of the signal DATA is also referred to as phase locking. In an example embodiment, the signal generating circuit 83 of fig. 8, the signal generating circuit 10 of fig. 1, and/or the signal generating circuit 40 of fig. 4 may also be referred to as a phase interpolator module or a phase interpolation circuit module.
In an example embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4, and/or the clock data recovery circuit 80 of fig. 8 may be disposed in a memory storage device. In another exemplary embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4 and/or the clock data recovery circuit 80 of fig. 8 may be provided in other types of electronic devices, but are not limited to memory storage devices.
FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 9, the memory storage device 90 is, for example, a memory storage device such as a solid state disk (Solid State Drive, SSD) including a rewritable nonvolatile memory module 93. The memory storage device 90 may be used with a host system that may write data to the memory storage device 90 or read data from the memory storage device 90. For example, reference to a host system is to be any system that can cooperate with the memory storage device 90 to store data, such as a desktop computer, a notebook computer, a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, among others.
The memory storage device 90 includes a connection interface unit 91, a memory control circuit unit 92, and a rewritable nonvolatile memory module 93. The connection interface unit 91 is used to connect the memory storage device 90 to a host system. In an exemplary embodiment, the connection interface unit 91 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 91 may be compliant with the parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, the high-speed peripheral component interface (Peripheral Component Interconnect Express, PCI Express) standard, the universal serial bus (Universal Serial Bus, USB) standard, or other suitable standards. The connection interface unit 91 may be packaged in one chip with the memory control circuit unit 92, or the connection interface unit 1001 may be disposed outside a chip including the memory control circuit unit 92.
The memory control circuit unit 92 is used for performing operations such as writing, reading and erasing of data in the rewritable nonvolatile memory module 93 according to instructions of the host system. In an example embodiment, the memory control circuit unit 92 is also referred to as a memory controller or a flash memory controller.
The rewritable nonvolatile memory module 93 is connected to the memory control circuit unit 92 and is used to store data written by the host system. The rewritable nonvolatile memory module 93 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
In an example embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4, and/or the clock data recovery circuit 80 of fig. 8 may be disposed in the connection interface unit 91, the memory control circuit unit 92, and/or the rewritable nonvolatile memory module 93.
It should be noted that the electronic circuit structures shown in fig. 1, 4 and 6-8 are only schematic diagrams of the signal generating circuit and the clock data recovery circuit in some exemplary embodiments, and are not meant to limit the present invention. In applications not mentioned in part, more electronic components may be added to the signal generating circuit and/or the clock data recovery circuit or replace part of the electronic components to provide additional, identical or similar functionality. In addition, in some applications not mentioned, the circuit layout and/or the element connection relationship inside the signal generating circuit and/or the clock data recovery circuit may be changed appropriately to meet the practical requirements.
Fig. 10 is a flowchart illustrating a signal generation method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a phase control signal is generated according to a phase adjustment signal. In step S1002, a bias voltage is generated according to the phase control signal. In step S1003, a clock signal is generated according to the phase control signal and the bias voltage. It should be noted that the bias voltage is used to adjust the current of the phase interpolation circuit to correct the error of the clock signal.
However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.
In summary, after generating the bias voltage according to the phase control signal, the bias voltage can be used to adjust the current of the phase interpolation circuit, so as to effectively correct the clock signal generated by the phase interpolation circuit. For example, in one exemplary embodiment, the adjusted bias voltage may be used to increase the current of the phase interpolation circuit so that the waveform of the clock signal generated by the phase interpolation more approximates a perfect waveform.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (18)
1. A signal generating circuit comprising:
the phase control circuit is used for generating a phase control signal according to the phase adjustment signal;
a bias control circuit connected to the phase control circuit and configured to generate a bias voltage according to the phase control signal; and
a phase interpolation circuit connected to the phase control circuit and the bias control circuit for generating a clock signal according to the phase control signal and the bias voltage,
wherein the bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal,
wherein the bias voltage adjusts the voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage adjusts the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
2. The signal generating circuit of claim 1, wherein the bias control circuit comprises:
an encoding circuit connected to the phase control circuit and configured to generate a bias control signal according to the phase control signal; and
and the bias circuit is connected to the coding circuit and used for generating a first bias voltage according to the bias control signal.
3. The signal generating circuit of claim 2, wherein the bias circuit comprises:
a current source; and
at least one switch circuit connected in series to the current source and used for responding to the bias control signal to adjust the conduction state of the at least one switch circuit so as to adjust the bias voltage.
4. The signal generating circuit of claim 2, wherein the bias control circuit further comprises:
and the filter circuit is connected to the bias circuit and the phase interpolation circuit and is used for filtering the first bias voltage to generate the bias voltage.
5. The signal generating circuit of claim 1, wherein the phase interpolation circuit comprises:
a driving circuit; and
a phase interpolator connected to the driving circuit,
wherein the driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and
the phase interpolator is used for generating the clock signal according to the current.
6. The signal generating circuit according to claim 5, wherein the bias voltage affects a current value of the current.
7. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable nonvolatile memory module;
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module; and
a clock data recovery circuit disposed in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit,
wherein the clock data recovery circuit comprises a signal generation circuit,
the signal generating circuit is used for generating a phase control signal according to the phase adjustment signal,
the signal generating circuit is further used for generating a bias voltage according to the phase control signal,
the signal generating circuit is further configured to generate a clock signal according to the phase control signal and the bias voltage, and
the bias voltage is used for adjusting the current of a phase interpolation circuit in the signal generating circuit to correct the error of the clock signal,
wherein the bias voltage adjusts the voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage adjusts the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
8. The memory storage device of claim 7, wherein the signal generation circuit comprises:
the encoding circuit is used for generating a bias voltage control signal according to the phase control signal; and
and the bias circuit is connected to the coding circuit and used for generating a first bias voltage according to the bias control signal.
9. The memory storage device of claim 8, wherein the bias circuit comprises:
a current source; and
at least one switch circuit connected in series to the current source and used for responding to the bias control signal to adjust the conduction state of the at least one switch circuit so as to adjust the bias voltage.
10. The memory storage device of claim 8, wherein the signal generation circuit further comprises:
and the filter circuit is connected to the bias circuit and used for filtering the first bias voltage to generate the bias voltage.
11. The memory storage device of claim 7, wherein the signal generation circuit comprises:
a driving circuit; and
a phase interpolator connected to the driving circuit,
wherein the driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and
the phase interpolator is used for generating the clock signal according to the current.
12. The memory storage device of claim 11, wherein the bias voltage affects a current value of the current.
13. A signal generation method for a memory storage device, the signal generation method comprising:
generating a phase control signal according to the phase adjustment signal;
generating a bias voltage according to the phase control signal; and
generating a clock signal according to the phase control signal and the bias voltage,
wherein the bias voltage is used for adjusting the current of the phase interpolation circuit to correct the error of the clock signal,
wherein the bias voltage adjusts the voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage adjusts the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
14. The signal generating method according to claim 13, wherein the step of generating the bias voltage according to the phase control signal comprises:
generating a bias control signal according to the phase control signal; and
and generating a first bias voltage according to the bias control signal.
15. The signal generating method of claim 14, wherein generating the first bias voltage according to the bias control signal comprises:
and adjusting the conduction state of at least one switch circuit to adjust the bias voltage in response to the bias control signal.
16. The signal generating method according to claim 14, wherein the step of generating the bias voltage according to the phase control signal further comprises:
the first bias voltage is filtered to produce the bias voltage.
17. The signal generating method according to claim 13, wherein the step of generating the clock signal according to the phase control signal and the bias voltage comprises:
providing the current to a phase interpolator based on the phase control signal and the bias voltage; and
the clock signal is generated by the phase interpolator based on the current.
18. The signal generating method according to claim 17, wherein the bias voltage affects a current value of the current.
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