KR20240019004A - Memory module adjusting inter-rank clock timing, memory system and training method thereof - Google Patents

Abstract

The memory module according to the present invention includes a first memory device constituting a first rank, and a second memory device constituting a second rank that shares command/address signals and clock signals with the first memory device, The first memory device and the second memory device receive command/address signals and clock signals in a matched type, and the first memory device has a variable delay for adjusting the delay of the received clock signal. Contains lines.

Description

Memory module for adjusting inter-rank timing, memory system, and training method thereof {MEMORY MODULE ADJUSTING INTER-RANK CLOCK TIMING, MEMORY SYSTEM AND TRAINING METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more specifically, to a memory module that adjusts inter-rank timing, a memory system, and a training method thereof.

Recently, various mobile devices and electronic devices such as smartphones, desktop computers, laptop computers, tablet PCs, and wearable devices are widely used. These electronic devices usually include semiconductor memory devices for storing data. As an example of a semiconductor memory device, a dynamic random access memory (DRAM) device, which is a volatile memory, stores data using charges stored in a capacitor.

In general, memory modules provided as low-power mobile memory can be divided into two or more ranks. That is, in the case of a dual rank structure, a plurality of semiconductor memory devices mounted on the substrate of the memory module are classified into two ranks, and semiconductor memory devices belonging to the same rank can be accessed simultaneously. In the end, rank may mean a unit through which a memory controller inputs and outputs data to semiconductor memory devices. For example, if single rank has a 64-bit data transmission width, dual rank may have a data transmission width twice that of single rank.

With the trend toward higher capacity and higher speed, the signal integrity (SI) characteristics of commands/addresses (CA) input at high speeds have deteriorated. In particular, in multi-rank systems, it is becoming increasingly difficult to achieve signal integrity (SI) depending on the distribution of characteristics between ranks. To overcome this, the timing of the command/address (CA) clock for each rank can be individually controlled in the memory controller, but this reduces performance and places a burden on related companies.

The purpose of the present invention is to provide a matched type multi-rank memory module capable of compensating for inter-rank clock skew, a memory system, and a training method thereof.

The memory module for achieving the above purpose includes a first memory device constituting a first rank, and a second memory device constituting a second rank that shares a command/address signal and a clock signal with the first memory device. However, the first memory device and the second memory device receive command/address signals and clock signals in a matched type, and the first memory device is configured to adjust the delay of the received clock signal. Contains variable delay lines.

The training method of a matched multi-rank memory module sharing a command/address signal and a clock signal to achieve the above purpose includes a method for checking whether the command/address signal and the clock signal for the first rank match. 1. Performing command bus training, performing second command bus training to check whether the command/address signal and the clock signal for the second rank match, of the first and second command bus training Checking the margin of the command/address signal of each of the first rank and the second rank using the result, and determining the margin of the command/address signal within the first rank or the second rank according to the margin of the command/address signal. and adjusting the delay of the clock signal.

A memory system for achieving the above purpose includes a memory controller that transmits a signal through a first bus and a clock signal through a second bus, and a first rank memory that shares the first bus and the second bus. and a memory module including a second rank memory, wherein the first rank memory or the second rank memory includes a variable delay line for internally variably delaying the clock signal received through the second bus. do.

According to the above-described embodiment of the present invention, inter-rank clock skew can be effectively compensated for in a matched-type multi-rank memory module in which each rank shares a command/address (CA) signal and a clock signal (CK).

1 is a block diagram briefly showing the structure of a memory system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the memory system of FIG. 1 in more detail.
FIG. 3 is a block diagram showing a simplified structure of the memory controller of FIG. 2.
FIG. 4 is a block diagram briefly showing the configuration of the memory device of FIG. 2.
FIG. 5 is a circuit diagram briefly showing an example structure of the clock delay line of FIG. 4.
Figure 6 is a timing diagram illustrating a command bus training (CBT) method according to an embodiment of the present invention.
Figure 7 is a diagram showing the results of command bus training (CBT) for multi-rank memory devices of the present invention.
Figure 8 is a flowchart briefly showing a command bus training (CBT) method according to an embodiment of the present invention.
Figure 9 is a block diagram briefly showing a memory system according to another embodiment of the present invention.
Figure 10 is a cross-sectional view showing the configuration of a memory system according to another embodiment of the present invention.
Figure 11 is a block diagram showing a memory system according to another embodiment of the present invention.
Figure 12 is a flow chart briefly showing a command bus training (CBT) method of a multi-rank memory system according to an embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are to be regarded as providing additional explanation of the claimed invention. Reference signs are indicated in detail in preferred embodiments of the invention, examples of which are indicated in the reference drawings. Wherever possible, the same reference numerals are used in the description and drawings to refer to the same or similar parts.

Hereinafter, DRAM will be used as an example of a semiconductor memory device to explain the features and functions of the present invention. However, those skilled in the art will readily understand other advantages and capabilities of the present invention based on what is described herein. The present invention may be implemented or applied through other embodiments. Moreover, the detailed description may be modified or changed according to viewpoints and applications without significantly departing from the scope, technical spirit and other purposes of the present invention.

1 is a block diagram briefly showing the structure of a memory system according to an embodiment of the present invention. Referring to FIG. 1 , the memory system 1000 includes a memory controller 1100 and a memory module 1500. The memory module 1500 includes memory devices 1200 and 1300 constituting two ranks.

The memory controller 1100 may perform an access operation to write data to the memory module 1500 or read data stored in the memory module 1500. The memory controller 1100 may generate a command (CMD) and an address (ADDR) for writing data to the memory module 1500 or reading data stored in the memory module 1500. The memory controller 1100 may be at least one of a chipset for controlling the memory module 1500, a system-on-chip (SoC) such as a mobile application processor (AP), a CPU, or a GPU.

The memory module 1500 includes memory devices 1200 and 1300 corresponding to multi-ranks (Rank0 and Rank1). That is, the memory device 1200 constitutes the first rank (Rank0), and the memory device 1300 constitutes the second rank (Rank1). Memory rank refers to a plurality of memory devices or memory chips that receive and respond to a common command/address (CA) from the memory controller 1100.

Memory devices of the ranks generally share at least one of a data bus (DQ), a command/address (CA) bus, and clock signals (CKt, CKc) used as strobe signals of the command/address (CA). In an embodiment of the present invention, the memory devices 1200 and 1300 each share a command/address (CA) bus and clock signals (CKt and CKc), and the data bus (DQ) uses a chip select signal (Chip Select: hereinafter, It is assumed that it is allocated by CS).

The first memory device 1200 constitutes the first rank (Rank0). The second memory device 1300 constitutes the second rank (Rank1). To configure multi-rank, a command/address (CA) signal is transmitted through at least one pad (Pa0) of the first memory device 1200. The same command/address (CA) signal is connected to at least one pad (Pb0) of the second memory device 1300 via the pad (Pa0) of the first memory device 1200. Electrically, the command/address signal CA is connected in parallel to the pads Pa0 and Pb0 of each of the memory devices 1200 and 1300. However, physically, the memory devices 1200 and 1300 may have different signal transmission characteristics as they are connected by wire bonding. Although the pad Pa0 and the pad Pb0 are each shown as one, it will be well understood that there may be two or more pads depending on the bit width of the command/address signal CA. Reception of the command/address signal (CA) and clock signal (CKt, CKc) of each of the memory devices 1200 and 1300 is provided in a matched type structure. That is, the paths of the command/address signal (CA) and clock signals (CKt, CKc) of each of the memory devices 1200 and 1300 are provided with the same delay size.

To configure multi-rank, the clock signals CKt and CKc, each transmitted in the form of a differential signal, are transmitted to the first memory device 1200 through the pads Pa1 and Pa2. The clock signals (CKt, CKc) can be used as strobe signals of the command/address signal (CA). Additionally, the clock signals CKt and CKc are connected to the pads Pb1 and Pb2 of the second memory device 1300 via the pads Pa1 and Pa2 of the first memory device 1200. The clock signals CKt and CKc are also electrically connected in parallel to the pads Pa1, Pa2, Pb1, and Pb2 of the memory devices 1200 and 1300, respectively. However, physically, the clock signal (CKt, CKc) transmission characteristics of the first memory device 1200 and the second memory device 1300 may vary depending on the wire connection.

The memory device (eg, 1300) of the present invention may include a controllable variable delay line 1340. The memory controller 1100 performs command bus training (CBT) for each rank. The memory controller 1100 may adjust the variable delay line 1340 of one rank (for example, Rank1) according to the command bus training (CBT) result so that each of the two ranks operates at optimal clock timing. That is, if there is a skew in the command/address signal (CA) received from the first memory device 1200 and the second memory device 1300, the variable delay line 1340 of the second memory device 1300 ) can be adjusted to compensate for the skew. Through this training, each rank can receive a command/address signal (CA) with optimal clock timing.

To detect whether the clock signals CKt and CKc and the command/address signal CA are aligned, the memory system 1000 may support a command bus training (CBT) mode. That is, the memory controller 1100 may perform bus training on the command bus when power is supplied to the memory module 1500 or during an initialization operation. The memory controller 1100 may perform command bus training (CBT) for each of the ranks (Rank0 and Rank1) to check the margin of the command/address signal (CA). Additionally, the skew may be compensated by adjusting the variable delay line (eg, 1340) of one of the ranks (Rank0 and Rank1) based on the margin of the command/address signal (CA).

The memory system 1000 may be implemented to be included in a personal computer (PC) or mobile device. Mobile devices include laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, and portable portable media (PMPs). Multimedia Player, PND (Personal Navigation Device or Portable Navigation Device), handheld game console, Mobile Internet Device (MID), wearable computer, Internet of Things (IoT) device , can be implemented as an Internet of Everything (IoE) device, or drone.

Each of the memory devices 1200 and 1300 may include a memory cell array including a plurality of memory cells. In one embodiment, the memory cell may be a volatile memory cell, and each of the memory devices 1200 and 1300 may include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, and DDR SDRAM. (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power DDR) SDRAM, GDDR (Graphic DDR) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc.

In another embodiment, the memory cell may be a non-volatile memory cell, and each of the memory devices 1200 and 1300 may include, but are not limited to, EEPROM (non-volatile memory such as an Electrically Erasable Programmable Read-Only Memory), flash memory, etc. (flash memory), PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory) Access Memory), etc. Hereinafter, each of the memory devices 1200 and 1300 will be described as being DRAM, but it will be well understood that the technical idea of the present disclosure is not limited thereto.

As described above, the memory system 1000 of the present invention includes a memory module 1500 with a multi-rank structure. And the memory module 1500 receives the command/address signal (CA) and clock signals (CKt, CKc) in a matched manner. The memory controller 1100 checks the skew of the command/address signal (CA) and clock signals (CKt, CKc) commonly used for each rank through command bus training (CBT). Additionally, at least one variable delay line among the memory devices 1200 and 1300 may be adjusted to compensate for the checked skew. Through this, the command/address signal (CA) and clock signals (CKt, CKc) can be transmitted without separate timing control when switching ranks in a memory system with a multi-rank structure. Accordingly, easy control is possible on the memory controller 1100 side and a high-performance matched-type multi-rank memory system can be provided.

FIG. 2 is a block diagram showing the memory system of FIG. 1 in more detail. Referring to FIG. 2 , the memory system 1000 includes a memory controller 1100 and memory devices 1200 and 1300. Memory devices 1200 and 1300 constitute the memory module 1500 of FIG. 1 . Each of the memory devices 1200 and 1300 constitutes a first rank (Rank0) and a second rank (Rank1).

The memory controller 1100 controls the memory devices 1200 and 1300 in a multi-rank manner. That is, the memory controller 1100 commonly applies the command/address signal (CA) bus and clock signals (CKt and CKc) to the memory devices 1200 and 1300. As described in FIG. 1 , the memory devices 1200 and 1300 are connected to share the command/address signal CA and the clock signals CKt and CKc through pads connected in parallel. Additionally, the memory controller 1100 can set the variable delay line 1240 or 1340 provided inside the memory devices 1200 and 1300 through command bus training (CBT). Using this function, the memory controller 1100 can remove or reduce skew that occurs due to differences in characteristics of command/address signals (CA) or clock signals (CKt, CKc) between ranks.

The memory devices 1200 and 1300 may be configured in a dual rank format as shown. However, the number of memory devices 1200 and 1300 may be increased to configure 4-rank or higher ranks of multiple channels. Each of the memory devices 1200 and 1300 receives a common command/address signal (CA) and clock signals (CKt and CKc) from the memory controller 1100. And each of the memory devices 1200 and 1300 uses a matched type command/address signal (CA) and clock signal (CKt, CKc) reception method. That is, each of the memory devices 1200 and 1300 is provided in a form in which the delays of the reception path of the command/address signal (CA) and the reception path of the clock signals (CKt and CKc) are matched.

However, the memory devices 1200 and 1300 according to the present invention include delay lines 1230, 1240, 1330, and 1340 for command/address signals (CA) and clock signals (CKt and CKc). The memory controller 1100 may perform command bus training (CBT) on each of the memory devices 1200 and 1300. Additionally, the margin of the command/address signal (CA) of each of the memory devices 1200 and 1300 may be checked based on the results of command bus training (CBT). Additionally, the delay lines of the clock signals CKt and CKc may be adjusted to match the timing of the command/address signal CA based on the margin of the command/address signal CA of each of the memory devices 1200 and 1300. . To this end, the variable delay lines 1240 and 1340 of the clock signals CKt and CKc may be set using a fuse or a mode register set (MRS).

The first memory device 1200 receives the command/address signal (CA) transmitted from the memory controller 1100 using the first comparator 1210. That is, the first comparator 1210 compares the received command/address signal (CA) and the reference voltage (VREF) and performs sampling. The command/address signal (CA) sampled by the first comparator 1210 will be transmitted to the data input terminal (D) of the first flip-flop 1250 via the first delay line 1230.

Clock signals (CKt, CKc) transmitted from the memory controller 1100 are received by the second comparator 1220. The second comparator 1220 converts the clock signals CKt and CKc delivered in the form of differential signals into an internal clock signal CK0 in the CMOS form. That is, the second comparator 1220 will receive the clock signals CKt and CKc as a function of a common mode-CMOS (CML to CMOS: C2C) converter. The internal clock signal CK0 converted to the CMOS level by the second comparator 1220 is transmitted to the clock input terminal of the first flip-flop 1250 via the variable delay line 1240. The command/address signal CA is sampled by the first flip-flop 1250 in synchronization with the internal clock signal CK0 provided from the variable delay line 1240. The sampled command/address signal (CA) is transmitted to the first command decoder 1260 or an address decoder (not shown).

The internal clock signal CK0 output from the second comparator 1220 is transmitted to the first flip-flop 1250 via the first variable delay line 1240. The first variable delay line 1240 can be delayed controlled in various ways. That is, the first variable delay line 1240 can be set using a fuse program or mode register set (MRS). Skew of the command/address signal (CA) between ranks can be compensated for by setting the first variable delay line 1240.

The second memory device 1300 constituting the second rank (Rank1) also includes substantially the same configuration as the first memory device 1200. That is, the second memory device 1300 includes a third comparator 1310, a fourth comparator 1320, a second delay line 1330, a second variable delay line 1340, a second flip-flop 1350, and It may include a second instruction decoder 1360. Accordingly, description of the functions of the components of the second memory device 1300 will be omitted.

However, command bus training (CBT) is performed for each of the memory devices 1200 and 1300 or ranks (Rank0 and Rank1). In order to adjust the skew of the command/address signal (CA) between ranks based on the results of command bus training (CBT), the variable delay lines 1240 and 1340 are adjusted among the memory devices 1200 and 1300. It can only be applied to one or the other.

The memory system 1000 of the present invention includes multi-rank memory devices 1200 and 1300 that receive a command/address signal (CA) and a clock signal (CKt and CKc) in a matched manner. And the skew of the command/address signal (CA) or clock signal (CKt, CKc) that exists between these memory devices (1200, 1300) can be adjusted through adjustment of the variable delay line (1230 or 1340) provided inside one of them. can be compensated Through this training, each matched multi-rank can receive command/address signals (CA) with optimal clock timing.

FIG. 3 is a block diagram showing a simplified structure of the memory controller of FIG. 2. Referring to FIG. 3, the memory controller 1100 may include a command/address generator 1110, a flip-flop 1120, a clock generator 1130, clock drivers 1132 and 1134, and a timing controller 1140. there is. The memory controller 1100 may further include data operation logic such as a system on a chip (SoC) or a processor, but illustration and description of these will be omitted for simplicity of explanation.

The command/address generator 1110 generates commands and addresses for writing data to the memory devices 1200 and 1300 or reading data stored in the memory devices 1200 and 1300. For example, the command/address generator 1110 may generate a read command or a write command to access the memory device 1200. And the command/address generator 1110 will also generate addresses for reading or writing.

The flip-flop 1120 captures and outputs the command/address signal (CA) in synchronization with the clock signal (CLK) provided from the timing controller 1140. For example, a 4-bit wide command/address signal (CA[6:3]) may be output by the flip-flop 1120.

The clock generator 1130 generates clock signals (CKt, CKc) of designated frequencies. The clock generator 1130 may generate clock signals CKt and CKc for transmission of the command/address signal CA using the reference clock generated in the oscillator circuit. In addition, the clock generator 1130 may generate clock signals (WCKt and WCKc) for transmitting or receiving the data signal (DQ). The clock generator 1130 may be implemented as a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit, but is not limited thereto. Clock signals CKt and CKc from the clock generator 1130 will be commonly transmitted to the memory devices 1200 and 1300 through the clock drivers 1132 and 1134.

The timing controller 1140 synchronizes the clock signals CKt and CKc generated by the clock generator 1130 and the command/address signal CA. The timing controller 1140 can adjust the timing of the clock signals CKt and CKc to capture the command/address signal CA. That is, the command/address signal (CA) and the clock signal (CKt, CKc) can be aligned on the transmission side by the timing controller 1140.

The configuration of the memory controller 1100, which transmits a common command/address signal (CA) and clock signals (CKt, CKc) to the memory devices 1200 and 1300 forming the multi-rank above, has been briefly described. From the perspective of the memory controller 1100, it is a burden to separate the clock signals CKt and CKc by rank to compensate for the inter-rank skew of the command/address signal CA. Therefore, by using command bus training (CBT) for the matched memory devices 1200 and 1300 of the present invention, the signal integrity (SI) of the command/address signal (CA) can be increased without burdening the memory controller 1100. there is.

FIG. 4 is a block diagram exemplarily showing the configuration of the memory device of FIG. 2. Referring to FIG. 4, the advantages of the present invention will be explained by taking as an example the configuration of the first memory device 1200 corresponding to the first rank (Rank0) among memory devices constituting dual-rank. The first memory device 1200 includes comparators 1210 and 1220, a first delay line 1230, a first variable delay line 1240, a first flip-flop 1250, a first command decoder 1260, and a first command decoder 1260. 1 It may include an address decoder 1265, a first cell array 1270, a sense amplifier 1272, a data buffer 1274, a mode register set 1280, and a delay control logic 1290.

The first comparator 1210 receives the command/address signal (CA) transmitted from the memory controller 1100. The first comparator 1210 determines the signal level by comparing the command/address signal (CA) and the reference voltage (VREF). The determined signal level is transmitted to the first delay line 1230 as a sampled command/address signal (CA).

The second comparator 1220 receives clock signals CKt and CKc delivered in the form of differential signals. The clock signals CKt and CKc transmitted from the memory controller 1100 may be converted into an internal clock signal CK0 in CMOS format by the second comparator 1220. That is, the second comparator 1220 receives the clock signals (CKt, CKc) using the function of a common mode-CMOS (C2C) converter. The internal clock signal CK0 sampled by the second comparator 1220 and converted to a CMOS level is transmitted to the first variable delay line 1240.

The first delay line 1230 and the first variable delay line 1240 provide matched delays of the command/address signal (CA) and the clock signals (CKt and CKc), respectively. That is, the first delay line 1230 and the first variable delay line 1240 will be produced with a fixed optimally matched delay value. However, changes in delay characteristics may occur depending on the wire connections used to configure the multi-rank or the conductive lines of the printed circuit board (PCB). The first variable delay line 1240 of the present invention will be configured as a variable delay line to control the size of the delay.

The first flip-flop 1250 latches data at the input terminal (D) in response to an edge of the internal clock signal (CK0) transmitted via the first variable delay line 1240 and transfers it to the output terminal (Q). A command/address signal (CA) transmitted via the first delay line 1230 is provided to the input terminal (D) of the first flip-flop (1250). The command/address signal (CA) sampled from the first flip-flop 1250 is transmitted to the command decoder 1260 or the address decoder 1265.

The command decoder 1260 determines the input command by referring to the sampled command/address signal (CA). The command decoder 1260 may execute a control operation to write data into the cell array 1270 or a control operation to read data written into the cell array 1270 in response to a command provided from the outside. Additionally, the command decoder 1260 can write data to the mode register set 1280 according to commands and addresses provided from the outside. In the same way, address and other control signals provided through the command/address signal (CA) may be transmitted to the address decoder 1265. Then, the address decoder 1265 extracts the address and information signals through a decoding operation and delivers them to necessary components.

Write data transmitted through the data bus (DQ) is stored in the cell array 1270. Data stored in the cell array 1270 may be sensed through the sense amplifier 1272 and output to the outside through the data buffer 1274.

The mode register set 1280 sets an internal mode register in response to the MRS command and address for specifying the operation mode of the memory device 1200. In particular, the mode register set 1280 of the present invention allows commands for command bus training (CBT) to be written and executed. And, according to a request provided from the memory controller 1100 after command bus training (CBT), the mode register set 1280 can adjust the delay size of the first variable delay line 1240 composed of variable delay lines. To this end, the mode register set 1280 can control the delay control logic 1290.

The delay control logic 1290 may increase or decrease the delay of the first variable delay line 1240 according to information provided through the mode register set 1280. For example, the delay control logic 1290 may select the delay size in the first variable delay line 1240 according to the control of the mode register set 1280. Implementations of delay control logic 1290 may be provided in various ways. That is, the delay control logic 1290 may be implemented as a fuse option or control logic.

According to the first memory device 1200 described above, the delay of the internal clock CK0 generated from the received clock signals CKt and CKc can be adjusted. Through command bus training (CBT), skew of command/address signals (CA) between ranks can be detected. At this time, the memory controller 1100 maintains the signal integrity of the command/address signal (CA) of the multi-rank memory module (1500 (see FIG. 1)) by adjusting the delay of the internal clock (CK0) of one memory device. (SI) can be secured.

FIG. 5 is a circuit diagram briefly showing an example structure of the clock delay line of FIG. 4. Referring to FIG. 5, the first variable delay line 1240 uses a plurality of inverters (INV1 to INVn) as delay elements. That is, the first variable delay line 1240 may use one of the outputs (Out_1 to Out_n) of each of the plurality of inverters (INV1 to INVn) as the delayed output (CK0_j) of the internal clock (CK0). At this time, the output selected by the switch control signal (eg, SWn) is determined as the adjusted delay output (CK0_j) value. That is, one (eg, CK0_3) selected among the plurality of outputs (CK0_1 to CK0_n) can be used as a clock signal for capturing the command/address signal (CA). One selected among the plurality of outputs (CK0_1 to CK0_n) may be transmitted to the first flip-flop 1250 by the selected switch (SW1 to SWn).

In the above, a configuration using inverters and switches for the first variable delay line 1240 has been briefly described, but the present invention is not limited thereto. For example, the first variable delay line 1240 may use a plurality of flip-flops FF1 to FFn as delay elements. In addition, the second variable delay line 1340 included in the second memory device 1300 that configures the multi-rank may be configured substantially the same as the first variable delay line 1240.

Figure 6 is a timing diagram illustrating a command bus training (CBT) method according to an embodiment of the present invention. Referring to FIG. 6, the waveforms of signals exchanged between the memory controller 1100 and the memory device 1200 or 1300 during command bus training (CBT) are exemplarily shown. Hereinafter, command bus training (CBT) will be explained using the waveforms of signals exchanged between the memory controller 1100 and the memory device 1200 as an example.

As the chip select signal CS transitions to a high level, the first memory device 1200 is selected. And the clock signals (CKt, CKc) for transmitting the command/address signal (CA) begin to toggle. Then, it can be indicated that the chip select signal (CS) activated before T0 and the command/address signal (CA[6:0]) transmitted through the command/address bus are the mode register setting command (MRW). Then, the first memory device 1200 receives the mode register setting command MRW synchronized to the rising or falling edge of the clock signals CKt and CKc. The first memory device 1200 may set the received command bus training (CBT) mode in the mode register set 1280.

At point Ta1, toggling of data clock signals (WCKt, WCKc) begins. And at time Tb1, the data signal (DQ[7]) transitions to logic high in synchronization with the rising edge of the data clock signal (WCKt). Then, the memory device 1200 can enter the command bus training (CBT) mode.

Here, the data signal (DQ[7]) is a signal excluded from the one-to-one matching relationship with the command/address signal (CA[6:0]) among the data signals (DQ[7:0]) in command bus training (CBT) mode. am. In the command bus training (CBT) mode, each command/address signal (CA[6:0]) corresponds to each data signal (DQ[6:0]) and is output as a command bus training (CBT) signal. However, the data signal (DQ[7]) is not used to be output as a command bus training (CBT) signal. In other words, a data signal (DQ[7]) that is not used in the output signal of the command bus training (CBT) mode can be used as a signal to indicate entry into the command bus training (CBT) mode.

At point Te2, the chip select signal (CS) transitions to logic high. Then, the memory controller 1100 inputs a training pattern (PTN_A) to check the margin of the unit interval (hereinafter, UI) of the command/address signal (CA) of the first memory device 1200. At this time, the training pattern (PTN_A) is input in synchronization with the clock signals (CKt, CKc).

At time Tf0, a data signal (DQ[6:0]) according to the alignment characteristics of the input training pattern (PTN_A) and clock signals (CKt, CKc) is output. At this time, whether the data signal (DQ[6:0]) passes or fails is determined depending on the degree of alignment of the input training pattern (PTN_A) and the clock signals (CKt, CKc). The memory controller 1100 determines Pass or Fail by comparing the bit value of the training pattern (PTN_A) output as the data signal (DQ[6:0]) and the input training pattern. The memory controller 1100 compares the input bit value and the output bit value of the training pattern (PTN_A) and, if they are the same, determines it as a pass. On the other hand, the memory controller 1100 will determine it as a fail if the input bit value and output bit value of the training pattern (PTN_A) are different.

For command bus training (CBT), the input and output of the training pattern (PTN_A) described above may be performed multiple times while varying the timing of the training pattern (PTN_A). In another embodiment, the input and output of the training pattern (PTN_A) for command bus training (CBT) may be performed multiple times while varying the delays of the clock signals (CKt and CKc). When command bus training (CBT) for the first memory device 1200 is completed, the memory controller 1100 continues command bus training (CBT) according to the procedure described in the timing diagram for the second memory device 1300. will be.

Figure 7 is a diagram showing the results of command bus training (CBT) for the multi-rank memory of the present invention. Referring to FIG. 7, the relative position or margin of the training pattern (PTN_A) output according to the results of command bus training (CBT) for each rank with respect to the chip select signal (CS) is shown. Here, the first memory device 1200 constitutes the first rank (Rank0), and the second memory device 1300 constitutes the second rank (Rank1), so the memory devices 1200 and 1300 and the rank (Rank0) , Rank1) can be used interchangeably. That is, the first rank (Rank0) may refer to the first memory device 1200, and the second rank (Rank1) may refer to the second memory device 1300.

First, the results of command bus training (CBT) for the first rank (Rank0) are shown in the first column of the table. The characteristics of the command/address signal (CA) of the first rank (Rank0) are well aligned with the internal clock signal (CK0). Accordingly, the pass training pattern (PTN_A) output as a result of the CA sweep in the first rank (Rank0) is distributed in a balanced manner based on the center of the chip selection signal (CS). Here, CA Sweep refers to a training operation to determine the optimal input timing of the command bus. That is, for CA sweep, the memory controller 1100 (see FIG. 1) can input and output the training pattern PTN_A input to the command bus by varying the input timing multiple times. That is, the training pattern (PTN_A) input and output procedures of FIG. 7 can be executed multiple times by applying different input timings. In addition, the memory controller 1100 determines Pass or Fail according to the presence or absence of errors in the training patterns (PTN_A) corresponding to each output input timing. The input timing of the training patterns (PTN_A) is implemented with delays of different sizes within one input cycle (1tCK).

On the other hand, the results of Command Bus Training (CBT) for the second rank (Rank1) are shown in the second column of the table. The characteristics of the command/address signal (CA) of the second rank (Rank1) have skew with the internal clock signal (CK0). Accordingly, the pass training pattern (PTN_A) output as a result of the CA sweep is distributed in a skewed form based on the center of the chip selection signal (CS). That is, in order to increase the CA margin of the first rank (Rank0) and the second rank (Rank1), the internal clock signal (CK0) of the second rank (Rank1) is required to be delayed.

Considering the results of command bus training (CBT), it is necessary to delay the internal clock signal (CK0) of the second rank (Rank1). To this end, the memory controller 1100 may set the second variable delay line 1340 of the second memory device 1300 to increase the delay (+Delay) to a specific amount. As the delay (+Delay) of the internal clock signal through the second variable delay line 1340 increases, the margin of the command/address signal (CA) of the second rank (Rank1) may increase.

Figure 8 is a flowchart briefly showing a command bus training (CBT) method according to an embodiment of the present invention. Referring to FIG. 8, a sweep of the command/address signal (CA) is performed through command bus training (CBT) for each rank, and the variable delay line of one rank can be adjusted using the result. .

In step S110, the memory controller 1100 performs command bus training (CBT) for the first rank (Rank0). That is, the memory controller 1100 performs a sweep of the command/address signal (CA) by changing the input timing of the training pattern (PTN_A). In another embodiment, the input timing of the training pattern PTN_A may be fixed and a sweep of the command/address signal CA may be performed while changing the timing of the clock signals CKt and CKc.

In step S120, the memory controller 1100 checks the margin of the command/address signal (CA) for the first rank (Rank0). That is, the memory controller 1100 can check the margin of the command/address signal (CA) by comparing the input training pattern (PTN_A) and the output training pattern (PTN_A).

In step S130, the memory controller 1100 performs command bus training (CBT) for the second rank (Rank1). That is, the memory controller 1100 performs a sweep of the command/address signal (CA) while varying the input timing of the training pattern (PTN_A). Alternatively, the input timing of the training pattern (PTN_A) may be fixed and a sweep of the command/address signal (CA) may be performed while changing the timing of the clock signals (CKt and CKc).

In step S140, the memory controller 1100 checks the margin of the command/address signal (CA) for the second rank (Rank1). That is, the memory controller 1100 can check the margin of the command/address signal CA by comparing the training pattern PTN_A input to the second rank Rank1 with the training pattern PTN_A output.

In step S150, the memory controller 1100 compares the command/address signal (CA) margin of the first rank (Rank0) with the command/address signal (CA) margin of the second rank (Rank1). And the memory controller 1100 adjusts at least one clock delay line 1240 of the first rank (Rank0) and the second rank (Rank1) according to the comparison result.

Figure 9 is a block diagram briefly showing a memory system according to another embodiment of the present invention. Referring to FIG. 9 , the memory system 2000 includes a memory controller 2100 and memory devices 2200 and 2300. The memory devices 2200 and 2300 may each form a multi-rank memory module. That is, the memory devices 2200 and 2300 each configure two ranks (Rank0 and Rank1). Unlike the memory system 1000 of FIG. 2, the memory system 2000 shares the data signal DQ and the data clock signals WCKt and WCKc. Accordingly, the memory devices 2200 and 2300 may include a variable delay line 2240 or 2340 that can internally delay the data clock signals WCKt and WCKc.

The memory controller 2100 controls the memory devices 2200 and 2300 in a multi-rank manner. That is, the memory controller 1100 commonly applies the data signal DQ and the data clock signals WCKt and WCKc to the memory devices 2200 and 2300. The memory devices 2200 and 2300 may be connected to share the data signal DQ and the data clock signals WCKt and WCKc through pads connected in parallel. Additionally, the memory controller 2100 can set the variable delay line 2240 or 2340 provided inside the memory devices 2200 and 2300 through data bus training. Using this function, the memory controller 2100 can compensate for skew that occurs due to differences in characteristics of the data signal (DQ) or data clock signals (WCKt, WCKc) between ranks.

The memory devices 2200 and 2300 may be configured in a dual rank format as shown. However, the number of memory devices 2200 and 2300 may be increased to configure 4-rank or higher ranks of multiple channels. Each of the memory devices 2200 and 2300 receives a common command/address signal (CA) and clock signals (CKt and CKc) from the memory controller 2100. And each of the memory devices 2200 and 2300 uses a matched type reception method of the data signal (DQ) and data clock signal (WCKt, WCKc).

However, the memory devices 2200 and 2300 according to the present invention include variable delay lines 2240 and 2340 of the data clock signals WCKt and WCKc. The memory controller 2100 may perform data bus training for each of the memory devices 2200 and 2300. Additionally, the margin of the data signal DQ of each of the memory devices 2200 and 2300 may be checked based on the results of data bus training. Additionally, the variable delay lines of the data clock signals WCKt and WCKc may be adjusted based on the margin of the data signal DQ of each of the memory devices 2200 and 2300. To this end, the variable delay lines 2240 and 2340 of the data clock signals WCKt and WCKc may be set using a fuse or mode register.

The first memory device 2200 receives the data signal DQ transmitted from the memory controller 2100 using the first comparator 2210. That is, the first comparator 2210 compares the received data signal (DQ) and the reference voltage (VREF) and performs sampling. The data signal DQ sampled by the first comparator 2210 will be transmitted to the data input terminal (D) of the first flip-flop 2250 via the first data delay line 2230.

Data clock signals (WCKt, WCKc) transmitted from the memory controller 2100 are received by the second comparator 2220. The second comparator 2220 converts the data clock signals (WCKt, WCKc) delivered in the form of differential signals into signals in CMOS form. That is, the second comparator 2220 will receive the data clock signals (WCKt, WCKc) as a function of a common mode-CMOS (C2C) converter. It is converted to a CMOS level by the second comparator 2220 and transmitted to the clock input terminal of the first flip-flop 2250 via the first variable delay line 2240. The data signal DQ is sampled in synchronization with the data clock signals WCKt and WCKc by the first flip-flop 2250. The sampled data signal DQ is transmitted to the first data buffer 2260.

The data clock signals (WCKt, WCKc) received from the second comparator 2220 are transmitted to the first flip-flop 2250 via the first variable delay line 2240. The first variable delay line 2240 may be provided in a structure that allows control of the delay size through various means. That is, the first variable delay line 2240 can be set using a fuse program or mode register set (MRS). The skew of the data signal (DQ) between ranks is determined by setting the first variable delay line 2240 or the second variable delay line 2340 to adjust the size of the delay of the data clock signals (WCKt, WCKc). You can.

The second memory device 2300 constituting the second rank (Rank1) also includes substantially the same configuration as the first memory device 2200. That is, the second memory device 2300 includes a third comparator 2310, a fourth comparator 2320, a second data delay line 2330, a second variable delay line 2340, a second flip-flop 2350, And may include a second data buffer 2360. Accordingly, description of the functions of the components of the second memory device 2300 will be omitted.

However, data bus training is performed for each of the memory devices 2200 and 2300. In order to adjust the skew of the data signal (DQ) between ranks based on the results of data bus training, delay adjustment of the data clock signals (WCKt, WCKc) is performed only on one of the memory devices 2200 and 2300. It can be applied.

The memory system 2000 of the present invention includes multi-rank memory devices 2200 and 2300 that receive a data signal DQ and a data clock signal WCKt and WCKc in a matched manner. And the skew of the data signal DQ that exists between these memory devices 2200 and 2300 can be compensated for by adjusting the variable delay line 2230 or 2340 provided inside one of them. Through this training, each matched multi-rank can receive the data signal (DQ) with optimal clock timing.

Figure 10 is a cross-sectional view showing the configuration of a memory system according to another embodiment of the present invention. Referring to FIG. 10 , the memory system 3000 includes a memory controller 3100 and a memory module 3200. The memory module 3200 includes multi-layer memory devices 3210 and 3230 each configuring four ranks.

The memory controller 3100 may perform an access operation to write data to the memory module 3200 or read data stored in the memory module 3200. The memory controller 3100 may write data to the memory module 3200 or generate a command (CMD) and an address (ADDR) for reading data stored in the memory module 3200. The memory controller 3100 may be at least one of a chipset for controlling the memory module 3200, a system-on-chip (SoC) such as a mobile application processor (AP), a CPU, or a GPU.

The memory module 3200 includes a plurality of stacked memory devices corresponding to multi-ranks (Rank0, Rank1, Rank2, and Rank3). The four stacked memory devices 3210 may each share a command/address signal (CA) and clock signals (CKt and CKc) in a 2-rank structure. The four stacked memory devices 3210 may be connected to the memory controller 3100 in a structure in which two ranks each constitute one channel. That is, the first rank (Rank0) and the second rank (Rank1) among the memory devices 3210 may be connected through wire bonding to share the command/address signal (CA) and the clock signals (CKt and CKc). Additionally, the third rank (Rank2) and the fourth rank (Rank3) may be connected through wire bonding to share the command/address signal (CA) and clock signals (CKt and CKc). Memory devices 3230 may also be connected to the memory controller 3100 in the same rank structure as the memory devices 3210.

The memory devices 3210 may adjust the delay of the internal clock signals CKt and CKc through command bus training (CBT) in the manner described above. To this end, each of the memory devices 3210 may include a variable delay line (not shown) for setting the delay of the internal clock signal CK0.

Figure 11 is a block diagram showing a memory system according to another embodiment of the present invention. Referring to FIG. 11 , the memory system 4000 includes a memory controller 4100 and memory devices 4200, 4300, 4400, and 4500. Memory devices 4200, 4300, 4400, and 4500 constitute four ranks (Rank0, Rank1, Rank2, and Rank3).

The memory controller 4100 controls the memory devices 4200, 4300, 4400, and 4500 in a 4-rank manner. That is, the memory controller 4100 commonly applies the command/address signal (CA) bus and clock signals (CKt and CKc) to the memory devices 4200, 4300, 4400, and 4500. The memory devices 4200, 4300, 4400, and 4500 are connected to share a command/address signal (CA) and clock signals (CKt, CKc) through pads connected in parallel. And the memory controller 4100 can set one or more of the variable delay lines 4240, 4340, 4440, and 4540 provided inside the memory devices 4200, 4300, 4400, and 4500 through command bus training (CBT). there is. Using this function, the memory controller 4100 can remove or reduce skew that occurs due to differences in characteristics of command/address signals (CA) or clock signals (CKt, CKc) between ranks.

Each of the memory devices 4200, 4300, 4400, and 4500 receives a common command/address signal (CA) and clock signals (CKt, CKc) from the memory controller 4100. And each of the memory devices 4200, 4300, 4400, and 4500 uses a matched type command/address signal (CA) and clock signal (CKt, CKc) reception method. That is, each of the memory devices 4200, 4300, 4400, and 4500 is provided in a form in which the delays of the reception path of the command/address signal (CA) and the reception path of the clock signals (CKt and CKc) are matched.

The memory devices 4200, 4300, 4400, and 4500 according to the present invention include internal variable delay lines 4240, 4340, 4440, and 4540 that can adjust the delay of the clock signals CKt and CKc. The memory controller 4100 may perform command bus training (CBT) on each of the variable delay lines 4240, 4340, 4440, and 4540. And based on the results of command bus training (CBT), the margin of the command/address signal (CA) of each of the memory devices 4200, 4300, 4400, and 4500 may be checked. In order to match the timing of the command/address signal (CA) based on the margin of the command/address signal (CA) of each of the memory devices (4200, 4300, 4400, and 4500), a delay line of the clock signal (CKt, CKc) is provided. It can be adjusted. To this end, at least one of the variable delay lines 4240, 4340, 4440, and 4540 may be adjusted using a fuse or mode resistor. The configuration of each of the memory devices 4200, 4300, 4400, and 4500 is substantially the same as that of FIG. 4 described above.

The memory system 4000 of the present invention includes 4-rank memory devices 4200, 4300, 4400, and 4500 that receive a command/address signal (CA) and a clock signal (CKt, CKc) in a matched manner. And the skew of the command/address signal (CA) or clock signal (CKt, CKc) existing between these memory devices (4200, 4300, 4400, and 4500) is at least one of the variable delay lines (4240, 4340, 4440, 4540) can be compensated through adjustment. Through this training, each matched multi-rank can receive command/address signals (CA) with optimal clock timing.

Figure 12 is a flowchart briefly showing a command bus training (CBT) method of a multi-rank memory system according to an embodiment of the present invention. Referring to FIG. 12, a sweep of the command/address signal (CA) is performed through command bus training (CBT) for each rank, and the variable delay line of at least one rank can be adjusted using the result. .

In step S210, initialization of the rank identification number for command bus training (CBT) is performed. For example, the rank identification number (i, i is an integer greater than 0) may be initialized to '0'.

In step S220, the memory controller 4100 performs command bus training (CBT) for the first rank (Rank0). That is, the memory controller 4100 performs a sweep of the command/address signal (CA) by changing the input timing of the training pattern (PTN_A). In another embodiment, the input timing of the training pattern PTN_A may be fixed and a sweep of the command/address signal CA may be performed while changing the timing of the clock signals CKt and CKc.

In step S230, the memory controller 4100 checks the margin of the command/address signal (CA) for the first rank (Rank0) from the result of the command bus training (CBT) performed in step S220. That is, the memory controller 4100 can check the margin of the command/address signal (CA) by comparing the input training pattern (PTN_A) and the output training pattern (PTN_A).

In step S240, the memory controller 4100 checks whether the command bus training (CBT) performed in the previous step corresponds to the last rank. If the rank to which steps S220 and S230 are applied corresponds to the last rank (Yes direction), the procedure moves to step S250. On the other hand, if the rank to which steps S220 and S230 are applied does not correspond to the last rank (No direction), the procedure moves to step S245. In step S245, the rank identification number (i) increases. The procedure will then return to step S220 and Command Bus Training (CBT) for the next rank will continue.

In step S250, the memory controller 4100 determines the adjustment size of the clock signals CKt and CKc by referring to the results of command bus training (CBT) for each of the plurality of ranks. For example, the memory controller 4100 may determine an adjustment size for one or more of the variable delay lines 4240, 4340, 4440, and 4540.

In step S260, the memory controller 4100 adjusts one or more of the variable delay lines 4240, 4340, 4440, and 4540 to the delay size determined in step S250. To adjust the delay size of the variable delay lines 4240, 4340, 4440, and 4540, the memory controller 4100 may use a mode register set (MRS) command.

Above, a method of applying command bus training (CBT) of the present invention to a multi-rank system was briefly described. By applying the command bus training (CBT) of the present invention, the skew of the command/address signal (CA) and clock signals (CKt, CKc) of the multi-rank memory system provided in a matched type can be easily compensated. Through this training, each matched multi-rank can receive command/address signals (CA) with optimal clock timing.

As above, embodiments are disclosed in the drawings and specifications. Although specific terms are used here, they are used only for the purpose of describing the present invention and are not used to limit the meaning or scope of the present invention described in the patent claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

Claims (20)

a first memory device constituting a first rank; and
A second memory device constituting a second rank sharing a command/address signal and a clock signal with the first memory device,
The first memory device and the second memory device receive command/address signals and clock signals in a matched type, and the first memory device has a variable delay for adjusting the delay of the received clock signal. A memory module containing a line. According to claim 1,
The clock signal corresponds to a strobe signal for latching the command/address signal. According to claim 1,
The first memory device is:
a command/address delay line that delays the received command/address signal (CA) to a preset size;
a variable delay line that adjusts the clock signal to a set delay size; and
A memory module comprising a flip-flop that latches the command/address signal (CA) output from the command/address delay line in response to the adjusted clock signal. According to claim 3,
The first memory device further includes delay control logic that adjusts the variable delay line. According to claim 4,
A memory module in which the delay control logic is controlled through a mode register set (MRS) command provided externally to the first memory device. According to claim 4,
The delay control logic includes a fuse offset that sets the variable delay logic to the set delay size according to external control of the first memory device. According to claim 3,
The set delay size is determined through command bus training (CBT) for the first memory device and the second memory device. In the training method of a matched multi-rank memory module sharing command/address signals and clock signals:
performing first command bus training to check alignment of the command/address signal and the clock signal for a first rank;
performing second command bus training to check alignment of the command/address signal and the clock signal for a second rank;
checking margins of the command/address signals of each of the first rank and the second rank using results of the first and second command bus training; and
A training method comprising adjusting a delay of the clock signal within the first rank or the second rank according to the margin of the command/address signal. According to claim 8,
A training method including a variable delay line inside the first rank or the second rank to adjust a delay of the clock signal. According to clause 9,
A training method in which the variable delay line is adjusted through a mode register set (MRS) command or a fuse program. According to claim 8,
A training method wherein the clock signal corresponds to a strobe signal for latching the command/address signal. a memory controller that transmits a signal through a first bus and a clock signal through a second bus; and
A memory module including a first rank memory and a second rank memory sharing the first bus and the second bus,
The first rank memory or the second rank memory includes a variable delay line for internally variably delaying the clock signal received through the second bus. According to claim 12,
A memory system in which the first rank memory or the second rank memory receives the signal and the clock signal in a matched type. According to claim 12,
A memory system in which the signal transmitted through the first bus corresponds to a command/address signal (CA). According to claim 12,
A memory system in which a signal transmitted through the first bus corresponds to a data signal (DQ). According to claim 12,
The first rank memory is:
a first delay line that delays the received signal by a fixed amplitude;
a second delay line that varies the delay size of the received clock signal; and
A memory system comprising a flip-flop that latches the signal output from the first delay line in response to a clock signal output from the second delay line. According to claim 16,
The first rank memory further includes delay control logic that sets the delay size of the second delay line in response to a control signal. According to claim 17,
A memory system wherein the delay control logic includes a mode register set or fuse option. According to claim 18,
The memory system wherein the memory controller performs command bus training (CBT) to detect skew of the first bus of the first rank memory and the second rank memory. According to claim 19,
A memory system wherein the memory controller sets a delay size of the variable delay line of one of the first rank memory and the second rank memory according to a result of the command bus training (CBT).

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