CN117577143A - Voltage control circuit module, memory storage device and voltage control method - Google Patents
Voltage control circuit module, memory storage device and voltage control method Download PDFInfo
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- CN117577143A CN117577143A CN202311665534.1A CN202311665534A CN117577143A CN 117577143 A CN117577143 A CN 117577143A CN 202311665534 A CN202311665534 A CN 202311665534A CN 117577143 A CN117577143 A CN 117577143A
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- 230000005055 memory storage Effects 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000010355 oscillation Effects 0.000 claims abstract description 160
- 238000002347 injection Methods 0.000 claims description 57
- 239000007924 injection Substances 0.000 claims description 57
- 238000001514 detection method Methods 0.000 claims description 19
- 230000004044 response Effects 0.000 claims description 11
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- 239000003990 capacitor Substances 0.000 description 16
- 101100310637 Arabidopsis thaliana SON1 gene Proteins 0.000 description 5
- 101100417245 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPN4 gene Proteins 0.000 description 5
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- 230000003111 delayed effect Effects 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention provides a voltage control circuit module, a memory storage device and a voltage control method. The method comprises the following steps: generating a first oscillation signal by a first oscillation circuit according to a feedback control signal; generating a second oscillation signal by a second oscillation circuit according to the feedback control signal; generating an output voltage according to the first oscillation signal and the second oscillation signal; generating a feedback control signal according to the output voltage; and locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal. Thus, the voltage control efficiency for the output voltage can be improved.
Description
Technical Field
The present invention relates to a voltage control technology, and more particularly, to a voltage control circuit module, a memory storage device and a voltage control method.
Background
Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices. In memory storage devices that include rewritable non-volatile memory modules, most electronic circuit elements (e.g., memory controllers) are quite sensitive to voltage variations. In particular, when the variation amplitude of the received voltage is excessively large, data reading errors, data writing errors, or device anomalies may be caused.
Disclosure of Invention
The invention provides a voltage control circuit module, a memory storage device and a voltage control method, which can improve the voltage control efficiency of output voltage.
Exemplary embodiments of the present invention provide a voltage control circuit module including a first oscillating circuit, a second oscillating circuit, a voltage output circuit, a feedback control circuit, and an injection locking circuit. The voltage output circuit is connected to the first oscillating circuit and the second oscillating circuit. The feedback control circuit is connected to the first oscillating circuit, the second oscillating circuit and the voltage output circuit. The injection locking circuit is connected to the first oscillating circuit and the second oscillating circuit. The first oscillation circuit is used for generating a first oscillation signal according to a feedback control signal. The second oscillating circuit is used for generating a second oscillating signal according to the feedback control signal. The voltage output circuit is used for generating output voltage according to the first oscillation signal and the second oscillation signal. The feedback control circuit is used for generating the feedback control signal according to the output voltage. The injection locking circuit is used for locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
In an example embodiment of the present invention, the injection locking circuit includes a first injection locking circuit connected to the first oscillating circuit and the second oscillating circuit. The first injection locking circuit is used for adjusting the edge position of the second pulse wave in the second oscillation signal according to the first pulse wave in the first oscillation signal.
In an example embodiment of the present invention, the operation of the first injection locking circuit to adjust the edge position of the second pulse in the second oscillation signal according to the first pulse in the first oscillation signal includes: adjusting a threshold voltage according to the first pulse wave in the first oscillation signal, wherein the threshold voltage is used for influencing the edge position of the second pulse wave in the second oscillation signal.
In an exemplary embodiment of the invention, the first injection locking circuit includes a pulse detector and a voltage adjusting circuit. The pulse wave detector is connected to the first oscillation circuit. The voltage adjusting circuit is connected to the pulse wave detector and the second oscillating circuit. The pulse wave detector is used for detecting the first pulse wave in the first oscillation signal and generating a detection signal. The voltage adjusting circuit is used for adjusting the critical voltage according to the detection signal.
In an exemplary embodiment of the invention, the voltage adjusting circuit includes a switching element and a charge-discharge circuit. The switching element is connected to the pulse wave detector. The charge-discharge circuit is connected to the switching element and the second oscillation circuit. The switch element is used for switching on state according to the first detection signal. The charge-discharge circuit is used for adjusting the critical voltage in response to the switching element being turned on or turned off.
In an exemplary embodiment of the present invention, the second oscillating circuit includes a comparator and an oscillator. The comparator is connected to the voltage output circuit. The oscillator is connected to the comparator and the feedback control circuit. The comparator is used for comparing the first voltage with the critical voltage. The oscillator is used for generating the second pulse wave in the second oscillation signal according to the feedback control signal and the output of the comparator.
In an exemplary embodiment of the invention, the second oscillating circuit is further configured to set an initial value of the threshold voltage according to the output voltage.
In an example embodiment of the present invention, the injection locking circuit further includes a second injection locking circuit connected to the first oscillating circuit and the second oscillating circuit. The second injection locking circuit is used for adjusting the edge position of the fourth pulse wave in the first oscillation signal according to the third pulse wave in the second oscillation signal.
In an example embodiment of the present invention, the voltage output circuit includes a low-pass filter circuit connected to the first oscillation circuit, the second oscillation circuit, and the feedback control circuit. The low-pass filter circuit is used for generating the output voltage according to the first oscillation signal and the second oscillation signal.
In an exemplary embodiment of the present invention, the first oscillating circuit and the second oscillating circuit may be simultaneously in a start-up state.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit, and a voltage control circuit module. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The voltage control circuit module is arranged in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit. The voltage control circuit module is used for: generating a first oscillation signal by a first oscillation circuit according to a feedback control signal; generating a second oscillation signal by a second oscillation circuit according to the feedback control signal; generating an output voltage according to the first oscillation signal and the second oscillation signal; generating the feedback control signal according to the output voltage; and locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
The exemplary embodiments of the present invention further provide a voltage control method for a memory storage device. The voltage control method comprises the following steps: generating a first oscillation signal by a first oscillation circuit according to a feedback control signal; generating a second oscillation signal by a second oscillation circuit according to the feedback control signal; generating an output voltage according to the first oscillation signal and the second oscillation signal; generating the feedback control signal according to the output voltage; and locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
In an example embodiment of the present invention, locking the at least one of the frequency difference and the phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal includes: and adjusting the edge position of the second pulse wave in the second oscillating signal according to the first pulse wave in the first oscillating signal.
In an exemplary embodiment of the present invention, the step of adjusting the edge position of the second pulse wave in the second oscillation signal according to the first pulse wave in the first oscillation signal includes: adjusting a threshold voltage according to the first pulse wave in the first oscillation signal, wherein the threshold voltage is used for influencing the edge position of the second pulse wave in the second oscillation signal.
In an exemplary embodiment of the present invention, the step of adjusting the threshold voltage according to the first pulse in the first oscillation signal includes: detecting the first pulse wave in the first oscillation signal and generating a detection signal; and adjusting the critical voltage according to the detection signal.
In an exemplary embodiment of the present invention, the step of adjusting the threshold voltage according to the detection signal includes: switching on a switching element according to the first detection signal; and adjusting the threshold voltage in response to the switching element being turned on or off.
In an exemplary embodiment of the present invention, the step of adjusting the edge position of the second pulse wave in the second oscillation signal according to the first pulse wave in the first oscillation signal includes: comparing, by a comparator, the first voltage with the threshold voltage; and generating the second pulse wave in the second oscillation signal according to the feedback control signal and the output of the comparator.
In an exemplary embodiment of the present invention, the voltage control method further includes: and setting an initial value of the critical voltage according to the output voltage.
In an example embodiment of the present invention, locking the at least one of the frequency difference and the phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal includes: and adjusting the edge position of the fourth pulse wave in the first oscillating signal according to the third pulse wave in the second oscillating signal.
In an exemplary embodiment of the present invention, the step of generating the output voltage according to the first oscillation signal and the second oscillation signal includes: the low-pass filter circuit generates the output voltage according to the first oscillation signal and the second oscillation signal.
Based on the above, under the system architecture that the oscillation circuits respectively generate the oscillation signals, the oscillation signals can be used to jointly generate the output voltage. Furthermore, an injection locking circuit additionally provided in the architecture may be used to lock frequency differences and/or phase differences between the oscillating signals according to the oscillating signals. Thus, the efficiency of voltage control of the output voltage under such a system architecture can be improved.
Drawings
FIG. 1 is a schematic diagram of a voltage control circuit module shown in accordance with an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram of a voltage control circuit module shown according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a first oscillating circuit shown according to an example embodiment of the invention;
FIG. 4 is a schematic diagram of a second oscillating circuit shown according to an example embodiment of the invention;
FIG. 5 is a schematic diagram of a first injection locking circuit shown in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of a second injection locking circuit shown in accordance with an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram showing the first threshold voltage unchanged with time according to an exemplary embodiment of the present invention;
FIG. 8 is a schematic diagram showing a first threshold voltage over time according to an example embodiment of the invention;
FIG. 9 is a schematic diagram showing the second threshold voltage unchanged with time according to an exemplary embodiment of the present invention;
FIG. 10 is a schematic diagram showing a second threshold voltage over time according to an exemplary embodiment of the present invention;
FIG. 11 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
fig. 12 is a flowchart of a spread spectrum clock generation method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The present invention is described below with reference to a number of exemplary embodiments, however, the present invention is not limited to the exemplary embodiments illustrated. Also, suitable combinations are allowed between the exemplary embodiments. The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect means of coupling. For example, if a first device is described herein as being connected to a second device, that is to be interpreted as the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through other devices or some connection means. Further, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
Fig. 1 is a schematic diagram of a voltage control circuit module according to an exemplary embodiment of the present invention. Referring to fig. 1, the voltage control circuit module 10 can be used to generate a voltage Vout (also referred to as an output voltage) according to a reference voltage. For example, the voltage control circuit module 10 may perform boosting or stepping down on the reference voltage to generate the voltage Vout. Thereafter, the voltage Vout may be supplied to one or more electronic circuits to drive the electronic circuits.
The voltage control circuit module 10 includes an oscillation circuit (also referred to as a first oscillation circuit) 11, an oscillation circuit (also referred to as a second oscillation circuit) 12, a voltage output circuit 13, a feedback control circuit 14, and an injection locking circuit 15. The oscillation circuit 11 is connected to a feedback control circuit 14. The oscillating circuit 11 is configured to receive a signal FB (also referred to as a feedback control signal) from the feedback control circuit 14 and generate a signal S1 (also referred to as a first oscillating signal) according to the signal FB. For example, one or more pulses may be periodically entrained in the signal S1.
The oscillating circuit 12 is connected to a feedback control circuit 14. The oscillating circuit 12 is configured to receive the signal FB from the feedback control circuit 14 and generate a signal (also referred to as a second oscillating signal) S2 according to the signal FB. For example, one or more pulses may also be periodically entrained in the signal S2.
The voltage output circuit 13 is connected to the oscillating circuits 11 and 12. The voltage output circuit 13 is configured to receive the signal S1 from the oscillating circuit 11 and the signal S2 from the oscillating circuit 12. Then, the voltage output circuit 13 can generate the voltage Vout according to the signals S1 and S2. For example, the voltage output circuit 13 may be configured to perform a current summing and low pass filtering (low-pass filtering) on the signals S1 and/or S2 to generate the voltage Vout.
The feedback control circuit 14 is connected to the oscillation circuit 11, the oscillation circuit 12, and the voltage output circuit 13. The feedback control circuit 14 is used for generating a signal FB according to the reference voltage and the voltage Vout. The signal FB may reflect the condition of the voltage Vout. For example, the voltage value of the signal FB may be positively correlated to the voltage value of the voltage Vout. In an exemplary embodiment, the signal FB may also reflect the voltage difference between the reference voltage and the voltage Vout. For example, the voltage value of the signal FB may be positively related to the voltage difference between the reference voltage and the voltage Vout.
The injection locking circuit 15 is connected to the oscillation circuit 11, the oscillation circuit 12, and the voltage output circuit 13. The injection locking circuit 15 is used for locking the frequency difference and/or the phase difference between the signals S1 and S2 according to the signals S1 and S2. For example, the injection locking circuit 15 may be used to lock the frequency difference between the signals S1 and S2 to a specific frequency difference (also referred to as a target frequency difference) and/or lock the phase difference between the signals S1 and S2 to a specific phase difference (also referred to as a target phase difference).
In an exemplary embodiment, the injection locking circuit 15 performs the mutual locking between at least one pulse in the signal S1 and at least one pulse in the signal S2 according to the signals S1 and S2. For example, the lock may be a lock of a relative position between at least one pulse in the signal S1 and at least one pulse in the signal S2.
In an exemplary embodiment, locking the relative position between at least one pulse in the signal S1 and at least one pulse in the signal S2 is equivalent to locking the frequency difference and/or the phase difference between the signals S1 and S2. In an exemplary embodiment, the quality of the generated voltage Vout can be improved (e.g., the voltage Vout having a specific voltage value can be stably output) when the frequency difference and/or the phase difference between the signals S1 and S2 are locked, compared to the frequency difference and/or the phase difference between the signals S1 and S2 which continuously varies (i.e., the frequency difference and/or the phase difference between the unlocked signals S1 and S2 is locked).
Fig. 2 is a schematic diagram of a voltage control circuit module according to an example embodiment of the invention. Referring to fig. 2, in an exemplary embodiment, the oscillating circuit 11 may include a comparator 211 and an oscillator 212. The comparator 211 is configured to receive the voltages Vfb and V1 and generate the signal CT1 according to the voltage difference between the voltages Vfb and V1. The signal CT1 may reflect the voltage difference between the voltages Vfb and V1. For example, the comparator 211 may be an error amplifier (error amplifier), and the type of the comparator 211 is not limited thereto. The oscillator 212 is connected to the comparator 211. The oscillator 212 can receive the signal CT1 and generate the signal S1 according to the signal CT1.
In an exemplary embodiment, the oscillating circuit 12 may include a comparator 221 and an oscillator 222. The comparator 221 may be configured to receive the voltages Vfb and V2 and generate the signal CT2 according to the voltage difference between the voltages Vfb and V2. Signal CT2 may reflect the voltage difference between voltages Vfb and V2. For example, the comparator 221 may also be an error amplifier, and the type of the comparator 221 is not limited thereto. The oscillator 222 is connected to the comparator 221. The oscillator 222 may receive the signal CT2 and generate the signal S2 according to the signal CT2.
In an example embodiment, signal CT1 may be used to turn on or off oscillator 212. In the case where the oscillator 212 is started, the oscillator 212 may output the signal S1. However, in the case where the oscillator 212 is not started, the oscillator 212 does not output the signal S1.
In an example embodiment, signal CT2 may be used to turn on or off oscillator 222. In the case where the oscillator 222 is started, the oscillator 222 may output the signal S2. However, in the case where the oscillator 222 is not started, the oscillator 222 does not output the signal S2.
In an exemplary embodiment, at a certain point in time (also referred to as a first point in time), oscillators 212 and 222 may be simultaneously in a start-up state. In an exemplary embodiment, at a certain point in time (also referred to as a second point in time), only one of the oscillators 212 and 222 is in a start-up state, and the other of the oscillators 212 and 222 is in an inactive state.
In an example embodiment, the voltage output circuit 13 may include a boost or buck converter. In an exemplary embodiment, the voltage output circuit 13 may comprise a buck converter or similar voltage output circuit having a Current Mode (CM), a current mode-constant on-time (CMCOT) or an ADVANCED constant on-time (ADVANCED-COT) architecture.
In an exemplary embodiment, the voltage output circuit 13 may include a logic circuit 231, a logic circuit 232, a low-pass filter circuit 233, transistors M1-M4, and inductors L1, L2. Logic 231 is coupled to oscillator 212 and receives signal S1. The logic circuit 231, the transistor M1, the transistor M2, and the inductor L1 can generate a current (also referred to as a first induced current) I1 on the inductor L1 according to the signal S1. The logic circuit 232 is connected to the oscillator 222 and receives the signal S2. The logic circuit 232, the transistor M3, the transistor M4 and the inductor L2 can generate a current (also referred to as a second induced current) I2 on the inductor L2 according to the signal S2. The low-pass filter circuit 233 may low-pass filter the currents I1 and I2 to generate the voltage Vout. For example, the low-pass filter circuit 233 may include a capacitor C1 and resistors R1 and R2. In addition, the voltage output circuit 13 can generate the voltage V1 at the sensing point P1 and the voltage V2 at the sensing point P2. The voltage V1 may be provided to the comparator 211. The voltage V2 may be provided to the comparator 221.
In an exemplary embodiment, the feedback control circuit 14 may include a comparator 241, resistors R3-R5, and a capacitor C2. The resistors R3 and R4 can form a voltage dividing circuit. The voltage dividing circuit can be used for dividing the voltage Vout to generate a voltage V3. For example, the voltage value of voltage V3 may be positively correlated to the voltage value of voltage Vout. The comparator 241 may receive the voltages (i.e., the reference voltages) Vref and V3 and generate a voltage Vfb according to a voltage difference between the voltages Vref and V3. The voltage Vfb may reflect a voltage difference between the voltages Vref and V3. In an example embodiment, the signal FB of fig. 1 may include the voltage Vfb. The voltage Vfb may be supplied to the comparators 211 and 221.
In an exemplary embodiment, the injection locking circuit 15 includes an injection locking circuit (also referred to as a first injection locking circuit) 251 and an injection locking circuit (also referred to as a second injection locking circuit) 252. The injection locking circuit 251 is connected to the output terminal of the oscillating circuit 11 and the input terminal (or control terminal) of the oscillating circuit 12. The injection locking circuit 252 is connected to the output of the oscillating circuit 12 and the input (or control) of the oscillating circuit 11.
In an exemplary embodiment, the injection locking circuit 251 can be configured to adjust the edge position of at least one pulse (also referred to as a second pulse) in the signal S2 according to at least one pulse (also referred to as a first pulse) in the signal S1. For example, the edge position of the second pulse wave may correspond to the rising edge and/or the falling edge of the second pulse wave. In an exemplary embodiment, the edge position of the second pulse wave may include a rising edge position and/or a falling edge position of the second pulse wave. In an exemplary embodiment, the injection locking circuit 252 may be configured to adjust the edge position of at least one pulse (also referred to as a fourth pulse) in the signal S1 according to at least one pulse (also referred to as a third pulse) in the signal S2. For example, the edge position of the third pulse wave may correspond to a rising edge and/or a falling edge of the third pulse wave. In an exemplary embodiment, the edge position of the third pulse wave may include a rising edge position and/or a falling edge position of the third pulse wave. In an exemplary embodiment, the frequency and/or phase difference between the signals S1 and S2 can be locked by adjusting the edge position (e.g., rising edge position and/or falling edge position) of at least some of the pulses in the signals S1 and S2.
Fig. 3 is a schematic diagram of a first oscillating circuit shown according to an example embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the oscillating circuit 212 includes a feedback circuit 31, a comparator 32 and an oscillator 33. The feedback circuit 31 is configured to generate a voltage (also referred to as a first threshold voltage) Vth (1) according to the voltage Vout. For example, the feedback circuit 31 may include a resistor R31, a resistor R32, a capacitor C31, and a capacitor C32.
The comparator 32 may receive the voltage Vth (1) and the voltage VX1 (also referred to as a first voltage). The comparator 32 can compare the voltages Vth (1) and VX1 and generate a signal VY1 according to the voltage difference between the voltages Vth (1) and VX1. The signal VY1 may reflect a voltage difference between the voltages Vth (1) and VX1. The oscillator 33 can receive the signals VY1 and CT1 and generate the signals SON1 and S1. The signal CT1 may be used to start the oscillator 33. In the case where the oscillator 33 is started, the oscillator 33 may generate the signal S1 according to the signal VY1.
In an exemplary embodiment, the oscillating circuit 212 further includes a current source IS31, a capacitor C33, and a switching element SW31. The signal SON1 can be used to turn on or off the switching element SW31. When the switching element SW31 IS not in the on state, the current source IS31 can charge the capacitor C33 to increase the voltage value of the voltage VX1. In addition, when the switching element SW31 is in the on state, the capacitor C33 may be discharged to reduce the voltage value of the voltage VX1.
In an exemplary embodiment, if the signal VY1 reflects that the voltage value of the voltage VX1 is lower than the voltage value of the voltage Vth (1) when the oscillator 33 is started, the oscillator 33 may generate a pulse in the signal S1 according to the signal VY 1. In particular, the signal SON1 may be continuously pulled high during the generation of the pulse to reflect the duration of the pulse. For example, the duration of a pulse may be directly related to the width of the pulse.
In an exemplary embodiment, in response to the signal SON1 being pulled high, the switching element SW31 may be turned off to increase the voltage value of the voltage VX 1. Later, if the signal VY1 reflects that the voltage value of the voltage VX1 has been increased to be the same as the voltage Vth (1), the oscillator 33 may end the pulse according to the voltage VY 1. For example, the point in time at which the pulse is ended (i.e., the edge position of the pulse) may correspond to the falling edge (falling edge) of the pulse in signal S1. In response to the end of the pulse, the signal SON1 may be pulled low and the switching element SW31 may be turned on. Thus, a single pulse of a specific width in the signal S1 can be generated. By repeatedly performing the above operations, a plurality of pulses discontinuous in the signal S1 can be generated one by one.
Fig. 4 is a schematic diagram of a second oscillating circuit shown according to an example embodiment of the invention. Referring to fig. 4, in an exemplary embodiment, the oscillating circuit 222 includes a feedback circuit 41, a comparator 42 and an oscillator 43. The feedback circuit 41 can be used to generate a voltage (also referred to as a second threshold voltage) Vth (2) according to the voltage Vout. For example, the feedback circuit 41 may include a resistor R41, a resistor R42, a capacitor C41, and a capacitor C42.
The comparator 42 may receive the voltage Vth (2) and the voltage VX2 (also referred to as the second voltage). The comparator 42 can compare the voltages Vth (2) and VX2 and generate a signal VY2 according to the voltage difference between the voltages Vth (2) and VX2. The signal VY2 may reflect the voltage difference between voltages Vth (2) and VX2. The oscillator 43 can receive the signals VY2 and CT2 and generate the signals SON2 and S2. Signal CT2 may be used to start oscillator 43. In the case where the oscillator 43 is started, the oscillator 43 may generate the signal S2 according to the signal VY2.
In an exemplary embodiment, the oscillating circuit 222 further includes a current source IS41, a capacitor C43, and a switching element SW41. The signal SON2 can be used to turn on or off the switching element SW41. When the switching element SW41 IS in the non-conductive state, the current source IS41 can charge the capacitor C43 to increase the voltage value of the voltage VX2. In addition, when the switching element SW41 is in the on state, the capacitor C43 may be discharged to reduce the voltage value of the voltage VX2.
In an exemplary embodiment, if the signal VY2 reflects that the voltage value of the voltage VX2 is lower than the voltage value of the voltage Vth (2) when the oscillator 43 is started, the oscillator 43 may generate a pulse in the signal S2 according to the signal VY 2. In particular, the signal SON2 may be continuously pulled high during the generation of the pulse to reflect the duration of the pulse.
In an exemplary embodiment, in response to the signal SON2 being pulled high, the switching element SW41 may be turned off to increase the voltage value of the voltage VX 2. Later, if the signal VY2 reflects that the voltage value of the voltage VX2 has been increased to be the same as the voltage Vth (2), the oscillator 43 may end the pulse according to the voltage VY 2. For example, the point in time when the pulse is ended (i.e., the edge position of the pulse) may correspond to the falling edge of the pulse in signal S2. In response to the end of the pulse, the signal SON2 may be pulled low and the switching element SW41 may be turned on. Thus, a single pulse of a specific width in the signal S2 can be generated. By repeatedly performing the above operations, a plurality of pulses discontinuous in the signal S2 can be generated one by one.
In an exemplary embodiment, the injection locking circuit 251 in fig. 2 can further adjust the voltage Vth (2) (i.e., the second threshold voltage) in fig. 4 according to the pulse (i.e., the first pulse) in the signal S1, and the voltage Vth (2) can be used to influence the edge position of at least one pulse (i.e., the second pulse) generated in the signal S2. For example, if the voltage value of the voltage Vth (2) is increased, the edge position of at least one pulse generated in the signal S2 may be delayed. Alternatively, if the voltage Vth (2) is reduced, the edge position of at least one pulse generated in the signal S2 may be advanced. Thereby, the frequency difference and/or the phase difference between the signals S1 and S2 is facilitated to be locked.
In an exemplary embodiment, the injection locking circuit 252 in fig. 2 can adjust the voltage Vth (1) (i.e., the first threshold voltage) in fig. 3 according to the pulse (i.e., the third pulse) in the signal S2, and the voltage Vth (1) can be used to influence the edge position of at least one pulse (i.e., the fourth pulse) generated in the signal S1. For example, if the voltage value of the voltage Vth (1) is increased, the edge position of at least one pulse wave generated in the signal S1 may be delayed. Alternatively, if the voltage Vth (1) is lowered, the edge position of at least one pulse generated in the signal S1 may be advanced. Thereby, the frequency difference and/or the phase difference between the signals S1 and S2 is also facilitated to be locked.
Fig. 5 is a schematic diagram of a first injection locking circuit according to an example embodiment of the invention. Referring to fig. 5, in an exemplary embodiment, the injection locking circuit 251 includes a pulse detector 51 and a voltage adjusting circuit 52. The pulse detector 51 can be used for detecting the pulse (i.e. the first pulse) in the signal S1 and generating a signal (also referred to as the first detection signal) D1. For example, the pulse detector 51 can be used to detect the falling edge (i.e. the edge position) of the first pulse in the signal S1. In response to this falling edge, the pulse detector 51 may generate a signal D1. For example, the signal D1 may reflect the edge position of the first pulse wave. The voltage adjusting circuit 52 is connected to the pulse wave detector 51. The voltage adjusting circuit 52 can be used for receiving the signal D1 and adjusting the voltage Vth (2) according to the signal D1.
In an exemplary embodiment, the voltage adjusting circuit 52 includes a switching element SW51 and a charging/discharging circuit 521. The switching element SW51 is connected to the pulse wave detector 51. The charge-discharge circuit 521 is connected to the switching element SW51. In an exemplary embodiment, the signal D1 may be used to briefly turn on the switching element SW51. When the switching element SW51 is in the on state, the voltage adjusting circuit 52 may charge the capacitor C51 to increase the voltage value of the voltage Vth (2). Then, the switching element SW51 may be turned off. When the voltage Vth (2) has been increased and the switching element SW51 IS not in the on state, the voltage adjusting circuit 52 may discharge the capacitor C51 through the current source IS51 to decrease the voltage Vth (2).
In other words, in an exemplary embodiment, the injection locking circuit 251 can adjust (e.g. intermittently increase and decrease) the voltage value of the voltage Vth (2) according to the edge position (e.g. the falling edge) of at least part of the pulses (i.e. the first pulse) in the signal S1. Thus, the injection locking circuit 251 can control or adjust the edge position of the pulse wave (i.e., the second pulse wave) generated in the signal S2.
Fig. 6 is a schematic diagram of a second injection locking circuit according to an example embodiment of the invention. Referring to fig. 6, in an exemplary embodiment, the injection locking circuit 252 includes a pulse detector 61 and a voltage adjusting circuit 62. The pulse detector 51 can be used for detecting the pulse (i.e. the third pulse) in the signal S2 and generating a signal (also referred to as the second detection signal) D2. For example, the pulse detector 61 can be used to detect the falling edge (i.e. the edge position) of the third pulse in the signal S2. In response to this falling edge, the pulse detector 61 may generate the signal D2. For example, the signal D2 may reflect the edge position of the third pulse. The voltage adjusting circuit 62 is connected to the pulse wave detector 61. The voltage adjusting circuit 62 can be used for receiving the signal D2 and adjusting the voltage Vth (1) according to the signal D2.
In an exemplary embodiment, the voltage adjusting circuit 62 includes a switching element SW61 and a charging/discharging circuit 621. The switching element SW61 is connected to the pulse wave detector 61. The charge and discharge circuit 621 is connected to the switching element SW61. In an exemplary embodiment, the signal D2 may be used to briefly turn on the switching element SW61. When the switching element SW61 is in the on state, the voltage adjusting circuit 62 may charge the capacitor C61 to increase the voltage value of the voltage Vth (1). Then, the switching element SW61 may be turned off. When the voltage Vth (1) has been increased and the switching element SW61 IS not in the on state, the voltage adjusting circuit 62 may discharge the capacitor C61 through the current source IS61 to decrease the voltage Vth (1).
In other words, in an exemplary embodiment, the injection locking circuit 252 may adjust (e.g. intermittently increase and decrease) the voltage value of the voltage Vth (1) according to the edge position (e.g. the falling edge) of at least part of the pulses (i.e. the third pulse) in the signal S2. Thus, the injection locking circuit 252 can control or adjust the edge position of the pulse wave (i.e., the fourth pulse wave) generated in the signal S1.
Fig. 7 is a schematic diagram showing that the first threshold voltage is unchanged with time according to an exemplary embodiment of the present invention. Referring to fig. 3 and 7, in an exemplary embodiment, the voltage Vth (1) is ideally set to an initial value of the voltage Vth (1) according to the voltage Vout without dynamically adjusting the voltage Vth (1). During the period when the oscillator 33 is started, if the voltage VX1 is lower than the voltage Vth (1), a single pulse in the signal S1 can be generated and maintained. Later, when the voltage value of the voltage VX1 is increased to be the same as the voltage value of the voltage Vth (1), the pulse wave may be ended. In addition, during the period when the oscillator 33 is not activated, no pulse may be present in the signal S1.
Fig. 8 is a schematic diagram showing a change of a first threshold voltage with time according to an exemplary embodiment of the present invention. Referring to fig. 6 and 8, under the control of the injection locking circuit 252, the voltage Vth (1) can be dynamically adjusted, and the voltage value of the voltage Vth (1) can be changed with time. In particular, by adjusting the slope of the voltage value of the voltage Vth (1) with respect to time, the injection locking circuit 252 can precisely control (e.g., advance or retard) the edge position of at least a portion of the pulses in the signal S1 to lock the frequency difference and/or the phase difference between the signals S1 and S2. Further, the voltage value of the voltage Vth (1) may be a linear or nonlinear relationship with respect to time, and the present invention is not limited thereto.
Fig. 9 is a schematic diagram showing that the second threshold voltage is unchanged with time according to an exemplary embodiment of the present invention. Referring to fig. 4 and 9, in an exemplary embodiment, the voltage Vth (2) is ideally set to an initial value of the voltage Vth (2) according to the voltage Vout without dynamically adjusting the voltage Vth (2). During the period when the oscillator 43 is started, if the voltage VX2 is lower than the voltage Vth (2), a single pulse in the signal S2 can be generated and maintained. Later, when the voltage value of the voltage VX2 is increased to be the same as the voltage value of the voltage Vth (2), the pulse wave may be ended. In addition, during the period when the oscillator 43 is not activated, no pulse may be present in the signal S2.
Fig. 10 is a schematic diagram showing a change of the second threshold voltage with time according to an exemplary embodiment of the present invention. Referring to fig. 5 and 10, under the control of the injection locking circuit 251, the voltage Vth (2) can be dynamically adjusted, and the voltage value of the voltage Vth (2) can be changed with time. In particular, by adjusting the slope of the voltage value of the voltage Vth (2) with respect to time, the injection locking circuit 251 can precisely control (e.g., advance or retard) the edge position of at least a portion of the pulses in the signal S2 to lock the frequency difference and/or the phase difference between the signals S1 and S2. The voltage value of the voltage Vth (2) may be a linear or nonlinear relationship with respect to time.
It should be noted that all the circuit structures shown in fig. 1 to 6 are only examples, and are not meant to limit the present invention. In all the circuit structures shown in fig. 1 to 6, the connection relationship between the electronic circuits and/or the electronic components may be adjusted according to the actual requirements, which is not limited by the present invention. In an exemplary embodiment, in all the circuit structures shown in fig. 1 to 6, each electronic circuit and/or electronic component may be replaced by an electronic circuit and/or electronic component having the same or similar functions, which is not limited by the present invention. In addition, other types of electronic circuits and/or electronic components may be included in all of the circuit structures shown in fig. 1-6 to provide additional functionality, and the invention is not limited.
In an exemplary embodiment, the voltage control circuit module 10 of fig. 1 may be disposed in a memory storage device or a memory control circuit unit to operate together with the memory storage device or the memory control circuit unit. However, in an exemplary embodiment, the voltage control circuit module 10 of fig. 1 may be disposed in other types of electronic devices, and the invention is not limited thereto.
Fig. 11 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to FIG. 11, a memory storage device 1100 may be used with a host system 1110. For example, host system 1110 can write data to memory storage device 1100 or read data from memory storage device 1100. Host system 1110 can be any system that can cooperate with memory storage device 1100 to store data, such as a smart phone, tablet computer, desktop computer, notebook computer, digital camera, video camera, communication device, audio player, or video player, among others.
The memory storage device 1100 includes a connection interface unit 1101, a memory control circuit unit 1102, and a rewritable nonvolatile memory module 1103. The connection interface unit 1101 is used to connect the memory storage device 1100 to the host system 1110. For example, the connection interface unit 1101 may be compatible with a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, a peripheral component interconnect Express (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, or other suitable standards. The connection interface unit 1101 may be packaged in one chip with the memory control circuit unit 1102, or the connection interface unit 1101 may be disposed outside the chip including the memory control circuit unit 1102.
The memory control circuit 1102 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware. The memory control circuit unit 1102 can perform operations such as writing, reading and erasing of data in the rewritable nonvolatile memory module 1103 according to the instruction of the host system 1110.
The rewritable nonvolatile memory module 1103 can be connected to the memory control circuit unit 1102 and used to store data written by the host system 1110. For example, the rewritable nonvolatile memory module 1103 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a three-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a four-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same or similar characteristics.
In an example embodiment, the rewritable non-volatile memory module 1103 of fig. 11 may comprise a flash memory module. In an example embodiment, the memory control circuit unit 1102 of fig. 11 may include a flash memory controller for controlling the flash memory module.
In an example embodiment, the voltage control circuit module 10 of fig. 1 may be disposed in the connection interface unit 1101, the memory control circuit unit 1102, and/or the rewritable nonvolatile memory module 1103 of fig. 11 to power the connection interface unit 1101, the memory control circuit unit 1102, and/or the rewritable nonvolatile memory module 1103.
In an example embodiment, the voltage control circuit module 10 of fig. 1 may be connected to the connection interface unit 1101, the memory control circuit unit 1102, and/or the rewritable nonvolatile memory module 1103 of fig. 11 to power the connection interface unit 1101, the memory control circuit unit 1102, and/or the rewritable nonvolatile memory module 1103.
Fig. 12 is a flowchart of a spread spectrum clock generation method according to an exemplary embodiment of the present invention. Referring to fig. 12, in step S1201, a first oscillation signal is generated by a first oscillation circuit according to a feedback control signal. In step S1202, a second oscillation signal is generated by a second oscillation circuit according to a feedback control signal. In step S1203, an output voltage is generated according to the first oscillation signal and the second oscillation signal. In step S1204, a feedback control signal is generated according to the output voltage. In step S1205, at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal is locked according to the first oscillation signal and the second oscillation signal.
However, the steps in fig. 12 are described in detail above, and will not be described again here. It should be noted that each step in fig. 12 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 12 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.
In summary, the voltage control circuit module, the memory storage device and the voltage control method according to the exemplary embodiments of the invention can lock the frequency difference and/or the phase difference between the oscillation signals by dynamically adjusting the threshold voltage of at least one oscillation circuit. Thus, the efficiency of voltage control of the output voltage in the system architecture in which the oscillation signals are generated by the plurality of oscillation circuits can be improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (30)
1. A voltage control circuit module, comprising:
a first oscillating circuit;
a second oscillating circuit;
a voltage output circuit connected to the first oscillating circuit and the second oscillating circuit;
a feedback control circuit connected to the first oscillating circuit, the second oscillating circuit, and the voltage output circuit; and
an injection locking circuit connected to the first oscillating circuit and the second oscillating circuit,
wherein the first oscillating circuit is used for generating a first oscillating signal according to a feedback control signal,
the second oscillating circuit is used for generating a second oscillating signal according to the feedback control signal,
the voltage output circuit is used for generating an output voltage according to the first oscillation signal and the second oscillation signal,
the feedback control circuit is used for generating the feedback control signal according to the output voltage, and
the injection locking circuit is used for locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
2. The voltage control circuit module of claim 1, wherein the injection locking circuit comprises:
A first injection locking circuit connected to the first oscillating circuit and the second oscillating circuit,
the first injection locking circuit is used for adjusting the edge position of the second pulse wave in the second oscillation signal according to the first pulse wave in the first oscillation signal.
3. The voltage control circuit module of claim 2, wherein the operation of the first injection locking circuit to adjust the edge position of the second pulse in the second oscillating signal according to the first pulse in the first oscillating signal comprises:
adjusting a threshold voltage according to the first pulse in the first oscillation signal,
wherein the threshold voltage is used to influence the edge position of the second pulse wave in the second oscillation signal.
4. The voltage control circuit module of claim 3 wherein the first injection locking circuit comprises:
a pulse wave detector connected to the first oscillation circuit; and
a voltage adjusting circuit connected to the pulse wave detector and the second oscillating circuit,
wherein the pulse wave detector is used for detecting the first pulse wave in the first oscillation signal and generating a detection signal, and
The voltage adjusting circuit is used for adjusting the critical voltage according to the detection signal.
5. The voltage control circuit module of claim 4, wherein the voltage adjustment circuit comprises:
a switching element connected to the pulse wave detector; and
a charge-discharge circuit connected to the switching element and the second oscillation circuit,
wherein the switching element is used for switching on state according to the detection signal, and
the charge-discharge circuit is used for adjusting the critical voltage in response to the switching element being turned on or turned off.
6. The voltage control circuit module of claim 3, wherein the second oscillating circuit comprises:
a comparator connected to the voltage output circuit; and
an oscillator connected to the comparator and the feedback control circuit,
wherein the comparator is used for comparing the first voltage with the critical voltage and
the oscillator is used for generating the second pulse wave in the second oscillation signal according to the feedback control signal and the output of the comparator.
7. The voltage control circuit module of claim 3, wherein the second oscillating circuit is further configured to set an initial value of the threshold voltage according to the output voltage.
8. The voltage control circuit module of claim 2, wherein the injection locking circuit further comprises:
a second injection locking circuit connected to the first oscillating circuit and the second oscillating circuit,
the second injection locking circuit is used for adjusting the edge position of the fourth pulse wave in the first oscillation signal according to the third pulse wave in the second oscillation signal.
9. The voltage control circuit module of claim 1, wherein the voltage output circuit comprises:
a low-pass filter circuit connected to the first oscillation circuit, the second oscillation circuit and the feedback control circuit,
the low-pass filter circuit is used for generating the output voltage according to the first oscillation signal and the second oscillation signal.
10. The voltage control circuit module of claim 1, wherein the first oscillating circuit and the second oscillating circuit are simultaneously activatable.
11. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable nonvolatile memory module;
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module; and
The voltage control circuit module is arranged in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit,
wherein the voltage control circuit module is used for:
generating a first oscillation signal by a first oscillation circuit according to a feedback control signal;
generating a second oscillation signal by a second oscillation circuit according to the feedback control signal;
generating an output voltage according to the first oscillation signal and the second oscillation signal;
generating the feedback control signal according to the output voltage; and
locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
12. The memory storage device of claim 11, wherein the voltage control circuit module comprises an injection locking circuit,
the injection locking circuit is used for adjusting the edge position of the second pulse wave in the second oscillation signal according to the first pulse wave in the first oscillation signal.
13. The memory storage device of claim 12, wherein the operation of the injection locking circuit to adjust the edge position of the second pulse in the second oscillating signal according to the first pulse in the first oscillating signal comprises:
Adjusting a threshold voltage according to the first pulse in the first oscillation signal,
wherein the threshold voltage is used to influence the edge position of the second pulse wave in the second oscillation signal.
14. The memory storage device of claim 13, wherein the injection locking circuit comprises:
a pulse wave detector; and
a voltage adjusting circuit connected to the pulse wave detector,
wherein the pulse wave detector is used for detecting the first pulse wave in the first oscillation signal and generating a detection signal, and
the voltage adjusting circuit is used for adjusting the critical voltage according to the detection signal.
15. The memory storage device of claim 14, wherein the voltage adjustment circuit comprises:
a switching element connected to the pulse wave detector; and
a charge-discharge circuit connected to the switching element,
wherein the switching element is used for switching on state according to the detection signal, and
the charge-discharge circuit is used for adjusting the critical voltage in response to the switching element being turned on or turned off.
16. The memory storage device of claim 13, wherein the voltage control circuit module comprises:
A comparator; and
an oscillator connected to the comparator,
wherein the comparator is used for comparing the first voltage with the critical voltage and
the oscillator is used for generating the second pulse wave in the second oscillation signal according to the feedback control signal and the output of the comparator.
17. The memory storage device of claim 13, wherein the voltage control circuit module is further configured to set an initial value of the threshold voltage according to the output voltage.
18. The memory storage device of claim 12, wherein the injection locking circuit is further configured to adjust an edge position of a fourth pulse in the first oscillating signal according to a third pulse in the second oscillating signal.
19. The memory storage device of claim 11, wherein the voltage control circuit module comprises a low pass filter circuit,
the low-pass filter circuit is used for generating the output voltage according to the first oscillation signal and the second oscillation signal.
20. The memory storage device of claim 11, wherein the first oscillating circuit and the second oscillating circuit are simultaneously activatable.
21. A voltage control method for a memory storage device, the voltage control method comprising:
generating a first oscillation signal by a first oscillation circuit according to a feedback control signal;
generating a second oscillation signal by a second oscillation circuit according to the feedback control signal;
generating an output voltage according to the first oscillation signal and the second oscillation signal;
generating the feedback control signal according to the output voltage; and
locking at least one of a frequency difference and a phase difference between the first oscillation signal and the second oscillation signal according to the first oscillation signal and the second oscillation signal.
22. The voltage control method of claim 21, wherein locking the at least one of the frequency difference and the phase difference between the first and second oscillation signals according to the first and second oscillation signals comprises:
and adjusting the edge position of the second pulse wave in the second oscillating signal according to the first pulse wave in the first oscillating signal.
23. The voltage control method of claim 22, wherein adjusting the edge position of the second pulse in the second oscillating signal according to the first pulse in the first oscillating signal comprises:
Adjusting a threshold voltage according to the first pulse in the first oscillation signal,
wherein the threshold voltage is used to influence the edge position of the second pulse wave in the second oscillation signal.
24. The voltage control method of claim 23, wherein adjusting the threshold voltage according to the first pulse in the first oscillation signal comprises:
detecting the first pulse wave in the first oscillation signal and generating a detection signal; and
and adjusting the critical voltage according to the detection signal.
25. The voltage control method of claim 24, wherein adjusting the threshold voltage according to the detection signal comprises:
switching on the switching element according to the detection signal; and
the threshold voltage is adjusted in response to the switching element being turned on or off.
26. The voltage control method of claim 23, wherein adjusting the edge position of the second pulse in the second oscillating signal according to the first pulse in the first oscillating signal comprises:
comparing, by a comparator, the first voltage with the threshold voltage; and
and generating the second pulse wave in the second oscillation signal according to the feedback control signal and the output of the comparator.
27. The voltage control method of claim 23, further comprising:
and setting an initial value of the critical voltage according to the output voltage.
28. The voltage control method of claim 22, wherein locking the at least one of the frequency difference and the phase difference between the first and second oscillation signals according to the first and second oscillation signals comprises:
and adjusting the edge position of the fourth pulse wave in the first oscillating signal according to the third pulse wave in the second oscillating signal.
29. The voltage control method of claim 21, wherein generating the output voltage from the first and second oscillating signals comprises:
the low-pass filter circuit generates the output voltage according to the first oscillation signal and the second oscillation signal.
30. The voltage control method of claim 21, wherein the first oscillating circuit and the second oscillating circuit are simultaneously in an on state.
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| CN202311665534.1A CN117577143A (en) | 2023-12-06 | 2023-12-06 | Voltage control circuit module, memory storage device and voltage control method |
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| CN202311665534.1A CN117577143A (en) | 2023-12-06 | 2023-12-06 | Voltage control circuit module, memory storage device and voltage control method |
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