CN106712747A - Frequency dividing clock signal acquisition method and apparatus - Google Patents
Frequency dividing clock signal acquisition method and apparatus Download PDFInfo
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- CN106712747A CN106712747A CN201611132496.3A CN201611132496A CN106712747A CN 106712747 A CN106712747 A CN 106712747A CN 201611132496 A CN201611132496 A CN 201611132496A CN 106712747 A CN106712747 A CN 106712747A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
Abstract
The present invention provides a frequency dividing clock signal acquisition method and apparatus. An initial frequency dividing clock signal that is easy to obtain is obtained firstly, a high level and a low level in the initial frequency dividing clock signal are converted into stored energy of a first energy storage element and a second energy storage element, so as to be compared conveniently, and durations of a high level and a low level of a current initial frequency dividing clock signal are adjusted according to a comparison result feedback, so that the duty ratio of the initial frequency dividing clock signal is adjusted. Before the stored energy of the first energy storage element and the second energy storage element is equal, the duty ratio is adjusted constantly according to the comparison result, so as to reach a preset duty ratio. Compared with the solution using a phase-locked loop, the frequency dividing clock signal acquisition apparatus has a simple implementation circuit, and can acquire odd number or decimal number clock frequency dividing signals of various duty ratios according to demands, so as to meet control demands of an IC chip. A smaller area is used for deploying the frequency dividing clock signal acquisition apparatus, so that less area is used for deploying the IC chip.
Description
Technical field
The present invention relates to electronic technology field, more particularly to sub-frequency clock signal acquisition methods and device.
Background technology
With the development of electronic technology field, requirement more and more higher of the user to electronic product portability.In order to meet use
The requirement at family, realizes the lightweight of electronic product volume and weight, therefore, the integrated level of electronic product internal components is also increasingly
It is high.For for an IC (integrated circuit, integrated circuit) chip, high integration does not require nothing more than internal circuit cloth
Office is reasonable enough so that the space of itself is enough to accommodate to be needed to be laid out all devices.Simultaneously as the control process of logical device
Almost it is all based on controlling what clock was carried out, therefore, under high integration, the requirement to controlling clock is also higher：Except requiring
Outside smaller clock skew, also require to provide the different sub-frequency clock signal of various dutycycles to service different controls
Journey.For example, the frequency-dividing clock of 50% dutycycle is exactly wherein to apply one kind widely, its work in interface data treatment
With almost can not be substituted.
Sub-frequency clock signal is simply introduced below：If desired a fractional frequency signal for Fractional-N frequency is obtained, then first
The external clock cycle being input into should be counted, after count value reaches N, produce a clock in output end, thus
Ensure that N/mono- that frequency divider output clock frequency is input clock frequency.For the output clock of frequency divider, dutycycle is
One very important performance parameter, the dutycycle of generally basic frequency divider output clock is by judging the count value of counter
To control, in N number of original clock cycle, if output clock level in m-th original clock occurs saltus step, when exporting
The dutycycle of clock is M/N.
For obtaining even frequency division clock signal, when M is equal to N/2, dutycycle is 50%, and this is very simple in realization
It is single.But for frequency division by odd integers than even fractional frequency division than clock signal, to realize 50% dutycycle just it is extremely difficult, it is necessary to
Extremely complex analog circuit is aided in, for example, can apply to phaselocked loop.Phaselocked loop generally exists in the form of individual devices,
If realizing obtaining target sub-frequency clock signal by phaselocked loop, not only cause that IC chip operating circuit is complicated, Er Qiesuo
The part deployment region that phase ring can also take, hinders the lifting of IC chip integrated level.
The content of the invention
Sub-frequency clock signal acquisition methods and device that the present invention is provided, mainly solving the technical problems that：There is provided a kind of
The acquisition methods and device of default dutycycle sub-frequency clock signal are obtained, to solve obtaining odd number or decimal point in the prior art
, it is necessary to the problem of the device such as phaselocked loop auxiliary during frequency clock signal.
In order to solve the above technical problems, the present invention provides a kind of sub-frequency clock signal acquisition methods, including：
Initial sub-frequency clock signal is obtained relative to the frequency dividing numerical value of external timing signal according to target sub-frequency clock signal；
Default dutycycle based on the target sub-frequency clock signal is in current initial sub-frequency clock signal a cycle
High level duration is carried out to the energy-storage travelling wave tube of specification identical first with the second energy-storage travelling wave tube respectively with low level duration
Charging energy-storing, and the electric energy that first energy-storage travelling wave tube is stored with second energy-storage travelling wave tube is compared；
When comparative result characterizes the current dutycycle of the initial sub-frequency clock signal is not equal to default dutycycle, progressively
High level and low level duration in the current initial sub-frequency clock signal of increase and decrease adjustment, to the initial sub-frequency clock signal
As target sub-frequency clock signal.
Further, first energy-storage travelling wave tube and second energy-storage travelling wave tube are electric capacity.
Further, the default dutycycle based on the target sub-frequency clock signal is in current initial sub-frequency clock signal one
High level duration and low level duration are respectively to the energy-storage travelling wave tube of specification identical first and the second energy storage in the individual cycle
Element carries out charging energy-storing to be included：
Default dutycycle according to the target sub-frequency clock signal determine respectively to for first energy-storage travelling wave tube with
The ratio between the charging rate of second energy-storage travelling wave tube, first energy-storage travelling wave tube and charging rate of second energy-storage travelling wave tube are
The ratio between low level and high level duration under the default dutycycle；
Control first energy-storage travelling wave tube and second energy-storage travelling wave tube according to for respective charging rate respectively in height
Level duration, low level duration carry out charging energy-storing.
Further, the present invention also provides a kind of sub-frequency clock signal acquisition device, including：
Initial frequency dividing circuit, for being obtained relative to the frequency dividing numerical value of external timing signal according to target sub-frequency clock signal
Initial sub-frequency clock signal；
Frequency dividing comparison circuit, including control unit, comparing unit and the energy-storage travelling wave tube of specification identical first and the second storage
Can element；Described control unit is based on the default dutycycle of the target sub-frequency clock signal in current initial sub-frequency clock signal
High level duration stores up to the energy-storage travelling wave tube of specification identical first and second respectively with low level duration in a cycle
Energy element carries out charging energy-storing；The comparing unit is used for what first energy-storage travelling wave tube and second energy-storage travelling wave tube were stored
Electric energy is compared；
Frequency dividing adjustment circuit, for being not equal to when comparative result characterizes the current dutycycle of the initial sub-frequency clock signal
During default dutycycle, progressively increase and decrease adjusts high level and low level duration in current initial sub-frequency clock signal, to institute
Initial sub-frequency clock signal is stated as target sub-frequency clock signal.
Further, first energy-storage travelling wave tube and second energy-storage travelling wave tube are electric capacity.
Further, described control unit determines to pin respectively according to the default dutycycle of the target sub-frequency clock signal
To the charging rate of first energy-storage travelling wave tube and second energy-storage travelling wave tube, and first energy-storage travelling wave tube is controlled with described
Two energy-storage travelling wave tubes carry out charging storage in high level duration, low level duration respectively according to for respective charging rate
Can, the ratio between first energy-storage travelling wave tube and charging rate of second energy-storage travelling wave tube under the default dutycycle low level with
The ratio between high level duration.
Further, the target sub-frequency clock signal is the sub-frequency clock signal of 50% dutycycle, first energy storage
Charging rate between element and second energy-storage travelling wave tube is equal.
Further, also including enabling control circuit, the enable control circuit is used for the initial frequency dividing circuit, institute
The work for stating frequency dividing comparison circuit and the frequency dividing adjustment circuit is enabled.
Further, the frequency dividing adjustment circuit includes adjustment control unit and delay chain, the adjustment control unit root
The length of the delay chain for determining to participate in work according to the comparative result of the comparing unit.
Further, it is described adjustment control unit also for the comparing unit determine first energy-storage travelling wave tube with
Recorded in the case that second energy-storage travelling wave tube storage electric energy is equal and keep currently participating in the delay chain length of work.
The beneficial effects of the invention are as follows：
Sub-frequency clock signal acquisition methods and device that the present invention is provided, first get the initial frequency-dividing clock being easily obtained
Signal, and high level in current initial clock fractional frequency signal and the respective duration of low level are changed into the first energy-storage travelling wave tube
Size with the second energy-storage travelling wave tube stores electric energy, is then compared, and according to the current initial clock of comparative result feedback adjustment
The high level of fractional frequency signal and low level duration, so as to reach the purpose of adjustment initial clock fractional frequency signal dutycycle.
The first energy-storage travelling wave tube is compared with the energy storage of the second energy-storage travelling wave tube again after adjustment, until the first energy-storage travelling wave tube and second
Energy-storage travelling wave tube energy storage is equal, namely high level meets default duty with the low level duration in initial clock fractional frequency signal
Than.Relative to the frequency-dividing clock that the scheme of the clock division signal that default dutycycle is obtained using phaselocked loop, the present invention are provided
Signal acquisition device realizes that circuit is more simple, and can according to demand get the target odd number or decimal of various dutycycles
Clock division signal, meets the demand for control of IC chip.And the region required for the deployment of sub-frequency clock signal acquisition device
It is smaller, the occupancy to IC chip deployment region can be reduced, be conducive to being lifted the integrated level of IC chip.
Brief description of the drawings
Fig. 1 is a kind of flow chart of the sub-frequency clock signal acquisition methods that the embodiment of the present invention one is provided；
Fig. 2 is a kind of schematic diagram of the delay chain of offer in the embodiment of the present invention one；
Fig. 3 is a kind of structural representation of the sub-frequency clock signal acquisition device that the embodiment of the present invention two is provided；
Fig. 4 is a kind of structural representation of frequency dividing comparison circuit in Fig. 3；
Fig. 5 a are a kind of circuit diagram for enabling control circuit；
Fig. 5 b are the timing diagram of enable control circuit in Fig. 5 a；
Fig. 6 a are a kind of circuit diagram of initial frequency dividing circuit in Fig. 3；
Fig. 6 b are the timing diagram of initial frequency dividing circuit in Fig. 6 a；
Fig. 7 a are a kind of circuit diagram of frequency dividing comparison circuit in Fig. 3；
Fig. 7 b are the timing diagram of frequency dividing comparison circuit in Fig. 7 a
Fig. 8 a are a kind of circuit diagram of frequency dividing adjustment circuit in Fig. 3；
Fig. 8 b are the timing diagram of frequency dividing adjustment circuit in Fig. 8 a.
Specific embodiment
The present invention is described in further detail below by specific embodiment combination accompanying drawing.
Embodiment one：
In order to solve in the prior art when odd number or fractional frequency division clock signal is obtained, it is necessary to pass through the devices such as phaselocked loop
Part, the complicated problem of the circuit of odd number or fractional frequency division clock signal is obtained so as to cause, when the present embodiment provides a kind of frequency dividing
Clock signal acquiring method, the method can be performed by sub-frequency clock signal acquisition device, refer to Fig. 1：
S102, the frequency dividing numerical value initial frequency-dividing clock of acquisition according to target sub-frequency clock signal relative to external timing signal
Signal.
It is assumed that in the present embodiment, it is decimal that sub-frequency clock signal acquisition device needs the target clock fractional frequency signal for obtaining
Sub-frequency clock signal, the default dutycycle of such as clock signal of 4.5 frequency dividings, and the target sub-frequency clock signal is 50%, also
It is that in a cycle, high level and low level respectively account for half.Target clock fractional frequency signal is 4.5 frequency dividings, that is to say, that target
The a cycle of clock signal is equal to 4.5 cycles of external timing signal, in this 4.5 external clock cycles, when outside
Clock signal will experience 9 clocks and prolong, it may be possible to 4 rising edges and 5 trailing edges, it is also possible under 5 rising edges and four
Drop edge, in this case, in order to reach the requirement of the dutycycle of target clock fractional frequency signal 50%, sub-frequency clock signal obtains dress
Putting can first obtain initial clock fractional frequency signal, and progressively be adjusted on the basis of initial clock fractional frequency signal, Ke Yili
Solution, the dutycycle of the initial clock fractional frequency signal that sub-frequency clock signal acquisition device is easily obtained in the present embodiment can be with
It is any one in 1/9,2/9 ... 8/9, because just corresponding when high level is with low transition in these dutycycles
In the rising edge or trailing edge of external timing signal, thus can directly by the rising edge or trailing edge of external clock come
Control initial frequency-dividing clock high level and low level switching.
Due to finally needing for the initial duty cycle in initial clock fractional frequency signal to be adjusted to default dutycycle, therefore, it is
Simplified adjustment process, can select closest to default dutycycle, such as upper from the initial duty cycle being easily obtained
State 8 dutycycles, can using selective value closest to 50% 4/9 or 5/9 as initial clock fractional frequency signal initial duty cycle.It is right
It is same in other frequency dividing numerical value, such as the 3.5 target clock fractional frequency signals for dividing of 50% dutycycle, can be initial
The initial duty cycle of sub-frequency clock signal is defined as 3/7 or 4/7, so can as far as possible reduce initial sub-frequency clock signal and mesh
The gap of dutycycle between mark sub-frequency clock signal, so as to reduce the amount for needing adjustment, reduces adjustment number of times, when solving adjustment
Between, quickly obtain the target sub-frequency clock signal of needs.
S104, the default dutycycle based on target sub-frequency clock signal are in current initial sub-frequency clock signal a cycle
High level duration is carried out to the energy-storage travelling wave tube of specification identical first with the second energy-storage travelling wave tube respectively with low level duration
Charging energy-storing, and the electric energy that the two is stored is compared.
In order to realize the specific quantization to current initial sub-frequency clock signal dutycycle, currently can believe initial frequency-dividing clock
High level changes into the electric energy that can be compared on electricity field with the low level duration respectively in number a cycle, from
And realize the comparing to high level and low level width.In order to by the high level lasting time in initial frequency-dividing clock a cycle
And low duration is converted into electric energy, herein sub-frequency clock signal acquisition device can by the first energy-storage travelling wave tube with
Second energy-storage travelling wave tube is realized.
First energy-storage travelling wave tube high level duration in current initial clock fractional frequency signal a cycle is charged, the
Two energy-storage travelling wave tubes low level duration in current initial clock fractional frequency signal a cycle carries out charging energy-storing.Namely
Say, the charging interval of the first energy-storage travelling wave tube and the second energy-storage travelling wave tube is the dutycycle for being based on current initial sub-frequency clock signal come really
Fixed, and the charging rate of the first energy-storage travelling wave tube and the second energy-storage travelling wave tube can be according to the default duty of target sub-frequency clock signal
Than determining.It is comparator due to what is be generally compared to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube storage electric energy, and compares
Compared with the first input that device can only identify itself less than the second input, and the first input is more than or equal to second two kinds of feelings of input
Condition.It is two kinds of lines of demarcation of situation that first input is equal with the second input, therefore in the present embodiment, in order that comparator can
Identify that initial sub-frequency clock signal high level lasting time meets the situation of default dutycycle with low duration, should
The situation that the dutycycle of current initial sub-frequency clock signal is equal to default dutycycle is input into and the second input with comparator first
Equal situation is associated, that is, is associated with the first energy-storage travelling wave tube situation equal with the second energy-storage travelling wave tube storage electric energy
Come, directly to determine that initial point when comparator identifies that the first energy-storage travelling wave tube is equal with the second energy-storage travelling wave tube storage electric energy
The dutycycle of frequency clock signal has equalized to default dutycycle, that is, it is target to determine that initial sub-frequency clock signal has been adjusted to
Sub-frequency clock signal.
So, if the specification of two energy-storage travelling wave tubes is identical, the two storage electric energy number only be subject to the charging interval, charge speed
The influence of degree, and working as after initial sub-frequency clock signal is adjusted to target sub-frequency clock signal, the first energy-storage travelling wave tube and the second storage
Can be determined according to default dutycycle in charging interval of more element, if default dutycycle is N/M, the ratio between the two charging interval
It should be N：(M-N) it is, 1 to ensure the ratio between the two rechargeable electrical energy:1, then their charging rate should be set to (M-
N)：N.When it is 50% that sub-frequency clock signal acquisition device needs the dutycycle of the target sub-frequency clock signal for obtaining, the first storage
The charging rate of energy element and the second energy-storage travelling wave tube can be 1:1.
Sub-frequency clock signal acquisition device before being charged to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube, Ke Yixian
Determined for respective charging rate according to default dutycycle, after charging rate is determined, can be at current initial point
Frequency clock signal high level duration and low level duration to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube respectively according to
The charging rate determined carries out charging energy-storing.Sub-frequency clock signal acquisition device is in the first energy-storage travelling wave tube and the second energy-storage travelling wave tube
Bulk charge compares the electric energy of the first energy-storage travelling wave tube and the storage of the second energy-storage travelling wave tube after terminating.Sub-frequency clock signal acquisition device is usual
It is the voltage VC2 at voltage VC1 and the second energy-storage travelling wave tube two ends for comparing the first energy-storage travelling wave tube two ends by comparator.
It should be appreciated that above-mentioned situation directly determines the first energy-storage travelling wave tube and the second energy-storage travelling wave tube according to default dutycycle
The scheme of charging rate is only limitted to the first energy-storage travelling wave tube and energy storage governing factor suffered by the second energy-storage travelling wave tube only have the charging interval with
In the case of charging rate, when the two charging energy-storing also needs to be limited by other factors, also dutycycle may be being preset
On the basis of accounted for reference to other factors.
The first energy-storage travelling wave tube and the second energy-storage travelling wave tube in the present embodiment can be the various phases with electrical power storage ability
Between, including inductance, electric capacity and etc. the rechargeable battery with charging ability, certainly, it is contemplated that sub-frequency clock signal acquisition device
The influence of space for its deployment and other factors on the ic chip, can select electric capacity as energy-storage travelling wave tube in real process.
S106, when comparative result characterizes the current dutycycle of initial sub-frequency clock signal and is not equal to default dutycycle, by
High level and low level duration in the step increase and decrease current initial sub-frequency clock signal of adjustment, to initial sub-frequency clock signal into
It is target sub-frequency clock signal.
If VC1 is unequal with VC2, illustrates the dutycycle of current initial sub-frequency clock signal also and be not equal to target point
The default dutycycle of frequency clock signal, should continue to be adjusted the dutycycle of current initial sub-frequency clock signal, during frequency dividing
Clock signal acquisition device is progressively increased and decreased, for example, obtaining when adjustment current initial sub-frequency clock signal dutycycle
The initial duty cycle of the initial sub-frequency clock signal for obtaining is 3/7, then during follow-up, sub-frequency clock signal acquisition device meeting
Dutycycle to initial sub-frequency clock signal is stepped up, and increased granularity all can be smaller every time.Obviously, if
Initial duty cycle is 4/7, then need progressively to reduce initial duty cycle.When sub-frequency clock signal acquisition device is to initial frequency-dividing clock
After the dutycycle adjustment of signal, then recharge and the process for comparing once more, certainly it should be understood by those skilled in the art that
, before carrying out charging energy-storing to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube again, should by the first energy-storage travelling wave tube with
The energy of the second energy-storage travelling wave tube storage originally is all discharged, and can otherwise cause comparative result below the problem of mistake occur.
Whenever sub-frequency clock signal acquisition device compare the first energy-storage travelling wave tube and the second energy-storage travelling wave tube storage energy not
It is equal, then will continue to adjust to continue to be adjusted dutycycle on the basis of initial sub-frequency clock signal current duty cycle, by
It is smaller in the granularity of each adjustment, accordingly, it is possible to be directed to an initial sub-frequency clock signal and may need to adjust repeatedly can just make
The target sub-frequency clock signal that default dutycycle is equal to as dutycycle.Although adjustment granularity is smaller, it is necessary to by multiple
Adjustment, extends adjustment time, but adjustment granularity is smaller, then the dutycycle for finally giving will get over default dutycycle and connect
Closely.
In the present embodiment, in order to realize the progressively adjustment to dutycycle, sub-frequency clock signal acquisition device can be used
Delay chain is carried out.The structure of delay chain can be with as shown in Fig. 2 delay chain 2 includes multiple time delay parts, and each time delay part prolongs
Shi Nengli be able to can also be differed with identical, but in the present embodiment, the process for the ease of adjusting dutycycle can be according to equal
Even granularity is carried out, then can be set to the delay-capacity of each time delay part in each delay chain 2 identical.Time delay part 21, prolongs
When part 22 ... time delay part n be connected in series, in delay chain 2, the number for participating in the time delay part of work can be parallel to by multiple
The switch of output end 20 is controlled.
It is understood that sub-frequency clock signal acquisition device is compared by the dutycycle of initial sub-frequency clock signal
Compared with when, except utilizing delay chain, in addition it is also necessary to by the effect of other logic circuits.When sub-frequency clock signal acquisition device exists
Certain is once adjusted after time delay even, and the first energy storage is found after being charged to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube again
Electric energy between element and the second energy-storage travelling wave tube is equal, then now can determine that initial sub-frequency clock signal has been adjusted to mesh
Mark sub-frequency clock signal.Now, sub-frequency clock signal acquisition device can keep the length of the delay chain for now participating in work, with
Just target sub-frequency clock signal is persistently exported.Certain sub-frequency clock signal acquisition device can also record current delay chain length,
When needing to obtain again the target sub-frequency clock signal later, can be directly according to record it is determined that how much control prolongs
When part participation work, it is to avoid the process for adjusting again.
In the present embodiment, sub-frequency clock signal acquisition device carries out the initiating process of charging energy-storing to the first energy-storage travelling wave tube
Must be kept with the end time with the initial time of high level in current initial sub-frequency clock signal a cycle with terminal procedure
Unanimously, likewise, for the charging process of the second energy-storage travelling wave tube, then must be low level with current initial sub-frequency clock signal
Initial time is consistent with the end time.So sub-frequency clock signal acquisition device is also needed to the first energy storage in the present embodiment
Element, the second energy-storage travelling wave tube charge, and the beginning that electric energy such as compares at the process is controlled with end.
The sub-frequency clock signal acquisition methods that the present embodiment is provided, first get the initial frequency-dividing clock letter being easily obtained
Number, and by high level in current initial clock fractional frequency signal and the respective duration of low level change into the first energy-storage travelling wave tube with
Second energy-storage travelling wave tube stores the size of electric energy, is then compared, and according to the current initial clock of comparative result feedback adjustment point
The high level of frequency signal and low level duration, so as to reach the purpose of adjustment initial clock fractional frequency signal dutycycle.
Before first energy-storage travelling wave tube is equal with the second energy-storage travelling wave tube storage electric energy, current initial clock point is constantly adjusted according to comparative result
High level meets default dutycycle with the low level duration in frequency signal.Relative to obtaining default duty using phaselocked loop
The scheme of the clock division signal of ratio, the sub-frequency clock signal acquisition device that the present invention is provided realizes that circuit is more simple, and
The target odd number or decimal clock division signal of various dutycycles can be according to demand got, the control need of IC chip are met
Ask.And the required region of sub-frequency clock signal acquisition device deployment is also smaller, can reduce to IC chip deployment region
Take.
Embodiment two：
The present embodiment provides a kind of sub-frequency clock signal acquisition device, refers to Fig. 3, sub-frequency clock signal acquisition device 30
Including initial frequency dividing circuit 302, frequency dividing comparison circuit 304, frequency dividing adjustment circuit 306, initial frequency dividing circuit 302 is used for according to mesh
Mark sub-frequency clock signal obtains initial sub-frequency clock signal relative to the frequency dividing numerical value of external timing signal.As shown in figure 4, frequency dividing
Comparison circuit 304 includes specification identical the first energy-storage travelling wave tube 3041 and the second energy-storage travelling wave tube 3042 and the He of comparing unit 3043
Control unit 3044；The default dutycycle that control unit 3043 is based on target sub-frequency clock signal is believed in current initial frequency-dividing clock
In number a cycle high level duration and low level duration respectively to the first energy-storage travelling wave tube of specification identical 3041 with
Second energy-storage travelling wave tube 3042 carries out charging energy-storing, and comparing unit 3043 is used for the first energy-storage travelling wave tube 3041 and the second energy-storage travelling wave tube
The electric energy of 3042 storages is compared；Frequency dividing adjustment circuit 306 is used to characterize the initial sub-frequency clock signal when comparative result
When current dutycycle is not equal to default dutycycle, progressively increase and decrease adjusts high level and low electricity in current initial sub-frequency clock signal
The flat duration, target sub-frequency clock signal is turned into initial sub-frequency clock signal.
It is assumed that in the present embodiment, it is fractional frequency division that initial frequency dividing circuit 302 needs the target clock fractional frequency signal for obtaining
Clock signal, the default dutycycle of such as clock signal of 4.5 frequency dividings, and the target sub-frequency clock signal is 50%, that is,
In a cycle, high level and low level respectively account for half.Target clock fractional frequency signal is 4.5 frequency dividings, that is to say, that target clock
The a cycle of signal is equal to 4.5 cycles of external timing signal, in this 4.5 external clock cycles, external clock letter
Number will experience 9 clocks prolongs, it may be possible to 4 rising edges and 5 trailing edges, it is also possible to 5 rising edges and four trailing edges,
In this case, in order to reach the requirement of the dutycycle of target clock fractional frequency signal 50%, initial frequency dividing circuit 302 can be obtained first
Initial clock fractional frequency signal is taken, and is progressively adjusted on the basis of initial clock fractional frequency signal, it is to be understood that at this
The dutycycle of the initial clock fractional frequency signal that initial frequency dividing circuit 302 is easily obtained can be 1/9,2/9 ... 8/9 in embodiment
In any one because exactly corresponding to external timing signal when high level and low transition in these dutycycles
Rising edge or trailing edge, therefore initial frequency-dividing clock can be directly controlled by the rising edge or trailing edge of external clock
High level and low level switching.
Due to finally needing for the initial duty cycle in initial clock fractional frequency signal to be adjusted to default dutycycle, therefore, it is
Simplified adjustment process, initial frequency dividing circuit 302 can be selected closest to default duty from the initial duty cycle being easily obtained
Ratio, such as above-mentioned 8 dutycycles, can be using selective value closest to 50% 4/9 or 5/9 as initial clock fractional frequency signal
Initial duty cycle.Same for other frequency dividing numerical value, such as the target clock for 3.5 frequency dividings of 50% dutycycle is divided
The initial duty cycle of initial sub-frequency clock signal can be defined as 3/7 or 4/7 by signal, initial frequency dividing circuit 302, so can
The gap of dutycycle between initial sub-frequency clock signal and target sub-frequency clock signal is reduced as far as possible, so as to reduce need adjustment
Amount, reduce adjustment number of times, solve adjustment time, quickly obtain the target sub-frequency clock signal of needs.
In the present embodiment, sub-frequency clock signal acquisition device also includes enabling control circuit, and enabling control circuit is used for
Work enable to initial frequency dividing circuit 302, frequency dividing comparison circuit 304 and frequency dividing adjustment circuit 306 is controlled, it is determined that point
When each several part starts working in frequency clock signal acquisition device 30.Due to being controlled by signal clock edge
The work of each several part processed, therefore a kind of enable control circuit that can be produced and enable control signal is provided in the present embodiment, such as
Shown in Fig. 5 a：
Enabling control circuit includes register X1.Triggered by rising edge clock.In the middle of the example, when register is multiple
During position, its output is equal to 0, that is, logic low." rst " is the reset signal of circuit, works as rst=0, and register X1 is answered
Position, now, the output net2=0 of X1.When reset signal is released, i.e. rst=0 becomes rst=1, and register X1 starts working：
When there is first rising edge of clk_in, net2 becomes " 1 " from " 0 ".When occur second rising edge of clk_in, net1 from
" 1 " becomes " 0 ", specifically may be referred to the timing diagram that Fig. 5 b are provided.
Accompanying drawing 6a gives the circuit diagram that a kind of initial frequency dividing circuit obtains initial sub-frequency clock signal, it is assumed that the present embodiment
It is middle need obtain target sub-frequency clock signal be 3.5 frequency dividings and dutycycle be 50% signal, with reference to specific example pair
The structure of initial frequency dividing circuit is illustrated：
In the middle of initial frequency dividing circuit, including register X3, X4, X5, X6 and phase inverter X7, X9, X10, X14, with door X8,
X11, X15, PMOS device X12, X17 and nmos device X13, X16.When sel=" 0 ", clock falling edge trigger register；
When sel=" 1 ", rising edge clock trigger register.In the middle of Fig. 6 a, the sel ends of net8 connection registers X3, X4, X5, X6
Mouthful.When net8=" 1 ", register X3, X4, X5, X6 are triggered by rising edge clock；When net8=" 0 ", register X3, X4,
X5, X6 are triggered by clock falling edge.When rst=" 0 ", net2 resets to initial frequency dividing circuit, the acquiescence output after reset
It is net4=" 1 ", net5=" 1 ", net6=" 0 ", net7=" 0 ", net8=" 0 ".Due to net2=" 0 ", therefore now
Net9=" 0 ".When reset signal release, net2 from " 0 " become " 1 " when, net2 and net5 pass through and gate logic treatment so that
Net9 becomes " 1 " from " 0 ".Now X3, X4, X5, X6 start working.Initial frequency dividing circuit starts its first job state：
Because now net8=" 0 ", 4 registers are all the trailing edge triggerings for giving tacit consent to clk_in, when first
When clk_in trailing edges are reached, net4=" 0 ", net5=" 1 ", net6=" 0 ", net7=" 0 ", net8=" 0 ", net9=
“1”.When second clk_in trailing edge is reached, net4=" 0 ", net5=" 0 ", net6=" 1 ", net7=" 0 ", net8=
" 0 ", net9=" 0 ".When there is the 3rd trailing edge, net4=" 0 ", net5=" 0 ", net6=" 1 ", net7=" 1 ",
Net8=" 0 ", net9=" 0 ".When there is the 4th trailing edge, net4=" 0 ", net5=" 0 ", net6=" 1 ", net7=
" 1 ", net8=" 1 ", net9=" 0 ".
Now, the output of net8 becomes " 1 " from " 0 ", therefore, register X3, X4, X5, X6 becomes by rising edge clock
Triggering.Hereafter, circuit enters second working condition：When first clk_in rising edge of appearance, net4=" 1 ", net5=
" 0 ", net6=" 1 ", net7=" 1 ", net8=" 1 ", net9=" 0 ".Reached when there is second clk_in rising edge, net4
=" 1 ", net5=" 1 ", net6=" 0 ", net7=" 1 ", net8=" 1 ", net9=" 1 ".When on the 3rd clk_in of appearance
Rise along arrival, net4=" 1 ", net5=" 1 ", net6=" 0 ", net7=" 0 ", net8=" 1 ", net9=" 1 ".When occurring the
During four clk_in rising edges, net4=" 1 ", net5=" 1 ", net6=" 0 ", net7=" 0 ", net8=" 0 ", net9=
“1”。
Now the value of net8 is changed into " 0 " from " 1 " again, so four registers revert to clock falling edge triggering again, i.e.,
Return to the first job state of circuit.By that analogy, initial frequency dividing circuit will work in first job state and second
Circulated between state.From can be seen that initial frequency dividing circuit in the middle of Fig. 6 a, work as net7=0, after net10 is negated equal to net8
Exported with logic with net9.As net7=1, net10 is equal to being exported with logic for the inverted signal of net8 and net9.Each is defeated
The specific timing diagram for going out is as shown in Figure 6 b.By initial frequency dividing circuit, when can obtain the output that dutycycle is 7/3rds
Clock.
In order to realize the specific quantization to current initial sub-frequency clock signal dutycycle, can be by currently initial frequency-dividing clock
High level changes into the electric energy that can be compared on electricity field with the low level duration respectively in signal a cycle,
So as to realize the comparing to high level and low level width.During in order to the high level in initial frequency-dividing clock a cycle being continued
Between and low duration be converted into electric energy, comparison circuit 304 is divided herein can be by the first energy-storage travelling wave tube and the
Two energy-storage travelling wave tubes are realized.
First energy-storage travelling wave tube high level duration in current initial clock fractional frequency signal a cycle is charged, the
Two energy-storage travelling wave tubes low level duration in current initial clock fractional frequency signal a cycle carries out charging energy-storing.Namely
Say, the charging interval of the first energy-storage travelling wave tube and the second energy-storage travelling wave tube is the dutycycle for being based on current initial sub-frequency clock signal come really
Fixed, and the charging rate of the first energy-storage travelling wave tube and the second energy-storage travelling wave tube can be according to the default duty of target sub-frequency clock signal
Than determining.It is comparator due to what is be generally compared to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube storage electric energy, and compares
Compared with the first input that device can only identify itself less than the second input, and the first input is more than or equal to second two kinds of feelings of input
Condition.It is two kinds of lines of demarcation of situation that first input is equal with the second input, therefore in the present embodiment, in order that comparator can
Identify that initial sub-frequency clock signal high level lasting time meets the situation of default dutycycle with low duration, should
The situation that the dutycycle of current initial sub-frequency clock signal is equal to default dutycycle is input into and the second input with comparator first
Equal situation is associated, that is, is associated with the first energy-storage travelling wave tube situation equal with the second energy-storage travelling wave tube storage electric energy
Come, directly to determine that initial point when comparator identifies that the first energy-storage travelling wave tube is equal with the second energy-storage travelling wave tube storage electric energy
The dutycycle of frequency clock signal has equalized to default dutycycle, that is, it is target to determine that initial sub-frequency clock signal has been adjusted to
Sub-frequency clock signal.
So, if the specification of two energy-storage travelling wave tubes is identical, the two storage electric energy number only be subject to the charging interval, charge speed
The influence of degree, and working as after initial sub-frequency clock signal is adjusted to target sub-frequency clock signal, the first energy-storage travelling wave tube and the second storage
Can be determined according to default dutycycle in charging interval of more element, if default dutycycle is N/M, the ratio between the two charging interval
It should be N：(M-N) it is, 1 to ensure the ratio between the two rechargeable electrical energy:1, then their charging rate should be set to (M-
N)：N.When it is 50% that sub-frequency clock signal acquisition device 30 needs the dutycycle of the target sub-frequency clock signal for obtaining, first
The charging rate of energy-storage travelling wave tube and the second energy-storage travelling wave tube can be 1:1.
Frequency dividing comparison circuit 304, can first basis before being charged to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube
Default dutycycle is determined for respective charging rate, after charging rate is determined, can be in current initial frequency dividing
Clock signal high level duration and low level duration are to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube respectively according to determination
The charging rate for going out carries out charging energy-storing.Frequency dividing comparison circuit 304 is in the first energy-storage travelling wave tube and the second energy-storage travelling wave tube bulk charge knot
Compare the electric energy of the first energy-storage travelling wave tube and the storage of the second energy-storage travelling wave tube after beam.Compare the first energy storage unit generally by comparator
The voltage VC1 at the part two ends and voltage VC2 at the second energy-storage travelling wave tube two ends.
It should be appreciated that above-mentioned situation directly determines the first energy-storage travelling wave tube and the second energy-storage travelling wave tube according to default dutycycle
The scheme of charging rate is only limitted to the first energy-storage travelling wave tube and energy storage governing factor suffered by the second energy-storage travelling wave tube only have the charging interval with
In the case of charging rate, when the two charging energy-storing also needs to be limited by other factors, also dutycycle may be being preset
On the basis of accounted for reference to other factors.
The first energy-storage travelling wave tube and the second energy-storage travelling wave tube in the present embodiment can be the various phases with electrical power storage ability
Between, including inductance, electric capacity and etc. the rechargeable battery with charging ability, certainly, it is contemplated that sub-frequency clock signal acquisition device
The influence of 30 space for its deployment and other factors on the ic chip, can select electric capacity as energy storage unit in real process
Part.
Frequency dividing comparison circuit 304 is introduced with reference to Fig. 7：The frequency dividing comparison circuit 304 shown in Fig. 7 a is included
Phase inverter X501, X404, X401, X403, X441, X442, and door X405, X402, OR gate X502, X440, the first electric capacity X409,
Second electric capacity X410, nmos device X408, X411, PMOS device X406, X407, and comparator X412.Timing diagram such as Fig. 7 b
It is shown.Before the T1 moment arrives, when net23=" 1 ", nmos device X408, X411 are respectively rapidly to the first electric capacity X409, the
Two electric capacity X410 discharge, until the electric charge on two electric capacity is equal to 0.When net23=" 0 ", and net21=0, current source X406 points
It is other that first electric capacity X409 is charged, until the T2 moment.Since the T2 moment, net23=" 0 ", net28=0, current source X406 pairs
Second electric capacity X410 is started to charge up, until the T3 moment；When net23=" 0 ", net28=1, net23=0, current source do not charge.
It is understood that the charging interval is more long, the electric charge accumulated on electric capacity is more, and magnitude of voltage is also higher.Comparator X412 compares
The voltage of the first electric capacity X409 and the second electric capacity X410, and send out a comparative result：Net10 is illustrated that current first in Fig. 7 b
The timing diagram of beginning sub-frequency clock signal, and the high level in net10 is correspondingly changed into the low level of net21, its low level quilt
Change into the low level of net28, therefore, although substantially or net10 high level duration to the first electric capacity X409
Charge, low level duration charges to the second electric capacity X410, but present be converted to by the low level control the of net21
One electric capacity X409 charges, and the second electric capacity of low level control X410 of net28 charges.When the low level of net21 is than net28's
Low level is narrow, then the electric charge for being accumulated on the first electric capacity X409 will be fewer than the electric charge on the second electric capacity X410, the first electric capacity X409
On voltage can be lower than the voltage of the second electric capacity X410, compare by comparator X412DE, will output net322 be equal to " 1 ", than
Relatively result will be latched into register X710 at the T4 moment by the trailing edge of net10.
If VC1 is unequal with VC2, illustrates the dutycycle of current initial sub-frequency clock signal also and be not equal to target point
The default dutycycle of frequency clock signal, frequency dividing adjustment circuit 306 should continue the dutycycle to current initial sub-frequency clock signal
It is adjusted, frequency dividing adjustment circuit 306 is progressively to be increased and decreased when adjustment current initial sub-frequency clock signal dutycycle
, for example, the initial duty cycle of the initial sub-frequency clock signal for obtaining is 3/7, then during follow-up, divide adjustment circuit
306 can be stepped up to the dutycycle of initial sub-frequency clock signal, and increased granularity all can be smaller every time.It is aobvious
So, if initial duty cycle is 4/7, need progressively to reduce initial duty cycle.When the initially frequency dividing of adjustment circuit 306 pairs is divided
After the dutycycle adjustment of clock signal, then recharge and the process for comparing once more, certain those skilled in the art should manage
Solution, before carrying out charging energy-storing to the first energy-storage travelling wave tube 3041 and the second energy-storage travelling wave tube 3042 again, should be by first
The energy of the storage originally of 3041 and second energy-storage travelling wave tube of energy-storage travelling wave tube 3042 is all discharged, and can otherwise cause comparative result below
There is the problem of mistake.
Whenever frequency dividing adjustment circuit 306, to compare the first energy-storage travelling wave tube unequal with the energy that the second energy-storage travelling wave tube is stored,
Then will continue to adjust to continue to be adjusted dutycycle on the basis of initial sub-frequency clock signal current duty cycle, due to each
The granularity of adjustment is smaller, repeatedly can just be made accordingly, it is possible to be directed to an initial sub-frequency clock signal and may need to adjust
Dutycycle is equal to the target sub-frequency clock signal of default dutycycle.Although adjustment granularity is smaller, it is necessary to by repeatedly adjustment, prolong
Grown adjustment time, but adjustment granularity is smaller, then the dutycycle for finally giving will with default dutycycle closer to.
In the present embodiment, in order to realize the progressively adjustment to dutycycle, frequency dividing adjustment circuit 306 can use delay chain
To carry out dutycycle adjustment, frequency dividing adjustment circuit 306 includes adjustment control unit and delay chain, as shown in Fig. 8 a and Fig. 8 b：
Frequency dividing adjustment circuit include register X710, X710_1, X710_2, X710_3 ... X710_N, X710_N+1,
Buffer X432_0, buffer X432_1, buffer X432_2, buffer X432_3 ..., buffer X432_N, buffer
X432_N+1.Switch Q0, Q1, Q2, Q3, Q4 ..., QN, QN+1.
When the comparator output result of first time net10 collections is equal to 1, then switch Q1, net10=net622_1 are opened,
Other switches are closed.When the comparator output result of second net10 collection is equal to 1, then switch Q2, net900=are opened
Net622_2, other switches are closed.By net10 some clock cycle, the comparator output result of net10 collections is equal to 1, then
Switch Q2net900=net622_N is opened, when the N+1 cycle, when the comparator output result of net10 collections is equal to 0, i.e.,
Represent that the high level lasting time and low duration of net10 are in equal critical point.Now net322=0, shields
Divide the input clock of all registers of adjustment circuit.The value of register is constant, i.e. Q2net900=net622_N.So as to real
The fractional frequency division clock circuit of dutycycle 50% is showed, timing diagram is as shown in Figure 8 b.
It is understood that frequency dividing adjustment circuit 306 is when the dutycycle to initial sub-frequency clock signal is compared
Wait, except utilizing delay chain, in addition it is also necessary to by the effect of other logic circuits.When frequency dividing adjustment circuit 306 is once adjusted at certain
After delay chain, the first energy-storage travelling wave tube and second are found after being charged to the first energy-storage travelling wave tube and the second energy-storage travelling wave tube again
Electric energy between energy-storage travelling wave tube is equal, then now can determine that initial sub-frequency clock signal has been adjusted to target frequency-dividing clock
Signal.Now, the adjustment control unit in frequency dividing adjustment circuit 306 can keep the length of the delay chain for now participating in work,
So as to lasting output target sub-frequency clock signal.Certainly adjustment control unit can also record current delay chain length, after
When needing to obtain again the target sub-frequency clock signal, can be directly according to record it is determined that controlling how many time delay parts to join
With work, it is to avoid the process that adjusts again.
The sub-frequency clock signal acquisition device that the present embodiment is provided, first gets the initial frequency-dividing clock letter being easily obtained
Number, and by high level in current initial clock fractional frequency signal and the respective duration of low level change into the first energy-storage travelling wave tube with
Second energy-storage travelling wave tube stores the size of electric energy, is then compared, and according to the current initial clock of comparative result feedback adjustment point
The high level of frequency signal and low level duration, so as to reach the purpose of adjustment initial clock fractional frequency signal dutycycle.
Before first energy-storage travelling wave tube is equal with the second energy-storage travelling wave tube storage electric energy, current initial clock point is constantly adjusted according to comparative result
High level meets default dutycycle with the low level duration in frequency signal.Relative to obtaining default duty using phaselocked loop
The scheme of the clock division signal of ratio, the sub-frequency clock signal acquisition device that the present invention is provided realizes that circuit is more simple, and
The target odd number or decimal clock division signal of various dutycycles can be according to demand got, the control need of IC chip are met
Ask.And the required region of sub-frequency clock signal acquisition device deployment is also smaller, can reduce to IC chip deployment region
Take.
Obviously, those skilled in the art should be understood that each module or each step of the invention described above can be with general
Computing device realizes that they can be concentrated on single computing device, or be distributed in what multiple computing devices were constituted
On network, alternatively, they can be realized with the executable program code of computing device, it is thus possible to be stored in
Performed by computing device in computer-readable storage medium (ROM/RAM, magnetic disc, CD), and in some cases, can be with not
The order being same as herein performs shown or described step, or they are fabricated to each integrated circuit modules respectively, or
Multiple modules or step in them are fabricated to single integrated circuit module to realize by person.So, the present invention is not restricted to appoint
What specific hardware and software is combined.
Above content is to combine specific embodiment further description made for the present invention, it is impossible to assert this hair
Bright specific implementation is confined to these explanations.For general technical staff of the technical field of the invention, do not taking off
On the premise of present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to protection of the invention
Scope.
Claims (10)
1. a kind of sub-frequency clock signal acquisition methods, including：
Initial sub-frequency clock signal is obtained relative to the frequency dividing numerical value of external timing signal according to target sub-frequency clock signal；
Default dutycycle based on target sub-frequency clock signal electricity high in current initial sub-frequency clock signal a cycle
Flat duration charges to the energy-storage travelling wave tube of specification identical first with the second energy-storage travelling wave tube respectively with low level duration
Energy storage, and the electric energy that first energy-storage travelling wave tube is stored with second energy-storage travelling wave tube is compared；
When comparative result characterizes the current dutycycle of the initial sub-frequency clock signal is not equal to default dutycycle, progressively increase and decrease
High level and low level duration in the current initial sub-frequency clock signal of adjustment, turn into the initial sub-frequency clock signal
Target sub-frequency clock signal.
2. sub-frequency clock signal acquisition methods as claimed in claim 1, it is characterised in that first energy-storage travelling wave tube with it is described
Second energy-storage travelling wave tube is electric capacity.
3. sub-frequency clock signal acquisition methods as claimed in claim 1 or 2, it is characterised in that when being divided based on the target
The default dutycycle of clock signal high level duration in current initial sub-frequency clock signal a cycle continues with low level
Period carries out charging energy-storing to the energy-storage travelling wave tube of specification identical first and the second energy-storage travelling wave tube respectively to be included：
Default dutycycle according to the target sub-frequency clock signal determine respectively to for first energy-storage travelling wave tube with it is described
The ratio between the charging rate of the second energy-storage travelling wave tube, first energy-storage travelling wave tube and charging rate of second energy-storage travelling wave tube are described
The ratio between low level and high level duration under default dutycycle；
Control first energy-storage travelling wave tube and second energy-storage travelling wave tube according to for respective charging rate respectively in high level
Duration, low level duration carry out charging energy-storing.
4. a kind of sub-frequency clock signal acquisition device, it is characterised in that including：
Initial frequency dividing circuit, for obtaining initial relative to the frequency dividing numerical value of external timing signal according to target sub-frequency clock signal
Sub-frequency clock signal；
Frequency dividing comparison circuit, including control unit, comparing unit and the energy-storage travelling wave tube of specification identical first and the second energy storage unit
Part；Described control unit is based on the default dutycycle of the target sub-frequency clock signal in current initial sub-frequency clock signal one
High level duration is first to the energy-storage travelling wave tube of specification identical first and the second energy storage respectively with low level duration in cycle
Part carries out charging energy-storing；The comparing unit is used for the electric energy stored with second energy-storage travelling wave tube to first energy-storage travelling wave tube
It is compared；
Frequency dividing adjustment circuit, for when comparative result characterize the current dutycycle of the initial sub-frequency clock signal be not equal to it is default
During dutycycle, progressively increase and decrease high level and low level duration in the current initial sub-frequency clock signal of adjustment, it is extremely described first
Beginning sub-frequency clock signal turns into target sub-frequency clock signal.
5. sub-frequency clock signal acquisition device as claimed in claim 4, it is characterised in that first energy-storage travelling wave tube with it is described
Second energy-storage travelling wave tube is electric capacity.
6. sub-frequency clock signal acquisition device as claimed in claim 4, it is characterised in that described control unit is according to the mesh
The default dutycycle for marking sub-frequency clock signal determines to for first energy-storage travelling wave tube and second energy-storage travelling wave tube respectively
Charging rate, and control first energy-storage travelling wave tube to exist respectively according to for respective charging rate with second energy-storage travelling wave tube
High level duration, low level duration carry out charging energy-storing, first energy-storage travelling wave tube and second energy-storage travelling wave tube
The ratio between charging rate be the ratio between low level and high level duration under the default dutycycle.
7. sub-frequency clock signal acquisition device as claimed in claim 6, it is characterised in that the target sub-frequency clock signal is
The sub-frequency clock signal of 50% dutycycle, the charging rate phase between first energy-storage travelling wave tube and second energy-storage travelling wave tube
Deng.
8. sub-frequency clock signal acquisition device as claimed in claim 4, it is characterised in that also including enabling control circuit, institute
State and enable control circuit for the work to the initial frequency dividing circuit, the frequency dividing comparison circuit and the frequency dividing adjustment circuit
Enable.
9. the sub-frequency clock signal acquisition device as described in claim any one of 4-8, it is characterised in that the frequency dividing adjustment electricity
Road includes adjustment control unit and delay chain, and the adjustment control unit determines to participate according to the comparative result of the comparing unit
The length of the delay chain of work.
10. sub-frequency clock signal acquisition device as claimed in claim 9, it is characterised in that the adjustment control unit also with
In the case of determining that first energy-storage travelling wave tube is equal with second energy-storage travelling wave tube storage electric energy in the comparing unit
Record and keep currently to participate in the delay chain length of work.
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| CN201611132496.3A CN106712747A (en) | 2016-12-09 | 2016-12-09 | Frequency dividing clock signal acquisition method and apparatus |
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| CN110011659A (en) * | 2019-04-15 | 2019-07-12 | 上海安路信息科技有限公司 | Frequency divider and its chip |
| CN111313893A (en) * | 2020-02-28 | 2020-06-19 | 深圳市紫光同创电子有限公司 | Frequency divider and electronic device |
| CN114221642A (en) * | 2022-02-22 | 2022-03-22 | 浙江地芯引力科技有限公司 | PWM wave generation and duty ratio control method, device, timer and equipment |
| WO2023221230A1 (en) * | 2022-05-19 | 2023-11-23 | 长鑫存储技术有限公司 | Time delay circuit and memory |
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