CN111192609A - Clock duty ratio calibration circuit and calibration method - Google Patents
Clock duty ratio calibration circuit and calibration method Download PDFInfo
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- CN111192609A CN111192609A CN201811363215.4A CN201811363215A CN111192609A CN 111192609 A CN111192609 A CN 111192609A CN 201811363215 A CN201811363215 A CN 201811363215A CN 111192609 A CN111192609 A CN 111192609A
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Abstract
The embodiment of the invention provides a clock duty ratio calibration circuit and a calibration method, wherein the circuit comprises: a transmission circuit for receiving an input clock signal and transmitting an output clock signal, having a first node and a second node; a first pull-down circuit connected to the first node and discharging the first node; a second pull-down circuit connected to the second node to discharge the second node; the first pull-down current regulating circuit is connected with the first pull-down circuit, and changes the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal; and the second pull-down current regulating circuit is connected with the second pull-down circuit, and changes the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal. According to the embodiment of the invention, different nodes on the transmission circuit are discharged, so that the duty ratio of the output clock signal can be quickly and accurately adjusted to about 50%.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a clock duty ratio calibration circuit and a calibration method.
Background
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
In the field of DRAM (Dynamic Random Access Memory), DDR (Double Data Rate SDRAM) technology triggers reading Data on both the upper and lower edges of the clock, so a clock with a good duty cycle is also more important in the DRAM field. The existing clock calibration circuit can not realize rapid and accurate adjustment of the duty ratio of a clock signal, so that the correctness of the whole DRAM for reading data can not be ensured.
Disclosure of Invention
Embodiments of the present invention provide a clock duty ratio calibration circuit and a calibration method, so as to at least alleviate or solve one or more technical problems in the prior art.
In a first aspect, an embodiment of the present invention provides a clock duty ratio calibration circuit, including:
a transmission circuit for receiving an input clock signal and transmitting an output clock signal, the transmission circuit having at least one set of a first node and a second node;
a first pull-down circuit connected between the first node and a ground line for discharging the first node;
the second pull-down circuit is connected between the second node and the ground wire and used for discharging the second node;
the first pull-down current regulating circuit is connected with the first pull-down circuit and used for changing the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal;
and the second pull-down current regulating circuit is connected with the second pull-down circuit and used for changing the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal.
In some embodiments, the transmission circuit includes a plurality of buffers connected in series, and an inverter is connected between two adjacent buffers; the input and output of one of the inverters form a first node and a third node, respectively, and the input and output of the other inverter form a second node and a fourth node, respectively.
In some embodiments, the first pull-down current regulation circuit comprises:
the drain electrode and the grid electrode of the first current transistor are connected together to form a first connecting point, and the first current generated by the first connecting point and the pull-down current of the first node form mirror current;
the drain electrode of the first switch transistor is connected with the source electrode of the first current transistor, the source electrode of the first switch transistor is connected with the ground wire, and the grid electrode of the first switch transistor is connected with the power supply voltage;
and the first root current regulating circuit is connected with the first connecting point and is used for regulating the first root current according to the first pull-down current control signal.
In some embodiments, the first pull-down circuit includes:
the grid electrode of the first mirror image transistor is connected with a first connecting point, and the drain electrode of the first mirror image transistor is connected with a first node;
and the grid electrode of the second switch transistor is connected with the third node, the drain electrode of the second switch transistor is connected with the source electrode of the first mirror image transistor, and the source electrode of the second switch transistor is connected with the ground wire.
In some embodiments, the second pull-down current regulation circuit comprises:
the drain electrode and the grid electrode of the second current transistor are connected together to form a second connection point, and a second current generated by the second connection point and the pull-down current of a second node form mirror current;
the drain electrode of the third switching transistor is connected with the source electrode of the second current transistor, the source electrode of the third switching transistor is connected with the ground wire, and the grid electrode of the third switching transistor is connected with the power supply voltage;
and the second current regulating circuit is connected to the second connection point and used for regulating a second current according to the second pull-down current control signal.
In some embodiments, the second pull-down circuit comprises:
the grid electrode of the second mirror image transistor is connected with a second connection point, and the drain electrode of the second mirror image transistor is connected with a second node;
and the grid electrode of the fourth switching transistor is connected with the fourth node, the drain electrode of the fourth switching transistor is connected with the source electrode of the second mirror image transistor, and the source electrode of the fourth switching transistor is connected with the ground wire.
In some embodiments, the transmission circuit has a plurality of sets of first nodes and second nodes, each first node being connected to one first pull-down circuit and each second node being connected to one second pull-down circuit.
In a second aspect, an embodiment of the present invention provides a calibration method for a clock duty ratio calibration circuit, including:
the first pull-down current regulating circuit changes the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal;
the second pull-down current regulating circuit changes the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal.
In some embodiments, an input of an inverter of the transmission circuit forms the first node, an output of the inverter forms the third node, and the calibration method further comprises:
when the first pull-down current regulating circuit is connected with the first node and the clock signal at the third node is at a high level, the first pull-down circuit discharges the first node.
In some embodiments, an input of another inverter of the transmission circuit forms the second node and an output of the other inverter forms the fourth node, the calibration method further comprising:
when the second pull-down current regulating circuit is connected to the second node and the clock signal at the fourth node is at a high level, the second pull-down circuit is connected to discharge the second node.
In a third aspect, an embodiment of the present invention provides a semiconductor memory, including the above clock duty ratio calibration circuit.
The embodiment of the invention adopts the technical scheme, and has the following advantages: by discharging different nodes on the transmission circuit, the duty ratio of the output clock signal of the transmission circuit is quickly and accurately adjusted to about 50%.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
FIG. 1 is a schematic diagram of a clock duty cycle calibration circuit according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of the connection of a clock duty cycle calibration circuit to other circuits according to an embodiment of the present invention;
FIG. 3 is a flowchart of a calibration method of a clock duty cycle calibration circuit according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of clock signals at nodes on a transmission circuit, in accordance with one embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a waveform change of a clock signal at each node on a transmission circuit according to an embodiment of the present invention.
Reference numerals:
100-a transmission circuit; 101-a first node; 102-a second node;
200-a first pull-down circuit; 300-ground line; 400-a second pull-down circuit;
103-a buffer; 104-an inverter; 105-a third node;
500-a first pull-down current regulation circuit; 600-a second pull-down current regulation circuit;
106-fourth node; 501-a first current transistor;
502-a first switching transistor; 503-a first current regulating circuit;
5031-a first transistor; 5032-a first control signal transistor;
201-a first mirror transistor; 202-a second switching transistor;
601-a second current transistor; 602-a third switching transistor;
603-a second current regulating circuit; 6031 — second transistor;
6032-second control signal transistor; 401-a second mirror transistor;
402-a fourth switching transistor.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In a first aspect, an embodiment of the present invention provides a clock duty ratio calibration circuit, as shown in fig. 1, including:
a transmission circuit 100 for receiving an input clock signal and transmitting an output clock signal, the transmission circuit 100 having at least one set of a first node 101 and a second node 102.
The first pull-down circuit 200 is connected between the first node 101 and the ground line 300, and discharges the first node 101.
The second pull-down circuit 400 is connected between the second node 102 and the ground line 300, and discharges the second node 102.
And the first pull-down current regulating circuit 500 is connected with the first pull-down circuit 200 and is used for changing the discharge rate of the first pull-down circuit 200 to the first node 101 by changing the pull-down current at the first node 101, so as to regulate the duty ratio of the output clock signal.
The second pull-down current adjusting circuit 600 is connected to the second pull-down circuit 400, and configured to change a discharging rate of the second pull-down circuit 400 to the second node 102 by changing a pull-down current at the second node 102, so as to adjust a duty ratio of the output clock signal.
In one embodiment, the transmission circuit 100 includes a plurality of buffers 103 connected in series, and an inverter 104 is connected between two adjacent buffers 103. The input and output of one of the inverters 104 form a first node 101 and a third node 105, respectively, and the input and output of the other inverter 104 form a second node 102 and a fourth node 106, respectively. It should be noted that the first node 101 and the second node 102 may be respectively disposed at the input ends of two adjacent inverters 104, or may be respectively disposed at the input ends of two non-adjacent inverters 104.
In one embodiment, the first pull-down current regulating circuit 500 includes:
the drain and gate of the first current transistor 501 are connected together to form a first connection point, and the first current generated by the first connection point is mirrored with the pull-down current of the first node 101. That is, changing the magnitude of the first root current will change the pull-down current of the first node 101.
A first switch transistor 502, the drain of the first switch transistor 502 is connected to the source of the first current transistor 501, the source of the first switch transistor 502 is connected to ground 300, and the gate of the first switch transistor 502 is connected to the supply voltage.
The first root current adjusting circuit 503 is connected to the first connection point, and is configured to adjust the first root current according to the first pull-down current control signal.
In one embodiment, the first current adjusting circuit 503 may include a plurality of current adjusting circuits connected in parallel, and an output terminal of each of the first current adjusting circuits 503 is connected to the first connection point. By changing the number of first root current adjusting circuits 503 according to the first pull-down current control signal, the magnitude of the first root current can be adjusted quickly. For example: the first pull-down current control signal is an 8-bit signal; the first pull-down current regulating circuit 500 may include 8 first current regulating circuits 503 connected in parallel; each bit of the first control signal is used to turn on or off a first current regulating circuit 503. It should be noted that x8 at 500 in fig. 1 means that 8 first current regulating circuits 503 are included.
In one embodiment, the first current regulating circuit 503 includes a first transistor 5031 and a first control signal transistor 5032. The source of the first transistor 5031 is connected to a power supply voltage, the gate of the first transistor 5031 receives a bias Voltage (VBIAS), the drain of the first transistor 5031 is connected to the source of the first control signal transistor 5032, the gate of the first control signal transistor 5032 receives a first pull-down current control signal, and the drain of the first control signal transistor 5032 is connected to a first connection point.
In one embodiment, the first pull-down circuit 200 includes:
a first mirror transistor 201, wherein the gate of the first mirror transistor 201 is connected to the first connection point, and the drain of the first mirror transistor 201 is connected to the first node 101.
A second switch transistor 202, wherein the gate of the second switch transistor 202 is connected to the third node 105, the drain of the second switch transistor 202 is connected to the source of the first mirror transistor 201, and the source of the second switch transistor 202 is connected to the ground line 300.
In some embodiments, the second pull-down current regulating circuit 600 includes:
the second current transistor 601, the drain and gate of the second current transistor 601 are connected together to form a second junction, and the second junction generates a second current that mirrors the pull-down current of the second node 102. That is, changing the magnitude of the second current will change the pull-down current of the second node 102.
And a second current regulating circuit 603 coupled to the second node for regulating a second current according to a second pull-down current control signal.
In one embodiment, the second current regulating circuit 603 may comprise a plurality of current regulating circuits connected in parallel, and an output terminal of each second current regulating circuit 603 is connected to the second connection point. According to the second pull-down current control signal, the conduction number of the second current adjusting circuit 603 is changed, so that the magnitude of the second current can be rapidly adjusted. For example: the second pull-down current control signal is an 8-bit signal; the second pull-down current regulation circuit 600 may include 8 second current regulation circuits 603 in parallel; each bit of the second control signal may turn on or off a second current regulating circuit 603. X8 at reference numeral 600 in fig. 1 means that 8 second current regulating circuits 603 are included.
In one embodiment, the first pull-down current control signal changes the discharge rate of the first node 101 by controlling to change the magnitude of the first root current, so as to adjust the slope of the rising edge of the output clock signal; the second pull-down current control signal changes the magnitude of the second current by controlling, and further changes the discharge rate to the second node 102, thereby adjusting the slope of the falling edge of the output clock signal.
In one embodiment, the second current regulating circuit 603 includes a second transistor 6031 and a second control signal transistor 6032. A source of the second transistor 6031 is connected to a power supply voltage, a gate of the second transistor 6031 receives a bias Voltage (VBIAS), a drain of the second transistor 6031 is connected to a source of the second control signal transistor 6032, a gate of the second control signal transistor 6032 receives a first pull-down current control signal, and a drain of the second control signal transistor 6032 is connected to the second connection point.
In some embodiments, the second pull-down circuit 400 includes:
and a second mirror image transistor 401, wherein a gate of the second mirror image transistor 401 is connected to the second connection point, and a drain of the second mirror image transistor 401 is connected to the second node 102.
A fourth switching transistor 402, a gate of the fourth switching transistor 402 is connected to the fourth node 106, a drain of the fourth switching transistor 402 is connected to a source of the second mirror transistor 401, and a source of the fourth switching transistor 402 is connected to the ground line 300.
In one embodiment, to improve the capability of adjusting the duty ratio of the clock signal, the transmission circuit 100 may have a plurality of sets of first nodes 101 and second nodes 102, each first node 101 being connected to one first pull-down circuit 200, and each second node 102 being connected to one second pull-down circuit 400.
In an application example, as shown in fig. 2, the transmission circuit 100 of the clock duty ratio calibration circuit 10 according to the embodiment of the present invention is further connected to the duty ratio detector 20, the duty ratio detector 20 is connected to the counter 30, and the counter 30 is connected to the clock duty ratio calibration circuit 10. The duty ratio detector 20 is configured to detect a duty ratio of an output clock signal of the transmission circuit 100, and output a first pull-down current control signal and a second pull-down current control signal through the counter 30 according to the duty ratio of the output clock signal.
In a second aspect, an embodiment of the present invention provides a calibration method for a clock duty calibration circuit, where the method is applied to the clock duty calibration circuit in any one of the above embodiments, as shown in fig. 3, and includes:
s100: the first pull-down current regulating circuit changes the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal.
S200: the second pull-down current regulating circuit changes the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal.
In one embodiment, an input terminal of an inverter of the transmission circuit forms a first node, an output terminal of the inverter forms a third node, and the calibration method further includes:
s101: when the first pull-down current regulating circuit is connected with the first node and the clock signal at the third node is at a high level, the first pull-down circuit discharges the first node.
In some embodiments, an input of another inverter of the transmission circuit forms the second node and an output of the other inverter forms the fourth node, the calibration method further comprising:
s201: when the second pull-down current regulating circuit is connected to the second node and the clock signal at the fourth node is at a high level, the second pull-down circuit is connected to discharge the second node.
In one embodiment, the rate of falling edges is adjusted when the high time of the input clock signal is less than the low time. The rate of rising edges is adjusted when the low time of the input clock signal is less than the high time.
For example, as shown in fig. 4, when the high time (T1) of the input clock signal is less than the low time (T2), and the clock signals of the first node 101, the third node 105, the second node 102 and the fourth node 106 are as shown in fig. 4, the adjustment process is:
the method comprises the following steps: at time T0, the third node 105 is at a high level, and there is a pull-down current at the first node 101, and when the pull-down current is increased, the time of T1 is shortened, resulting in a smaller duty cycle, and the first pull-down current control signal is adjusted to decrease the pull-down current at the first node 101, thereby increasing the time of T1.
Step two: at time T1, the fourth node 106 is at a high level, and there is a pull-down current on the second node 102, and when the second node 102 rises, the rise is very slow due to the presence of the pull-down current, the time of T1 becomes longer by Δ T, the duty cycle changes toward 50%, and the second pull-down current control signal continues to adjust, so that the pull-down current on the second node 102 continues to increase, and the time of T1 continues to increase.
By cycling the first step and the second step multiple times, the time of T1 becomes longer, and finally T1 is made equal to the time of T2, and the duty ratio of the output clock signal is adjusted to 50%.
When the high level time (T1) of the input clock signal is greater than the low level time (T2), the above example is similar.
The working principle of the embodiment of the present invention is described below with reference to fig. 5. During the duty cycle adjustment of the clock signal, the first mirror transistor 201 and the second mirror transistor 401 are always in a conducting state under the control of the first current and the second current, respectively, and the conduction and the turn-off of the first pull-down circuit 200 and the second pull-down circuit 400 are affected by the second switching transistor 202 and the fourth switching transistor 402, respectively.
In the region a, the first pull-down circuit 200 is turned on to discharge the first node 101, and if the first pull-down current increases, the first pull-down circuit 200 discharges the first node 101 more quickly and the rising slope at the first node 101 becomes smaller. In the region B, the third node 105 is a low level signal, and the second switching transistor 202 is turned off, and the first pull-down circuit 200 is turned off, at this time, the first pull-down current is changed, and the rising slope is not changed.
In the region C, the fourth node 106 is a low level signal, which turns off the fourth switching transistor 402, and further turns off the second pull-down circuit 400, and at this time, the second pull-down current is changed, and the falling slope is not changed. In the region D, the fourth node 106 is a high level signal, the fourth switching transistor 402 is turned on, and the second pull-down circuit 400 is turned on, so that the second pull-down circuit 400 discharges the second node 102, and if the second pull-down current increases, the second pull-down circuit 400 discharges the second node 102 faster, so that the falling slope at the second node 102 becomes larger.
A third aspect of the present invention provides a semiconductor memory. The semiconductor memory includes the clock duty calibration circuit as in the above embodiments.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different features of the invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Claims (11)
1. A clock duty cycle calibration circuit, comprising:
a transmission circuit for receiving an input clock signal and transmitting an output clock signal, the transmission circuit having at least one set of a first node and a second node;
a first pull-down circuit connected between the first node and a ground line for discharging the first node;
a second pull-down circuit connected between the second node and the ground line for discharging the second node;
the first pull-down current regulating circuit is connected with the first pull-down circuit and used for changing the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal;
and the second pull-down current regulating circuit is connected with the second pull-down circuit and used for changing the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal.
2. The clock duty cycle calibration circuit of claim 1, wherein the transmission circuit comprises a plurality of buffers connected in series, an inverter being connected between two adjacent buffers; wherein the input and output of one of the inverters form the first and third nodes, respectively, and the input and output of the other inverter form the second and fourth nodes, respectively.
3. The clock duty cycle calibration circuit of claim 2, wherein the first pull-down current regulation circuit comprises:
a first current transistor, wherein the drain and the gate of the first current transistor are connected together to form a first connection point, and a first current generated by the first connection point is a mirror current with a pull-down current of the first node;
a first switch transistor, wherein the drain of the first switch transistor is connected with the source of the first current transistor, the source of the first switch transistor is connected with the ground wire, and the gate of the first switch transistor is connected with a power supply voltage;
and the first root current regulating circuit is connected with the first connecting point and is used for regulating the first root current according to a first pull-down current control signal.
4. The clock duty cycle calibration circuit of claim 3, wherein the first pull-down circuit comprises:
a first mirror image transistor, wherein the grid electrode of the first mirror image transistor is connected with the first connecting point, and the drain electrode of the first mirror image transistor is connected with the first node;
and the grid electrode of the second switch transistor is connected with the third node, the drain electrode of the second switch transistor is connected with the source electrode of the first mirror image transistor, and the source electrode of the second switch transistor is connected with the ground wire.
5. The clock duty cycle calibration circuit of claim 1, wherein the second pull-down current regulation circuit comprises:
a second current transistor, wherein the drain and the gate of the second current transistor are connected together to form a second connection point, and a second current generated by the second connection point and a pull-down current of the second node form a mirror current;
a third switching transistor, wherein a drain of the third switching transistor is connected to a source of the second current transistor, a source of the third switching transistor is connected to the ground, and a gate of the third switching transistor is connected to a power supply voltage;
and the second current regulating circuit is connected to the second connection point and used for regulating the second current according to a second pull-down current control signal.
6. The clock duty cycle calibration circuit of claim 5, wherein the second pull-down circuit comprises:
a second mirror transistor, a gate of the second mirror transistor being connected to the second connection point, and a drain of the second mirror transistor being connected to the second node;
and the grid electrode of the fourth switching transistor is connected with the fourth node, the drain electrode of the fourth switching transistor is connected with the source electrode of the second mirror image transistor, and the source electrode of the fourth switching transistor is connected with the ground wire.
7. The clock duty cycle calibration circuit of claim 1, wherein the transmission circuit has a plurality of sets of the first nodes and the second nodes, each of the first nodes being connected to one of the first pull-down circuits, each of the second nodes being connected to one of the second pull-down circuits.
8. A calibration method of a clock duty calibration circuit, based on the clock duty calibration circuit of claim 1, comprising:
the first pull-down current regulating circuit changes the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal;
the second pull-down current regulating circuit changes the discharge rate of the second pull-down circuit to the second node by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal.
9. The method of calibrating a clock duty cycle calibration circuit of claim 8, wherein an input of an inverter of the transmission circuit forms a first node and an output of the inverter forms a third node, the method further comprising:
when the first pull-down current regulating circuit is communicated with the first node and the clock signal at the third node is at a high level, the first pull-down circuit discharges the first node.
10. The method of calibrating a clock duty cycle calibration circuit of claim 8, wherein an input of another inverter of the transmission circuit forms a second node and an output of the other inverter forms a fourth node, the method further comprising:
when the second pull-down current regulating circuit is connected to the second node and the clock signal at the fourth node is at a high level, the second pull-down circuit is connected to discharge the second node.
11. A semiconductor memory comprising the clock duty cycle calibration circuit of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811363215.4A CN111192609A (en) | 2018-11-15 | 2018-11-15 | Clock duty ratio calibration circuit and calibration method |
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| US20100073059A1 (en) * | 2008-09-22 | 2010-03-25 | Chae Kwan-Yeob | Duty control circuit and semiconductor device having the same |
| CN102983842A (en) * | 2012-11-30 | 2013-03-20 | 上海宏力半导体制造有限公司 | Duty ratio adjusting circuit |
| US20150155855A1 (en) * | 2013-12-02 | 2015-06-04 | Micron Technology, Inc. | Apparatuses and methods for duty cycle adjustments |
| CN105493403A (en) * | 2013-07-30 | 2016-04-13 | 高通股份有限公司 | Clock doubler including duty cycle correction |
| US20180006636A1 (en) * | 2013-07-08 | 2018-01-04 | Micron Technology, Inc. | Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals |
| CN108134602A (en) * | 2017-12-21 | 2018-06-08 | 睿力集成电路有限公司 | Duty-ratio calibrating circuit and semiconductor memory |
| CN209001911U (en) * | 2018-11-15 | 2019-06-18 | 长鑫存储技术有限公司 | Clock duty cycle calibration circuit and semiconductor memory |
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- 2018-11-15 CN CN201811363215.4A patent/CN111192609A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100073059A1 (en) * | 2008-09-22 | 2010-03-25 | Chae Kwan-Yeob | Duty control circuit and semiconductor device having the same |
| CN102983842A (en) * | 2012-11-30 | 2013-03-20 | 上海宏力半导体制造有限公司 | Duty ratio adjusting circuit |
| US20180006636A1 (en) * | 2013-07-08 | 2018-01-04 | Micron Technology, Inc. | Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals |
| CN105493403A (en) * | 2013-07-30 | 2016-04-13 | 高通股份有限公司 | Clock doubler including duty cycle correction |
| US20150155855A1 (en) * | 2013-12-02 | 2015-06-04 | Micron Technology, Inc. | Apparatuses and methods for duty cycle adjustments |
| CN108134602A (en) * | 2017-12-21 | 2018-06-08 | 睿力集成电路有限公司 | Duty-ratio calibrating circuit and semiconductor memory |
| CN209001911U (en) * | 2018-11-15 | 2019-06-18 | 长鑫存储技术有限公司 | Clock duty cycle calibration circuit and semiconductor memory |
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