CN1960179A - Pulse generation device of variable frequencies and duty ratio - Google Patents
Pulse generation device of variable frequencies and duty ratio Download PDFInfo
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- CN1960179A CN1960179A CN 200510047611 CN200510047611A CN1960179A CN 1960179 A CN1960179 A CN 1960179A CN 200510047611 CN200510047611 CN 200510047611 CN 200510047611 A CN200510047611 A CN 200510047611A CN 1960179 A CN1960179 A CN 1960179A
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Abstract
It consists of the 1st and the 2nd data store units (DS), the 1st and the 2nd impulse realization units (IR), the low-level add unit (LA), the hi-level add unit (HA), the 1st and the 2nd output level judgment units (OLJ), the 1st and the 2nd calculation result selection units (CRS) and the hi-level preservation add unit (HPA). The system clock and the reset signal connect to the 1st and the 2nd DS and the 1st and the 2nd IR respectively. The output enable signal connects to the 1st CRS and the 1st OLJ. The frequency parameter connects to LA, HA and HPA. The multiplying power parameter connects to the 1st OLJ and HA. The occupied-empty ratio parameter connects to the 2nd OLJ. The output of the 1st IR connects to the 2nd OLJ. The output of the 2nd IR is the impulse output of this means. This impulse possesses a hi-precision, changeable frequency and changeable duty ratio.
Description
Technical field
The present invention relates to a kind of Design of Digital Circuit, specifically a kind of frequency and the variable pulse generation device of duty ratio.The present invention is used to produce frequency and the variable pulse of duty ratio, can be widely used in fields such as Electromechanical Control.
Background technology
Electromechanical Control is used widely day by day in automatic fields such as industry, office and families at present, control forms is also by power-actuated simple start and stop control is provided with machinery, develop into accurate control, the new stage that original " motor drags ", " electric drive " develop into " motion control " to its position, speed, acceleration torque etc.
The pulse generating portion of motion control is main at present by single-chip microcomputer or computer realization control.This traditional implementation method system configuration complexity, software development cycle is long and the output pulse precision is limited.
Summary of the invention
The object of the present invention is to provide a kind of system configuration simple, help system hardware and software design, high frequency and the variable pulse generation device of duty ratio of output pulse precision.The pulse that the present invention produces corresponding frequencies and duty ratio according to the configuration parameter of input, and the pulse of being exported has realized the real-time control to the output pulse along with the configuration parameter real-time change.
For achieving the above object, technical scheme of the present invention is as follows:
The pulse generation device that frequency and duty ratio are variable: form by pulse generation and duty ratio modulation two parts, wherein:
The pulse generating portion comprises first data and preserves unit, first pulse realization unit, low level adder unit, high level adder unit, the first output level judging unit, the first result of calculation selected cell;
Duty ratio modulation partly comprises second data and preserves unit, second pulse realization unit, high level maintenance adder unit, the second output level judging unit, the second result of calculation selected cell;
Wherein clock signal of system and reset signal connect first data respectively and preserve the unit, second data are preserved the unit, first pulse realizes the unit, second pulse realizes the input of unit, the output enable signal is connected respectively to the input of the first result of calculation selected cell and the first output level judging unit, frequency parameter is connected to the low level adder unit, high level adder unit and high level keep the input of adder unit, the multiplying power parameter is connected to the input of the first output level judging unit and high level adder unit, duty cycle parameters is connected to the input of the second output level judging unit, first pulse realizes that the short pulse signal of unit output is connected to the input of the second output level judging unit in the duty ratio modulation part in the pulse generating portion, and second pulse realizes that the unit sends pulse output as output.
The pulse generating portion clock signal of system input effectively, reset signal is under the high condition for high, output enable signal, according to the short pulse of the frequency parameter generated frequency real-time change of multiplying power parameter and real-time change and offer the duty ratio modulation part; Duty ratio modulation part the clock signal of system input effectively, reset signal is under the high condition, when the short pulse of pulse generating portion output arrives, frequency parameter according to duty cycle parameters and real-time change carries out duty ratio modulation to the short pulse that arrives, the final final pulse signal that meets frequency and change in duty cycle requirement that generates.
The present invention has following advantage:
1. export the pulse precision height.The present invention exports the ERROR CONTROL of pulse within 1 system clock cycle.
2. pulse output frequency and EDM Generator of Adjustable Duty Ratio.The realization scope of output pulse frequency of the present invention is 0 to 0.5 times a system clock frequency; The realization scope of duty ratio and can be adjusted output frequency in real time the pulse output smoothing is changed between 0 to 1.
3. parameter configuration is simple.The present invention disposes required parameter very strong intuitive and inner link, helps system and programming.
4. circuit structure is simple.Circuit structure of the present invention is fairly simple, and can require to set its inner register size and highway width according to reality, reaches the purpose of making rational use of resources.
Description of drawings
Fig. 1 is the structured flowchart of the variable pulse generation device of frequency of the present invention and duty ratio.
Fig. 2-1 is the structured flowchart of pulse generating portion among Fig. 1.
Fig. 2-2 is the circuit diagram of pulse generating portion among Fig. 1.
Fig. 3-1 is the structured flowchart of duty ratio modulation part among Fig. 1.
Fig. 3-2 is the circuit diagram of duty ratio modulation part among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
As shown in Figure 1, the variable pulse generation device of frequency of the present invention and duty ratio is made up of pulse generation, duty ratio modulation two parts.
Shown in Fig. 2-1,2-2, the pulse generating portion comprises first data and preserves unit R EG1, first pulse realization unit R EG2, low level adder unit ADD1, high level adder unit ADD2, the first output level judging unit, the first result of calculation selected cell; Its input port has clock signal of system SCLK (System Clock, abbreviation SCLK), reset signal RST (Reset, abbreviation RST), output enable signal OE (Output Enable, abbreviation OE), frequency parameter FP (FrequencyParameter, be called for short FP), multiplying power parameter MP (Multiple Parameter is called for short MP); Output port has short pulse signal SP (Short Pulse is called for short SP); Wherein first data are preserved unit R EG1 and are preserved inner count results, first pulse realizes that unit R EG2 realizes the high-low level output of pulse, calculating when low level adder unit ADD1 carries out the production burst low level, calculating when high level adder unit ADD2 carries out the production burst high level, the first output level judging unit should carry out which kind of calculating and the current level that should export according to internal calculation result and the judgement of multiplying power parameter, and the first result of calculation selected cell is selected the result of calculation of low level adder unit ADD1 and high level adder unit ADD2.
Wherein: the first output level judging unit comprise the first comparator C MP1 and the 3rd with the door U3, the first comparator C MP1 is input as first data and preserves unit R EG1 and multiplying power parameter MP, output signal and output enable signal OE together deliver to the 3rd with a door U3, the 3rd is connected to first pulse with door U3 output realizes unit R EG2;
Wherein: the first result of calculation selected cell comprise the first MUX MUX1, first and door U1 and second with U2, first with a door U1, second with the input signal of U2 output signal and output enable signal OE from the first output level judging unit, first is connected to the first MUX MUX1 with a door U1, second with the output signal of door U2, and the first MUX MUX1 and first data preservation unit R EG1 input links to each other.When output enable signal OE was low level, the first MUX MUX1 was output as zero; When first was high level with a door U1 output signal, the first MUX MUX1 selected the data output of low level adder unit ADD1; When second was high level with a door U2 output signal, the first MUX MUX1 selected the data output of high level adder unit ADD2.
Shown in Fig. 3-1, duty ratio modulation partly comprises second data and preserves unit R EG3, second pulse realization unit R EG4, high level maintenance adder unit ADD3, the second output level judging unit, the second result of calculation selected cell MUX2; Its input port has clock signal of system SCLK, reset signal RST, short pulse signal, frequency parameter FP, duty cycle parameters (Duty Ratio Parameter is called for short DRP); Output port has pulse output signals (Pulse Output is called for short PO); Wherein second data are preserved unit R EG3 and are preserved the internal calculation result, second pulse realizes that unit R EG4 realizes the high-low level output of pulse, calculating when high level keeps adder unit ADD3 to carry out the maintenance pulse high level, the second output level judging unit judges that according to internal calculation result and multiplying power parameter should continue to calculate still is zero clearing as a result and the current level that should export, and the second result of calculation selected cell MUX2 selects result of calculation.
Wherein: the second output level judging unit comprises that the second comparator C MP2, the 4th reaches or door U5 with door U4, or a door U5 input signal is pulse output PO and short pulse signal SP; The second comparator C MP2 is input as second data and preserves unit R EG3 and duty cycle parameters DRP signal, output signal with or the output of door U5 together deliver to the 4th with a door U4, the 4th is connected to second pulse with the output of door U4 realizes unit R EG4.
Its clock signal of system SCLK and reset signal RST connect first data respectively and preserve unit R EG1, second data are preserved unit R EG3, first pulse realizes unit R EG2, second pulse realizes the input of unit R EG4, output enable signal OE is connected respectively to the first result of calculation selected cell and the first output level judging unit, frequency parameter FP is connected to low level adder unit ADD1, high level adder unit ADD2 and high level keep adder unit ADD3, multiplying power parameter MP is connected to the first output level judging unit and high level adder unit ADD2, duty cycle parameters DRP is connected to the second output level judging unit, first pulse realizes that the short pulse signal of unit R EG2 output is connected to the second output level judging unit in the duty ratio modulation part in the pulse generating portion, and second pulse realizes that unit R EG4 sends pulse output PO as output.
The computing formula of its moderate multiplying factor, driving frequency and duty ratio is as follows:
Multiplying power=system clock frequency/multiplying power parameter;
Drive speed (PPS)=frequency parameter * multiplying power;
Duty ratio=duty cycle parameters/multiplying power parameter;
When the multiplying power parameter value was identical with system clock frequency, multiplying power was a minimum value 1, and the output pulse precision is the highest; Multiplying power reduces and increases with the multiplying power parameter, and pulse precision reduces and reduces with the multiplying power parameter; Guarantee that frequency parameter is less than 1/2nd of multiplying power parameter; The duty cycle parameters span is that (0～multiplying power parameter) duty ratio corresponding is (0～1).
Whole implementation of the present invention is as follows: the pulse generating portion is according to the short pulse of the frequency parameter generated frequency real-time change of multiplying power parameter and real-time change; The duty ratio modulation part is carried out duty ratio modulation according to the short pulse of the frequency real-time change of the frequency parameter paired pulses generating portion output of duty cycle parameters and real-time change, generates the final pulse signal that meets frequency and change in duty cycle requirement.
The implementation of pulse generating portion is as follows: effective at clock signal of system, reset signal is invalid, and under the effective condition of output enable signal, the pulse generating portion enters operating state.First data are preserved calculating, selection and the median maintenance that unit R EG1, low level adder unit ADD1, high level adder unit ADD2 and the first result of calculation selected cell MUX1 fit into line data, the first output level judgment unit judges is current should send out impulse level, and realizes that by first pulse unit R EG2 realizes.
The implementation of duty ratio modulation part is as follows: effective at clock signal of system, reset signal is invalid, and when receiving the short pulse that the pulse generating portion sends, second pulse realizes unit R EG4 output high level, second data are preserved unit R EG3, high level keeps the adder unit ADD3 and the second result of calculation selected cell MUX2 to fit into calculating, selection and the median maintenance of line data, whether the second output level judgment unit judges is current should finish high level output, and realizes that by second pulse unit R EG4 realizes.
Claims (4)
1. frequency and the variable pulse generation device of duty ratio, it is characterized in that: be made up of pulse generation and duty ratio modulation two parts, wherein: the pulse generating portion comprises first data and preserves unit, first pulse realization unit, low level adder unit, high level adder unit, the first output level judging unit, the first result of calculation selected cell; Duty ratio modulation partly comprises second data and preserves unit, second pulse realization unit, high level maintenance adder unit, the second output level judging unit, the second result of calculation selected cell; Clock signal of system (SCLK) and reset signal (RST) connect first data respectively and preserve the unit, second data are preserved the unit, first pulse realizes the unit, second pulse realizes the input of unit, output enable signal (OE) is connected respectively to the input of the first result of calculation selected cell and the first output level judging unit, frequency parameter (FP) is connected to the low level adder unit, high level adder unit and high level keep the input of adder unit, multiplying power parameter (MP) is connected to the input of the first output level judging unit and high level adder unit, duty cycle parameters (DRP) is connected to the input of the second output level judging unit, first pulse realizes that the short pulse signal (SP) of unit output is connected to the second output level judging unit in the duty ratio modulation part in the pulse generating portion, and second pulse realizes that the unit sends pulse output (PO) as output.
2. by described frequency of claim 1 and the variable pulse generation device of duty ratio, it is characterized in that: the first output level judging unit comprise first comparator (CMP1) and the 3rd with the door (U3), first comparator (CMP1) is input as first data and preserves unit (REG1) and multiplying power parameter (MP), output signal and output enable signal (OE) together deliver to the 3rd with door (U3), the 3rd is connected to first pulse with door (U3) output realizes unit (REG2).
3. by described frequency of claim 1 and the variable pulse generation device of duty ratio, it is characterized in that: the described first result of calculation selected cell comprise the first MUX MUX1, first and door U1 and second with U2, first with a door U1, second with the input signal of U2 output signal and output enable signal OE from the first output level judging unit, first is connected to first MUX (MUX1) with a door U1, second with the output signal of door U2, and first MUX (MUX1) and first data preservation unit (REG1) input links to each other.
4. by described frequency of claim 1 and the variable pulse generation device of duty ratio, it is characterized in that: the described second output level judging unit comprises that second comparator (CMP2), the 4th reaches or door (U5) with door U4, second comparator (CMP2) is input as second data and preserves unit (REG3) and duty cycle parameters (DRP), output signal with or the door (U5) output signal together deliver to the 4th with the door (U4), the 4th realizes that with door (U4) output and second pulse unit (REG4) links to each other, or (U5) input signal is that (PO) and short pulse signal (SP) are exported in pulse.
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| CNB2005100476112A CN100512003C (en) | 2005-11-02 | 2005-11-02 | Pulse generation device with variable frequencies and duty ratio |
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| CNB2005100476112A CN100512003C (en) | 2005-11-02 | 2005-11-02 | Pulse generation device with variable frequencies and duty ratio |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106559061A (en) * | 2016-11-25 | 2017-04-05 | 北京兆芯电子科技有限公司 | duty cycle corrector |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002124859A (en) * | 2000-10-16 | 2002-04-26 | Onkyo Corp | Pulse width modulation circuit |
| US6882196B2 (en) * | 2002-07-18 | 2005-04-19 | Sun Microsystems, Inc. | Duty cycle corrector |
| CN2593465Y (en) * | 2002-08-21 | 2003-12-17 | 北京有色金属研究总院 | Pulse power source pulse control circuit |
| CN1290260C (en) * | 2003-06-19 | 2006-12-13 | 台达电子工业股份有限公司 | PWM buffer circuit for regulating frequency and operating cycle of PWM signal |
| CN2836339Y (en) * | 2005-11-02 | 2006-11-08 | 中国科学院沈阳自动化研究所 | Pulse generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106559061A (en) * | 2016-11-25 | 2017-04-05 | 北京兆芯电子科技有限公司 | duty cycle corrector |
| CN106559061B (en) * | 2016-11-25 | 2021-12-14 | 北京兆芯电子科技有限公司 | Duty ratio corrector |
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