CN202068386U

CN202068386U - Harmonic suppression device based on hardware digital filter

Info

Publication number: CN202068386U
Application number: CN2011201752411U
Authority: CN
Inventors: 黄巧亮; 刘维亭; 朱志宇; 魏海峰; 曾庆军; 袁文华
Original assignee: Jiangsu University of Science and Technology
Current assignee: Jiangsu University of Science and Technology
Priority date: 2011-05-30
Filing date: 2011-05-30
Publication date: 2011-12-07
Anticipated expiration: 2021-05-30

Abstract

The utility model discloses a harmonic suppression device based on a hardware digital filter, which is formed by sequential series connection of an A/D (analogue to digital) converter, a programmable gate array, a control signal forming unit, a driving circuit and a fully-controlled inverting circuit. An output end of the A/D converter is connected with an input end of a first RAM (Random Access Memory), and an output end of the first RAM is respectively connected with an input end of a digital filter and one input end of a subtracter; an output end of the filter is connected with another input end of the subtracter and an input end of a cycle judgment unit respectively, and an output end of the cycle judgment unit is connected with one input end of a delay circuit; an output end of the subtracter is connected with a second RAM which is connected with an another input end of the delay circuit and one input end of the control signal forming unit respectively; and an output end of the delay circuit is connected with an another input end of the control signal forming unit. The harmonic suppression device based on the hardware digital filter has faster calculation speed, higher calculation precision, higher anti-electromagnetic interference ability and higher integration.

Description

A kind of harmonic suppression apparatus based on the hardware digital filtering

Technical field

The utility model relates to a kind of harmonic suppression apparatus, and is particularly a kind of based on the FPGA(field programmable gate array) harmonic suppression apparatus of hardware digital filtering.

Background technology

Along with power electronic equipment with to the continuous development of the load equipment of waveform sensitivity, the harmonic wave that various power electronic equipment produced has a strong impact on the reliability service to waveform apparatus sensitive or system, and how eliminating electric harmonic is that the major issue that faces is used in present electric power system.Passive filter at present commonly used or Active Power Filter-APF are eliminated electric harmonic, and passive filter is undesirable because of compensation effect, and compensation characteristic is influenced by electric network impedance and running status and substituted by Active Power Filter-APF gradually; The basic functional principle of Active Power Filter-APF is the harmonic current that detects earlier in the load current, is equated and opposite polarity offset current by compensation arrangement generation and harmonic wave size of current again.Active Power Filter-APF is to adopt simulation low-pass filter to obtain first-harmonic earlier at first, just can obtain harmonic wave after deducting first-harmonic, this method because of have bigger error and mains frequency and circuit element parameter are changed responsive, seldom employing at present; Method commonly used at present is that power network current is carried out A/D conversion and periodic sampling, adopt Mathematical Method to calculate the amplitude and the phase place of each harmonic by software programming then, the Mathematical Method that is adopted has: the fast Fourier analysis method, improved Fourier analysis method, methods such as the instantaneous reactive power of three-phase circuit, the common defects of these methods is that the error of calculation and real-time are poor, though wherein the error of calculation is by the analog or digital phase-locked loop, software digital filters etc. improve to some extent, but be not well solved, as: for the more frequent system of frequency change, be difficult to guarantee sample-synchronous, thereby be difficult to guarantee the precision calculated; Because the time that the software self-operating needs is longer relatively, real-time is not well solved yet in addition.

Summary of the invention

The purpose of this utility model is to overcome the defective of above-mentioned prior art and propose the harmonic suppression apparatus based on hardware filtering that a kind of computational speed is fast, precision is high.

The technical solution of the utility model is: by A/D converter, the programmable gate array control signal forms the unit, drive circuit and full control inverter circuit compose in series successively, programmable gate array is by the RAM memory, digital filter, subtracter, cycle judging unit and delay circuit are formed, A/D converter output termination the one RAM memory input, the one RAM memory output connects an input of digital filter input and subtracter respectively, filter output connects another input and the cycle judging unit input of subtracter respectively, an input of cycle judging unit output termination delay circuit, subtracter output termination the 2nd RAM memory, the 2nd RAM memory connects another input of delay circuit and the input that control signal forms the unit respectively, and the output termination control signal of delay circuit forms another input of unit.

The utility model realizes that by ultra-large field programmable gate array (FPGA) the digital filtering function replaces the digital filtering of traditional software programming, promptly realize the function of low pass filter with FPGA, make behind the low pass hardware digital filter that the digital signal after the A/D conversion realizes via FPGA, obtain fundamental signal, realize this fundamental signal by FPGA again and be kept at the algebraic operation between its source signal among the RAM of FPGA structure and obtain harmonic signal, control inverter is imported in power line and the harmonic signal equal and opposite in direction, the signal that direction is opposite, thereby the inhibition of realization harmonic wave; Have computational speed and higher computational accuracy, stronger anti-electromagnetic interference capability, higher integrated level faster.

Description of drawings

Below in conjunction with accompanying drawing the utility model is described in further detail:

Fig. 1 is a structural representation of the present utility model;

Among the figure: 1. programmable gate array; 2.A/D transducer; 3. a RAM memory; 4. digital filter; 5. subtracter; 6. cycle judging unit; 7. delay circuit; 8. the 2nd RAM memory; 9. control signal forms the unit; 10. drive circuit; 11. control inverter circuit entirely.

Embodiment

As Fig. 1, the utility model is formed unit 9, drive circuit 10 and controlled inverter circuit 11 entirely by A/D converter 2, programmable gate array 1 control signal to be formed.Wherein, A/D converter 2 is serially connected in the input of programmable gate array 1, and programmable gate array 1 output is connected in series control signal successively and forms unit 9, drive circuit 10 and control inverter circuit 11 entirely.

Programmable gate array 1 is made up of RAM memory, digital filter 4, subtracter 5, cycle judging unit 6 and delay circuit 7.The output of A/D converter 2 connects the input of a RAM memory 3, the input of the output difference linking number character filter 4 of the one RAM memory 3 and an input of subtracter 5, the output of filter 4 connects another input of subtracter 5 and the input of cycle judging unit 6 respectively, an input of the output termination delay circuit 7 of cycle judging unit 6, output termination the 2nd RAM memory 8 of subtracter 5, the 2nd RAM memory 8 connects another input of delay circuit 7 and the input that control signal forms unit 9 respectively, and the output connection control signal of delay circuit 7 forms another input of unit 9.

In the measuring-signal input a/d converter 2 with power line, A/D converter 2 is selected 16 high speed analog-to-digital conversion chips for use, and transformation result is stored in the RAM memory 3 of structure in the programmable gate array 1.Subtracter 5 deducts the first-harmonic value that obtains with the series of values of A/D converter 2 conversions behind digital filter 4 digital filterings, obtain harmonic wave then and suppress control signal, is stored in the RAM memory 8, and exports control signal formation unit 9 to.Cycle judging unit 6 is judged time of one-period according to the signal of digital filter 4, and determines to export delay time between the adjacent DA output control signal to through delay circuit 7 and form unit 9 according to fixing hits.Harmonic wave suppresses control signal controls inverter circuit 11 entirely through drive circuit 10 rear drives, injects and the harmonic signal equal and opposite in direction harmonic wave on the opposite signal suppressing power line of direction on power line.

Control signal forms the two kinds of methods that are formed with of the 9 pairs of control signals in unit, for the device that does not need harmonic analysis and communication function, control signal forms unit 9 and is composed in series by D/A converter and modulation circuit, can be after the D/A conversion with the 16 bit digital sequence harmonic signals that obtain, be converted to the PWM ripple of full control device in the more controlled inverter of analog quantity and carrier signal, generate control signal.Needs are carried out the device of harmonic analysis or communication function, control signal forms unit 9 and is made up of DSP or arm processor and peripheral circuit thereof, can from the 2nd RAM memory 8 of programmable gate array 1, read 16 bit digital sequence harmonic signals by DSP or arm processor, calculate the back and generate pwm control signal.For adopting processor to realize control signal, can also integrated as required man-machine interaction, functions such as field bus communication, serial communication, warning.

Claims

1. harmonic suppression apparatus based on the hardware digital filtering, by A/D converter (2), programmable gate array (1) control signal forms unit (9), drive circuit (10) and full control inverter circuit (11) compose in series successively, it is characterized in that: programmable gate array (1) is by the RAM memory, digital filter (4), subtracter (5), cycle judging unit (6) and delay circuit (7) are formed, A/D converter (2) output termination the one RAM memory (3) input, the one RAM memory (3) output connects an input of digital filter (4) input and subtracter (5) respectively, filter (4) output connects another input and cycle judging unit (6) input of subtracter (5) respectively, an input of cycle judging unit (6) output termination delay circuit (7), subtracter (5) output termination the 2nd RAM memory (8), the 2nd RAM memory (8) connects another input of delay circuit (7) and the input that control signal forms unit (9) respectively, and the output termination control signal of delay circuit (7) forms another input of unit (9).

2. a kind of harmonic suppression apparatus based on the hardware digital filtering according to claim 1 is characterized in that: described control signal forms unit (9) and is composed in series by D/A converter and modulation circuit.

3. a kind of harmonic suppression apparatus based on the hardware digital filtering according to claim 1 is characterized in that: described control signal forms unit (9) and is made up of DSP or arm processor and peripheral circuit thereof.