WO2007062577A1 - Boucle a phase asservie et methode d'amelioration de precision d'horloge - Google Patents

Boucle a phase asservie et methode d'amelioration de precision d'horloge Download PDF

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Publication number
WO2007062577A1
WO2007062577A1 PCT/CN2006/003059 CN2006003059W WO2007062577A1 WO 2007062577 A1 WO2007062577 A1 WO 2007062577A1 CN 2006003059 W CN2006003059 W CN 2006003059W WO 2007062577 A1 WO2007062577 A1 WO 2007062577A1
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WO
WIPO (PCT)
Prior art keywords
oscillator
locked loop
phase
digital synthesizer
control processor
Prior art date
Application number
PCT/CN2006/003059
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English (en)
Chinese (zh)
Inventor
Qing Zhang
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2007062577A1 publication Critical patent/WO2007062577A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/026—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using a memory for digitally storing correction values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Definitions

  • the invention relates to a Chinese patent filed on December 1, 2005, the Chinese Patent Office, the application number is 200510102081.7, and the invention name is "a phase-locked loop and a method for improving clock accuracy".
  • Priority of the application the entire contents of which are incorporated herein by reference.
  • the present invention relates to the field of electrical communication technologies, and in particular, to a phase locked loop and a method for improving clock accuracy.
  • the clock is generally required to provide the operating frequency.
  • Clock performance is an important aspect that affects the performance of the device.
  • the performance of the clock affects the performance of the entire network.
  • the indicators of the clock mainly include free time accuracy, drift generation during tracking, and maintaining performance.
  • the phase-locked loop technology is mainly used to keep the clock from the reference clock or the upper-level clock, so that the entire network clock works at the same frequency.
  • the clock circuit is usually implemented by a dedicated phase-locked loop device or a separate device. With the same input clock source, the accuracy of the clock depends on the design of the phase-locked loop and the performance of the oscillator.
  • the drift during tracking depends primarily on the design of the phase-locked loop. Free accuracy and hold performance depend primarily on the performance of the oscillator.
  • the secondary clock is configured with a cesium atomic clock, a three-stage clock configuration oscillator or a voltage controlled crystal oscillator.
  • the end device is characterized by a lack of concentration of the device and a large number. For this reason, reducing costs and increasing the accuracy of the clock have become new topics in the field of clocks.
  • FIG. 1 a schematic diagram of the structure of the phase locked loop is shown in FIG. 1
  • the phase-locked loop is usually composed of three basic components: a digital phase detector (PD) 110, a loop filter (LF) 120, and a voltage controlled oscillator (VCXO) 130.
  • the digital phase detector 110 is a phase comparison device for detecting a phase difference ⁇ e(t) between the phase Vi(t) of the input signal and the feedback signal phase Vo(t), and the output error signal Ud(t) is The phase difference signal ⁇ e(t); the loop filter 120 has a low-pass characteristic; the VCXO 130 is a voltage-to-frequency conversion device that acts as a controlled oscillator in the loop.
  • the digital phase detector uses the input signal as a standard, and its frequency and The phase is compared to the signal sent from the output. If any phase (frequency) difference is detected within its operating range, an error signal ud(i is generated, the AC component in the error signal is filtered by the loop filter, and the signal Uc(t) is generated to control the VCXO, forcing The VCXO changes its frequency in the direction of decreasing the phase/frequency error, causing any frequency or phase difference between the input reference signal and the VCXO output signal to gradually decrease until it is 0, at which point the loop is locked. If VCXO The output frequency is lower than the frequency of the input reference signal, and the output amplitude of the phase comparator is positive.
  • vcxo After filtering, it controls vcxo to increase its frequency until the frequency and phase of the two signals are accurately synchronized. Conversely, if the VCXO output frequency Above the input reference signal, the output of the phase comparator drops, causing the VCXO to lock at the frequency of the input reference signal.
  • the phase-locked loop is a closed-loop system.
  • the output voltage of the loop filter is a stable voltage.
  • the frequency of the VCXO output is also stable and locked.
  • phase-locked loop when the reference source is lost, the phase-locked loop will be in an unlocked state, and the output of the loop filter will change from a stable voltage to an indeterminate voltage. This voltage causes the VCXO to output a comparison. The biased frequency causes the output frequency to be unusable and the accuracy of the output clock to be low.
  • the phase-locked loop is in normal lock, if the reference source is disturbed, the output will be affected and the hold function will not be easily realized.
  • FIG. 2 a schematic diagram of the configuration of the phase locked loop is shown in FIG. 2, and generally consists of five basic components: a frequency divider 210, a phase detector 220, a filter 230, a digital synthesizer 240, and an oscillator 250.
  • the frequency divider 210 divides the input reference signal ref and the output feedback signal out, and divides the input signal and the output feedback signal to the same frequency;
  • the phase detector 220 is a phase comparison device for detecting the input.
  • Filter 230 can function as a low pass filter.
  • the digital synthesizer 240 is a digital synthesizing device which can stabilize the phase of the output clock out of the digital synthesizer and the phase opposite to the input clock ref by adjusting the frequency register of the digital synthesizer.
  • Oscillator 250 is the local oscillator portion of the system and provides an oscillator source for digital synthesizer 240.
  • the working process is as follows:
  • the frequency divider divides the input reference signal ref and the output feedback signal out, and the phase detector takes the input signal as a standard, and its frequency and phase are connected to the output terminal.
  • the sent signals are compared.
  • the phase detector sends the signal generated by the phase comparison to the filter for low-pass filtering. 4.
  • the digital synthesizer is adjusted according to the filter processing deviation value, so that the digital synthesizer output feedback signal out and the reference signal ref are relatively stable, so that the system is in a locked state.
  • the accuracy of the clock signal output by the system depends on the current frequency of the oscillator.
  • the value of the last filter output is to maintain the frequency value of the phase-locked loop output when the external reference clock signal is lost.
  • the accuracy of the output clock of the system depends on the aging characteristics of the oscillator. As the oscillator ages, the accuracy gradually Deterioration. When it is necessary to improve the freedom and retention performance of the phase-locked loop, a high-performance oscillator is required, which inevitably increases the cost of the device.
  • the accuracy of the clock depends on the design of the phase-locked loop and the performance of the oscillator.
  • the accuracy of the oscillator mainly depends on the factors such as the initial frequency deviation, the aging rate and the ambient temperature. Therefore, both the prior art 1 and the prior art 2 have the problems of the initial frequency deviation of the oscillator and the aging rate, and their existence greatly affects.
  • the performance of the phase-locked loop affects the accuracy of the clock. At the same time, when the reference source is lost, the impact on the prior art oscillator is large, the accuracy of the output clock is relatively low, and the ability to resist external interference is also poor.
  • the present invention proposes a phase locked loop and a method for improving the accuracy of the clock to improve the accuracy of the clock.
  • a phase locked loop includes a frequency divider, a phase detector, a filter, a digital synthesizer and an oscillator; a frequency divider is used to send the frequency-divided signal to the phase detector, and the phase detector processes the received signal. Outputting an error signal to the filter, the phase locked loop further comprising: a control processor, a temperature sensor and a memory;
  • the temperature sensor is configured to monitor a temperature of the oscillator, and transmit the monitored temperature value to the control processor;
  • the control processor is configured to, when normal tracking, adjust the digital synthesizer according to the filtered signal processed from the filter, and record the adjustment value; record the temperature sensor Obtaining the current temperature of the oscillator, and the correspondence between the current temperature value and the adjustment value; transferring the recorded information to the memory; the drift characteristic of the self-learning oscillator according to the adjusted value in the recorded preset time period and Aging rate
  • the memory is configured to store a temperature value of the oscillator, an adjustment value of the digital synthesizer, and a correspondence between the two;
  • the digital synthesizer is configured to output an output clock signal that is relatively stable with an input clock signal according to an adjustment signal from the control processor and an oscillation source signal from the oscillator.
  • the control processor is further configured to: when the device is powered on each time, obtain an adjustment value corresponding to the current temperature value from the memory according to the current temperature value and transmit the adjustment value to the digital synthesizer.
  • the control processor is further configured to predict and correct the adjustment value currently output to the digital synthesizer in real time according to the drift characteristics of the learned oscillator and the aging rate in the hold state.
  • the frequency divider and phase detector are implemented by an erasable programmable logic device EPLD or a field programmable gate array FPGA.
  • the filter is a digital filter composed of software
  • the temperature sensor is a temperature monitoring chip
  • the digital controller is a direct digital synthesis device DDS.
  • the oscillator is a constant temperature crystal.
  • the memory is comprised of an electrically erasable programmable read only memory (EEPROM) or flash memory (FLASH) that can be powered down.
  • EEPROM electrically erasable programmable read only memory
  • FLASH flash memory
  • a method for improving clock accuracy by using a phase locked loop as described above comprising: obtaining a current frequency deviation of an oscillator by monitoring a temperature of an oscillator and an adjusted value of a recorded digital synthesizer; in normal tracking, the control processor is based on The adjusted value of the recorded digital synthesizer is the drift characteristic and aging law of the self-learning oscillator.
  • the adjustment value of the digital synthesizer corresponding to the current temperature is selected and written into the digital synthesizer to eliminate the initial frequency deviation of the oscillator.
  • the method further includes: when the device is in the hold state, the control processor performs prediction and correction in real time according to the obtained drift characteristics and the aging rule.
  • control processor the temperature sensor and the memory are added as compared with the prior art 2.
  • the design of the phase locked loop is improved.
  • Real-time monitoring of temperature and recording of DDS adjustment values to obtain the current initial frequency deviation of the oscillator, to achieve high-precision output when free.
  • the drift characteristics and the aging rate of the oscillator in the system are obtained by a self-learning method without increasing the cost, and the stability and accuracy of the holding period are improved, and high-precision maintenance is realized.
  • FIG. 1 is a schematic structural view of a phase locked loop of the prior art
  • FIG. 2 is a schematic structural view of a phase locked loop of the prior art 2;
  • FIG. 3 is a schematic structural view of a phase locked loop according to an embodiment of the invention.
  • the phase locked loop of the present invention includes a frequency divider 310, a phase detector 320, a filter 330, a digital synthesizer 350, an oscillator 360, a control processor 340, a temperature sensor 370, and a memory.
  • the frequency divider 310 is connected to the phase detector 320, the phase detector 320, the filter 330, the control processor 340, the digital synthesizer 350, and the oscillator 360 are sequentially connected, and the control processor 340 is a central module of the phase locked loop;
  • the temperature sensor 370 is coupled to the control processor 340 and the oscillator 360 to detect the temperature of the oscillator in real time.
  • the memory 380 is coupled to the control processor 340 for storing data corresponding to the temperature of the oscillator 360 and the adjustment value of the digital synthesizer 350.
  • the temperature sensor is used to monitor the temperature of the oscillator, and the monitored temperature value is transmitted to the control processor; the temperature sensor is implemented by a common temperature monitoring chip.
  • the control processor is configured to adjust the digital synthesizer according to the filtered wave processed signal obtained from the filter during normal tracking, and record the adjustment value; record the current temperature of the oscillator obtained from the temperature sensor, and the current temperature value The correspondence with the adjustment value; the recorded information is transferred to the memory; the drift characteristic and the aging rate of the self-learning oscillator are based on the adjusted values in the recorded preset time period.
  • the control processor can also be configured to transmit, from the memory, an adjustment value corresponding to the current temperature value to the digital synthesizer according to the current temperature value each time the device is powered on.
  • the control processor can also be used to predict and correct the current output to digital synthesis in real time based on the drift characteristics of the learned oscillator and the aging rate.
  • the adjustment value of the device can be set by software in the factory, or it can be set. If it is not set, the accuracy may not be accurate enough when the first start, and then it will have no effect as long as it is adjusted to the normal state of the lock. And it has no effect on future operations.
  • the memory is used to store the temperature value of the oscillator, the adjustment value of the digital synthesizer, and the correspondence between the two; the memory is made of an electrically erasable programmable read only memory (EEPROM) or a flash memory (FLASH).
  • EEPROM electrically erasable programmable read only memory
  • FLASH flash memory
  • the digital synthesizer is configured to output an output clock signal that is relatively stable with an input clock signal according to an adjustment signal from the control processor and an oscillation source signal from the oscillator, that is, the digital synthesizer output feedback signal out and the reference signal ref are relatively Stable, so the system is locked.
  • the digital controller is a direct digital synthesis device (DDS).
  • the oscillator is a constant temperature crystal.
  • the frequency divider divides the input reference signal ref and the output feedback signal, and divides the input signal and the output feedback signal to the same frequency.
  • the two signals after frequency division are sent to the phase detector for phase discrimination processing, and the phase detector compares the phase difference between the phase of the input signal and the phase of the feedback signal after the frequency division of the output signal, and then sends the deviation value of the output to
  • the filter stores the phase value read by the phase detector into the buffer, filters out the outliers of the data in the buffer, and then takes the average of the data, so that the high frequency components can be effectively filtered out and simultaneously increased.
  • the divider and phase detector are implemented by an erasable programmable logic device (EPLD) or a field programmable gate array (FPGA).
  • the filter is a digital filter composed of software.
  • the oscillator When the device is just powered on and heated, the oscillator has a certain initial frequency deviation, and this deviation determines the accuracy of the device output at this time.
  • the temperature sensor can monitor the temperature of the oscillator in real time
  • the memory can be used to store the correspondence data of the oscillator temperature and frequency
  • the control processor records the ambient temperature of the current oscillator and the current adjustment value of the digital synthesizer. This adjustment value represents the frequency deviation of the oscillator at the corresponding temperature, so the control processor can select an appropriate value to write to the digital synthesizer based on the recorded current temperature to eliminate the initial frequency deviation of the oscillator.
  • the initial frequency offset oscillator 10-6 ⁇ 10-8 by this method, the device can output up to the free 1 (T 9 ⁇ 10- 1Q. This greatly improves the freedom of device clock indicators while enhancing The validity and practicability of the reference source decision.
  • the control processor adjusts the value of the digital synthesizer's frequency register in real time according to the data obtained by the filter to ensure the frequency of the output clock and the input clock. The frequency is consistent.
  • the adjustment value of the digital synthesizer indicates the frequency deviation of the oscillator relative to the reference source in this environment.
  • the value of the frequency register of the digital synthesizer is changed in real time to compensate for the aging of the oscillator, and the curve representation of the adjustment value of the digital synthesizer and the time relationship.
  • the aging process of the oscillator The control processor records each adjustment value in real time while adjusting the digital synthesizer. Based on these adjustment values, the drift characteristics and aging laws of the oscillator obtained by self-learning can be calculated.
  • the control processor obtains the drift characteristic and the aging rate of the oscillator according to the device in the tracking state, and performs real-time prediction and correction on the adjustment value of the digital synthesizer, thereby improving the output of the retention period. Clock stability and accuracy.
  • the above-mentioned real-time prediction correction process includes: In the tracking situation, the device can obtain the aging characteristics of the oscillator under different temperature conditions through self-learning. When the device enters the hold, the device selects an appropriate aging value from the previous aging characteristics to compensate in real time according to the current temperature condition, thereby realizing real-time prediction and correction.

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Abstract

L'invention concerne une boucle à phase asservie et une méthode consistant à améliorer la précision d'une horloge. Dans l'invention, un processeur de commande, un capteur de température et une mémoire sont ajoutés à la boucle à phase asservie. Une valeur de réglage d'un synthétiseur numérique est sélectionnée de manière appropriée par un processeur de commande, et inscrite dans le synthétiseur numérique, de sorte à éliminer la déviation de fréquence d'origine, ce qui permet d'améliorer la norme standard d'horloge libre du dispositif. Lorsque le système fonctionne normalement, la caractéristique de déviation et la vitesse de vieillissement de l'oscillateur du système sont obtenus par un calcul. Lorsque le système est en veille, celui-ci réalise une prédiction en temps réel et une correction en temps réel effectuées selon les caractéristiques de déviation et selon la vitesse de vieillissement de l'oscillateur obtenues, de sorte à améliorer la stabilité et la précision de l'horloge de sortie pendant une veille. L'invention permet d'améliorer la précision d'horloge et la synchronisation de réseau par l'amélioration de la conception de la boucle à phase asservie.
PCT/CN2006/003059 2005-12-01 2006-11-14 Boucle a phase asservie et methode d'amelioration de precision d'horloge WO2007062577A1 (fr)

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CN200510102081.7 2005-12-01
CNB2005101020817A CN100477527C (zh) 2005-12-01 2005-12-01 一种锁相环及提高时钟精度的方法

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CN102647182A (zh) * 2012-05-09 2012-08-22 西北工业大学 一种降低锁相调频电路温度漂移的模拟补偿装置
CN110309593A (zh) * 2019-07-01 2019-10-08 广东大普通信技术有限公司 一种预测恒温晶振老化率的装置及方法
CN110784216A (zh) * 2019-09-18 2020-02-11 浙江赛思电子科技有限公司 一种提升时钟服务器保持性能的方法和系统
CN111953345A (zh) * 2020-07-06 2020-11-17 南京熊猫电子股份有限公司 一种高稳定低相噪标频处理方法及系统

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CN102082658B (zh) * 2009-12-01 2013-11-06 中兴通讯股份有限公司 一种提高目的时钟频率稳定度的方法及装置
CN102281062B (zh) * 2010-06-12 2014-03-12 大唐移动通信设备有限公司 一种输出时钟信号的方法和设备
CN104901690A (zh) * 2015-06-10 2015-09-09 杭州晟元芯片技术有限公司 一种测试模式下自动校准环振的方法及装置
CN106936425B (zh) * 2015-12-29 2020-10-02 普天信息技术有限公司 时钟频率保持方法及装置
CN105892280B (zh) * 2016-04-08 2018-07-17 武汉中原电子集团有限公司 一种卫星授时装置
CN109217821B (zh) * 2017-07-03 2024-02-09 中兴通讯股份有限公司 频率器件补偿方法、装置、系统及计算机可读存储介质
CN109188889B (zh) * 2018-10-24 2021-02-12 北京无线电计量测试研究所 一种原子钟1pps时间同步方法和系统
CN110011174B (zh) * 2019-04-09 2020-07-03 南京航空航天大学 基于微波光子分频的光学锁相方法及装置
CN114866215B (zh) * 2022-04-01 2023-11-07 中国人民解放军国防科技大学 一种分布式运动平台之间的高精度自主相位同步方法
CN115395889A (zh) * 2022-09-05 2022-11-25 北京中科睿信科技有限公司 一种环路预置电压校准优化跳频时间系统和方法

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CN102647182A (zh) * 2012-05-09 2012-08-22 西北工业大学 一种降低锁相调频电路温度漂移的模拟补偿装置
CN110309593A (zh) * 2019-07-01 2019-10-08 广东大普通信技术有限公司 一种预测恒温晶振老化率的装置及方法
CN110309593B (zh) * 2019-07-01 2022-06-28 广东大普通信技术股份有限公司 一种预测恒温晶振老化率的装置及方法
CN110784216A (zh) * 2019-09-18 2020-02-11 浙江赛思电子科技有限公司 一种提升时钟服务器保持性能的方法和系统
CN110784216B (zh) * 2019-09-18 2023-09-26 浙江赛思电子科技有限公司 一种提升时钟服务器保持性能的方法和系统
CN111953345A (zh) * 2020-07-06 2020-11-17 南京熊猫电子股份有限公司 一种高稳定低相噪标频处理方法及系统

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