WO2007045171A1

WO2007045171A1 - Analog phase-locked loop and method of realizing hold function thereof

Info

Publication number: WO2007045171A1
Application number: PCT/CN2006/002755
Authority: WO
Inventors: Zhi Hong
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2005-10-21
Filing date: 2006-10-18
Publication date: 2007-04-26
Also published as: CN1859006A; CN100512011C

Abstract

An analog phase-locked loop and a method of realizing the hold function thereof are provided, belonging to technical field of communication. The analog phase-locked loop comprises: a phase detector, a loop filter and a VCO, and includes a hold circuit connected in series between the loop filter and the VCO as well. The hold circuit collects a control voltage from the output terminal of the loop filter, and processes it correspondingly to supply an input signal to the VCO. The corresponding method is: the phase detector comparing the phase of a received reference signal to that of a feedback signal to output an error signal to the loop filter; the loop filter outputting a control voltage corresponding to the said error signal; the holding circuit collecting and processing the said control voltage to supply the input signal to the VCO. In the present invention, when a reference source is lost or deteriorated, the output of the whole phase-locked loop cannot be pulled deviated, that is to say the phase-locked loop has a “hold” function, so as to improve the reliability of the output of phase-locked loop.

Description

Analog phase-locked loop and method for implementing the same

This application claims the priority of the Chinese patent application filed on October 21, 2005, the Chinese Patent Office, the application number is 200510100700.9, and the invention is entitled "A system and method for maintaining the function of the analog phase-locked loop". Pass: ^ Citation is incorporated in this application. '

Technical field

The present invention relates to the field of communications technologies, and in particular, to an analog phase locked loop and a method for implementing the same.

Background technique

Phase-locked loops are widely used in communication electronic circuits. At present, the phase-locked loop is divided into two types: analog phase-locked loop and digital phase-locked loop. The analog phase-locked loop changes the capacitance of the oscillation loop by adjusting the voltage to achieve the purpose of changing the frequency. The digital phase-locked loop is adjusted by frequency division. The ratio (increase, minus pulse) is used to adjust the frequency.

At present, the more common analog phase-locked loop is shown in Figure 1. It is composed of three basic components of the phase detector 110, the loop filter 120 and the voltage controlled oscillator 130, wherein the output end of the voltage controlled oscillator 130 is connected with the feedback end of the phase detector 110 to form a Feedback loop. The following describes the role of the basic components in the loop.

The phase detector is a phase comparison device for comparing the phase difference 0e(t) between the reference signal Vi(t) and the feedback signal phase Vo(t), and outputting the error signal Ud(t). Among them, the output error signal Ud(t) is a function of the phase difference signal 0e(t).

The loop filter has a low-pass characteristic that acts as a low-pass filter and, more importantly, it plays a decisive role in loop parameter adjustment. The loop filter is a linear circuit that can be represented by a transfer operator F ( P ) in time domain analysis. Commonly used loop filters are RC integral filter, passive proportional integral filter and active proportional integral filter.

The voltage controlled oscillator is a voltage/frequency converter that acts as a controlled oscillator in the loop. Its oscillation frequency varies linearly with the input control voltage Uc( ), so the voltage-controlled oscillator is in the phase-locked loop. An integral link.

The phase-locked loop is a closed-loop phase control unit. The phase detector compares the phase difference between the reference signal and the voltage-controlled oscillator output signal (feedback signal) to generate an error control voltage to adjust The frequency of the voltage controlled oscillator is at the same frequency as the reference signal. When the loop starts to work, usually the frequency of the reference signal is different from the oscillation frequency when the voltage controlled oscillator is not controlled. Due to the inherent frequency difference between the two signals, the phase difference between them must constantly change, so that the frequency of the voltage controlled oscillator also changes within the corresponding range. If the frequency of the voltage controlled oscillator is equal to the frequency of the reference signal, the voltage controlled oscillator is stabilized at this frequency. After reaching the stability, the frequency between the reference signal and the output signal of the voltage controlled oscillator is the same, and the phase difference no longer changes with time. At this time, the error control voltage is a fixed value, and the loop enters a so-called "locked" state.

In order to facilitate the phase comparison of the reference signal and the feedback signal by the phase detector, it is necessary to connect a frequency divider in series in the feedback loop. The function of the frequency divider is to divide the frequency of the feedback signal to a frequency consistent with the reference signal. Only the frequency of the feedback signal and the reference signal are the same to participate in phase discrimination. Generally, the frequency of the reference signal participating in phase discrimination is lower than the input frequency of the voltage controlled oscillator. Of course, if the frequency of the reference signal participating in the phase discrimination is the same as the frequency of the feedback signal, there is no need to divide the frequency, and it is directly used as feedback.

In the prior art, the use of a separate device to form an analog phase-locked loop has the advantages of flexible circuit, high performance index, low circuit cost, and can realize some existing integrated phase-locked loops, compared to a single-chip integrated phase-locked loop. The functions realized, for example: The loop bandwidth and damping coefficient can be flexibly adjusted. Since the phase-locked loop is a separate component, the loop bandwidth and damping coefficient are adjusted by adjusting the values of the peripheral components, so that the phase-locked loop has Different filtering characteristics, so the analog phase-locked loop formed by the discrete device is widely used in the current circuit design. The specific system block diagram is shown in Figure 2. The working principle is as follows:

The phase detector 210 detects a phase difference between the phase of the reference signal and the phase of the feedback signal, and the two output levels of the output are respectively input to the positive and negative poles of the active low-pass proportional-integral filter 220, and the active low-pass proportional integral The filter 220 outputs a control voltage to adjust the output of the voltage controlled oscillator 230. The output is divided by the frequency divider of the frequency divider 240 as a feedback signal to enter the phase detector 210 to participate in the identification machine.

In this scheme, the phase detector and the frequency divider can be implemented in a logic device, such as Field Programmable Gate Array (FPGA), Complex Programmable Logical Device (CPLD) or erasable. Programming logic device (EPLD: Erasable Programmable Logic Device), the active 4氐-pass proportional-integral filter can be realized by an operational amplifier and peripheral circuits.

In the case of normal locking, the phase-locked loop is a closed-loop system. The output voltage of the active low-pass filter is a stable voltage. At this time, the output of the voltage-controlled oscillator is also stable and locked. However, when the input reference signal is lost or degraded, the phase-locked loop will be in an unlocked state, and the output of the active low-pass filter will change from a stable voltage to an indeterminate voltage, which makes the voltage-controlled oscillator Outputs a very biased frequency that causes the output frequency to be unusable. Summary of the invention

The technical problem to be solved by the present invention is to provide an analog phase-locked loop and a method for implementing the same. When the phase-locked loop input reference source is lost or deteriorated, the pin-phase loop enters a "hold" mode, that is, the voltage-controlled oscillation The device continues to output the frequency memorized in the normal tracking state, so that when the reference source is lost or degraded, the frequency of the phase-locked loop output does not jump, which improves the reliability of the phase-locked loop output.

The present invention is achieved by the following technical solutions:

An analog phase-locked loop includes: a phase detector, a loop filter, and a voltage controlled oscillator connected in series, and an output of the voltage controlled oscillator is coupled to a feedback end of the phase detector through a feedback loop; The phase locked loop also includes:

a holding circuit connected in series between the loop filter and the voltage controlled oscillator, collecting a control voltage from the output end of the loop filter for determining the output of the control loop filter when the phase locked loop is in a locked state The end is connected to the input end of the voltage controlled oscillator; when the phase locked loop is determined to be in the unlocked state, the path between the output of the loop filter and the input end of the voltage controlled oscillator is turned off, The collected control voltage is processed and input to the input of the voltage controlled oscillator.

The analog phase locked loop further includes a frequency divider connected in series to a feedback loop between the output of the voltage controlled oscillator and the feedback terminal of the phase detector.

The holding circuit includes an A/D converter, a D/A converter, a control unit, and a switching unit;

The control unit is configured to collect a control voltage from an output end of the loop filter through an A/D converter, and determine that the phase locked loop is in a locked state, and transmit the connection to the control end of the switch unit through the second output end thereof a signal of an output of the loop filter and a voltage controlled oscillator; determining the phase lock When the ring is in the unlocked state, the control terminal of the switching unit is transmitted through its second output to block the signal of the output of the loop filter and the voltage controlled oscillator, and through its first output and D/A conversion Transmitting a processed control voltage signal to a second input of the switching unit;

The switching unit is configured to control, according to a control signal received from the control end, the control loop filter to be connected to the voltage controlled oscillator via its first input terminal; or to control the collected control voltage signal via its own The second input is coupled to the voltage controlled oscillator.

The control unit is further configured to save the collected control voltage when the pin phase ring is in a locked state, and calculate an average value of the saved control voltage;

The 控制 collected control voltage signal transmitted to the second input end of the switch unit is 平均值 the calculated average value of the collected control voltages.

The control unit includes a processor and a memory, and the memory is respectively connected to the processor, the A/D converter and the D/A converter, and the processor is connected to the control end of the switch unit.

The analog phase-locked loop according to claim 3, wherein the memory is a general-purpose memory, and includes: a FLASH and a hard disk.

The loop filter includes: an RC integration filter, a passive proportional integral filter, or an active proportional integral filter.

The voltage controlled oscillator includes: a crystal voltage controlled oscillator, an LC voltage controlled oscillator or a voltage controlled multiple resonant oscillator.

The switch unit includes a soft switch or a hard switch.

A method for simulating a phase-locked loop to implement a hold function includes the following steps:

The phase detector compares the phases of the received reference signal and the feedback signal, and outputs an error signal to the loop filter, and the loop filter outputs a corresponding control voltage according to the error signal; maintaining the output of the loop filter output of the circuit Controlling the voltage, determining whether the pin phase loop is currently in a stable locked state, and if so, controlling the output voltage of the control loop filter as an input signal of the voltage controlled oscillator; otherwise, the holding circuit will control the collected The voltage is processed as an input signal to the voltage controlled oscillator. ... - The process of determining whether the phase locked loop is currently in a stable locked state includes:

The hold circuit collects the control voltage from the output of the loop filter and saves it, calculates the average control voltage value for one cycle, and compares the average control voltage value with at least one newly acquired control Voltage values are compared:

If the generated difference is not within the preset error range for n times, and n is equal to the preset value, it is determined that the pin phase loop is currently in an unstable locking state;

If the generated difference is not within the preset error range for n consecutive times, and n is less than the preset value, or if the generated difference is within the preset error range, it is determined that the pin phase loop is currently in A stable lock state.

If the generated difference is not within the preset error range for n times, and n is equal to the preset value, the method further includes: the holding circuit discarding the newly collected control voltage value;

The average control voltage value of the control voltage collected by the holding circuit as the input signal of the voltage controlled oscillator is the average value of the control voltage that has been calculated before discarding.

If the generated difference is not within the preset error range for n times, and n is less than the preset value, the method further includes: the holding circuit discarding the newly collected control voltage value; and, re-counting n.

If the generated difference is within the preset error range, the holding circuit replaces the saved control voltage value with the newly stored control voltage value in real time, and calculates a new average value of the control voltage in real time. Old average, and save.

Due to the above technical solution, when the reference source is lost or degraded, the output of the entire phase-locked loop is not pulled, that is, the phase-locked loop has a hold function, which avoids the phase-locked loop when the reference source is lost or deteriorated. The frequency of the output is hopped; furthermore, the invention can also adjust the length of a cycle and the number of acquisitions of the control voltage and the size of the set error range in the cycle, and improve the application of the phase-locked loop in specific situations. Degree of freedom; depending on the actual application, it can be selected to switch to the "hold" state when the reference source is degraded; the reliability of the phase-locked loop output is improved.

DRAWINGS

1 is a basic configuration diagram of an analog phase locked loop in the prior art.

2 is a system block diagram of an analog phase locked loop in the prior art. FIG. 3 is a system block diagram of an analog phase locked loop in accordance with an embodiment of the present invention.

4 is a flow chart of a method for implementing a hold function of an analog phase locked loop in accordance with an embodiment of the invention. detailed description

As shown in Fig. 3, the system block diagram of the present invention is based on the prior art, and a holding circuit, i.e., a dotted frame portion in the drawing, is added.

The system includes: a phase detector 310, a loop filter 320, a hold circuit 330, and a voltage controlled oscillator 350; in order to make the reference signal and the frequency of the feedback signal coincide, it can also be in the voltage controlled oscillator 340 and the phase detector 310. A frequency divider 350 is coupled to the feedback loop.

The phase detector 310 receives the reference signal and the feedback signal output from the output of the voltage controlled oscillator 340, compares the phases of the two signals, and outputs the error signal to the loop filter 320.

The loop filter 320 is coupled to the output of the phase detector 310, and the loop filter 320 outputs a corresponding control voltage based on the received error signal.

The hold circuit 330 is connected in series between the loop filter 320 and the voltage controlled oscillator 340, which collects the control voltage and processes it accordingly to give an input signal to the voltage controlled oscillator 340.

The voltage controlled oscillator 340 outputs a signal of a certain frequency as an output of the entire system according to the input signal received at its input terminal.

The above holding circuit includes an A/D converter 331, a D/A converter 332, a processor 334, a memory 333, and a switching unit 335; an output of the loop filter 320 is connected to the memory 333 through an A/D converter 331; An output end of the loop filter 320 is connected to an input end of the voltage controlled oscillator 340 through a first input end and an output end of the switch unit 335; the processor 334 and the memory 333 are connected to each other; and the memory is sequentially subjected to D/A conversion. The second input end and the output end of the switch unit 335 are connected to the input end of the voltage controlled oscillator 340; the processor 334 is connected to the control end of the switch unit 335. The above processor 334 and memory 333 may be collectively referred to as a control unit 336. The memory is a general-purpose memory, including: flash memory (FLASH), hard disk.

If the entire system is in the "locked" state, the control voltage output by the loop filter is directly used as the input signal of the voltage controlled oscillator through the switching unit; if the reference signal is lost or degraded, the control unit outputs a corresponding control signal to The switching unit, the switching unit immediately disconnects the path between the loop filter and the voltage controlled oscillator, and simultaneously turns on the path between the D/A converter and the voltage controlled oscillator, at which time the control voltage of the voltage controlled oscillator is controlled by Keep the circuit to provide. Specifically, the control unit is configured to collect the control voltage from the output end of the loop filter through the A/D converter, and determine that the phase-end loop is in the locked state, and transmit the connection to the control end of the switch unit through the second output end thereof. The output of the loop filter and the signal of the voltage controlled oscillator; when the phase locked loop is determined to be in the unlocked state, the output end of the blocking loop filter is transmitted to the control end of the switching unit through the second output end thereof And a signal of the voltage controlled oscillator, and transmitting the processed control voltage signal to the second input end of the switch unit through the first output end thereof and the D/A converter; the specific processing includes: after rejecting the bad value, the remaining The number is averaged.

a switching unit, configured to, according to a control signal received from the control end, control the loop filter to be connected to the voltage controlled oscillator via its first input terminal; or to control the acquired control voltage signal via its second The input is connected to the voltage controlled oscillator.

The above loop filter is a linear circuit, and an RC integration filter, a passive ratio integration filter or an active proportional integration filter can be used to achieve the object of the present invention.

The above voltage controlled oscillator is a crystal voltage controlled oscillator, an LC voltage controlled oscillator or a voltage controlled multiple resonant oscillator. Among them, the crystal oscillator has the highest frequency stability, but its frequency control range is small, the linearity of control characteristics is the worst, and the control sensitivity is the lowest; the voltage-controlled multivibrator has the worst frequency stability and can only generate square waves. However, it has the largest controllable range, the best linearity, and the highest control sensitivity. The performance of the LC voltage controlled oscillator is somewhere in between. These voltage controlled oscillators can be substituted for each other to achieve the object of the present invention.

The above switching unit is a soft switch or a hard switch, and a hard switch such as a relay switch. To achieve the function of maintaining the phase-locked loop, it is first necessary to determine that the output of the phase-locked loop is in the state of the spike. Generally, there are two options: One is to confirm whether the phase-locked loop is stable by measuring the input reference source. The other is to confirm the stability by measuring the output of the phase-locked loop; the former solution can pass a special clock test instrument (such as oscilloscope, frequency meter, time interval analyzer) or test circuit (integrated in another In one module, the input reference source is measured for a part of the communication device, for example, the frequency of the reference source is tested within a normal range, and the phase-locked loop is considered to be in a stable state; the latter scheme is also the same It can be measured by a special clock test instrument or test circuit. For example, if the measured phase-locked loop output frequency deviation is within a certain range, the phase-locked loop is also considered to be in a stable state. When the phase locked loop is in the normal output state, as shown in FIG. 4, the specific implementation method of the present invention is as follows:

Step 401: The phase detector compares the phases of the received reference signal and the feedback signal, and outputs an error signal to the loop filter; the loop filter outputs a control voltage according to the error signal;

Steps 402 to 403, in one cycle, the holding circuit acquires M control voltages from the output of the loop filter through the A/D converter, and stores the M control voltage values in the memory; The operation calculates the average control voltage value in one cycle, stores it in the memory, and compares the average control voltage value with at least one newly acquired control voltage value;

If the generated difference is not within the preset error range for n consecutive times, the preset error range has been saved in the memory, and n is equal to the preset value as an integer), steps 404 to 405 are performed: It is considered that the phase locked loop is in an unstable locking state, that is, the reference signal is lost or deteriorated, and the processor in the holding circuit outputs the path between the open loop filter and the voltage controlled oscillator to the switching unit and turns on the D/A. a control signal of the path between the converter and the voltage controlled oscillator. At this time, the memory does not store the n new control voltage values, that is, discards the newly collected n control voltage values, and the average stored in the memory The control voltage value is converted by the D/A converter and input to the input end of the voltage controlled oscillator through the switch unit. At this time, the control voltage value applied to the input end of the voltage controlled oscillator is: The phase locked loop is in a stable locked state. That is, the average control voltage value stored in the memory is subjected to the D/A converted analog value before the reference signal is lost or deteriorated.

If the generated difference is not within the preset error range for n consecutive times, but n is less than the preset value, then step 406 407 is performed: At this time, the phase locked loop may be subject to clock interference, but does not cause the phase locked loop to lose lock. , the system is still considered to be in a stable output state; then the processor in the holding circuit outputs a control signal for maintaining the path between the loop filter and the voltage controlled oscillator to the switching unit; and re-counting n, and does not The corresponding collected control voltage values are stored in the memory, that is, the newly collected n control voltage values are discarded.

If the generated difference is within the preset error range, then steps 408 to 409 are performed: that is, the system itself is in a locked state of the stable output; the processor in the holding circuit supplies the switching unit output to maintain the loop filter and the voltage control Control signal for the path between the oscillators; at this point, the newly acquired control The voltage value replaces the control voltage value stored in the memory for the longest time in real time, and stores the reasonable data in a first-in, first-out manner. At the same time, the processor calculates the new average value of the control voltage in real time, replaces the old average value, and stores it in the memory. In, real-time updates.

More specific implementation process is as follows:

When the phase-locked loop is locked, the frequency of the output signal is stable, and the control voltage is also a stable voltage. If Y seconds is used as a cycle, and the voltage is collected every A seconds, then there is M= in one cycle. The Y/A voltage values are stored in the buffer. The M voltage values are very similar, but they are not all the same. Here, the average value X of the M voltages is called the "good value". ", every new A seconds, a new value is collected. This value will be compared with X. If there is little difference, the specific difference in the application is normal according to the actual situation, that is, the error range of the difference is set. Then think that this value is still a good value, the phase-locked loop is still normal, then put this value into the end of the buffer, move the first value of the buffer out, and the X value is also updated; if the difference is large, according to If the actual application determines this range, the value is considered to be a bad value. At this time, the value is not put into the buffer, and the X value is not updated. If the situation is restored after less than n times, it is considered not Clock Insufficient to cause loss of lock of the phase-locked loop; if this situation lasts for n times, it can be judged that it is not the interference of the clock, but the clock is interrupted or degraded, and the phase-locked loop is about to lose its lock. The calculated X is used as a control voltage to control the voltage controlled oscillator.

Since the phase-locked loop circuit is mostly used in communication equipment, the communication equipment is integrated by multiple functional circuit modules, and there is interconnection and interconnection between the circuit modules. There may be some uncertain interference inside and outside the communication equipment. Sources, improper handling of these sources of interference can cause the clock to be disturbed, such as unstable power systems, strong sources of electromagnetic radiation nearby, lightning strikes, etc., which can affect the input reference signal.

The error range can be adjusted, or wide or narrow; the length of the acquisition cycle can also be adjusted, or long or short; the number of acquisitions of the control voltage M in multiple acquisition periods is also adjustable, or large or Small; The preset value of the generated difference that continuously exceeds the error range is also adjustable, or larger or smaller; this depends on the specific application. The requirements for the stability of the phase locked loop are not the same in different situations, so the parameters involved above are set to be adjustable, which is advantageous for the present invention to be better applied to various occasions. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are included in the scope of the present invention.

Claims

Rights request

An analog phase-locked loop, comprising: a phase detector, a loop filter and a voltage controlled oscillator connected in series, and an output end of the voltage controlled oscillator is coupled to a feedback end of the phase detector through a feedback loop; The analog phase locked loop further includes:

2. The analog phase locked loop according to claim 1, further comprising: a frequency divider, wherein the frequency divider is connected in series between the output of the voltage controlled oscillator and the feedback end of the phase detector. On the loop.

The analog phase-locked loop according to claim 1 or 2, wherein: the holding circuit comprises an A/D converter, a D/A converter, a control unit, and a switching unit;

The control unit is configured to collect a control voltage from an output end of the loop filter through an A/D converter, and determine that the phase locked loop is in a locked state, and transmit the connection to the control end of the switch unit through the second output end thereof The output of the loop filter and the signal of the voltage controlled oscillator; when the pin phase loop is determined to be in an unlocked state, the output of the blocking loop filter is transmitted to the control end of the switching unit through the second output thereof And a signal of the voltage controlled oscillator, and transmitting the processed control voltage signal to the second input end of the switch unit through the first output end thereof and the D/A converter;

4. The analog phase locked loop of claim 3, wherein:

― the control unit further saves the collected control voltage when the locked phase loop is in the locked state, and calculates the average value of the saved control voltage;

The collected control voltage signal transmitted to the second input end of the switch unit is an average of the calculated collected control voltages.

5. The system for implementing a hold function of an analog phase locked loop according to claim 3, wherein: the control unit comprises a processor and a memory, the memory and the processor, the A/D converter and the D/A, respectively. The converter is connected, and the processor is connected to the control end of the switch unit.

7. The analog phase locked loop of claim 3, wherein: the loop filter comprises: an RC integration filter, a passive proportional integration filter, or an active proportional integration filter.

8. The analog phase locked loop of claim 3, wherein: the voltage controlled oscillator comprises: a crystal voltage controlled oscillator, an LC voltage controlled oscillator, or a voltage controlled multiple resonant oscillator.

9. The analog phase locked loop of claim 3, wherein: said switching unit comprises a soft switch or a hard switch.

10. A method for implementing a hold function by an analog phase locked loop, comprising the steps of:

The phase detector compares the phases of the received reference signal and the feedback signal, and outputs an error signal to the loop filter, and the loop filter outputs a corresponding control voltage according to the error signal; maintaining the output of the loop filter output of the circuit Controlling the voltage, determining whether the phase locked loop is currently in a stable locked state, and if so, controlling the output voltage of the control loop filter as an input signal of the voltage controlled oscillator; otherwise, the holding circuit will control the collected The voltage is processed as an input signal to the voltage controlled oscillator.

The method for implementing the hold function of the analog phase-locked loop according to claim 10, wherein the determining whether the phase-locked loop is currently in a stable locked state comprises:

The hold circuit collects the control voltage from the output of the loop filter and saves it, calculates the average control voltage value for one cycle, and compares the average control voltage value with at least one newly acquired control voltage value:

If the generated difference is not within the preset error range for n times, and n is equal to the preset value, it is determined that the phase locked loop is currently in an unstable locked state;

If the generated difference is not within the preset error range for n consecutive times, and n is less than the preset value, Alternatively, if the generated difference is within a preset error range, it is determined that the lock 'phase loop is currently in a stable locked state.

12. The method for implementing a hold function of an analog phase locked loop according to claim 11, wherein if the generated difference is not within a preset error range for n consecutive times, and n is equal to the preset value, further comprising : the hold circuit discards the newly acquired control voltage value;

The method for implementing a hold function of an analog phase-locked loop according to claim 11, wherein if the generated difference is not within a preset error range for n consecutive times, and n is less than a preset value, further comprising : The hold circuit discards the newly acquired control voltage value; and, recounts n.

14. The method according to claim 11, wherein the generated difference is within a preset error range, and the newly acquired control voltage value is maintained in real time. Replace the saved control voltage value with the longest storage time, calculate the new average value of the control voltage in real time, replace the average value of 1曰, and save it.