CN100512011C - System and method for realizing holding fuction by analogue phase locking loop - Google Patents
System and method for realizing holding fuction by analogue phase locking loop Download PDFInfo
- Publication number
- CN100512011C CN100512011C CNB2005101007009A CN200510100700A CN100512011C CN 100512011 C CN100512011 C CN 100512011C CN B2005101007009 A CNB2005101007009 A CN B2005101007009A CN 200510100700 A CN200510100700 A CN 200510100700A CN 100512011 C CN100512011 C CN 100512011C
- Authority
- CN
- China
- Prior art keywords
- voltage
- controlled oscillator
- voltage controlled
- output
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
- H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
This invention discloses a system and a method for simulating phase-locking loop to realize the holding function including: a phase-discriminator, a loop filter and a voltage-controlled oscillator and also a holding circuit connected between the loop filter and the oscillator to collect control voltages from the output of the filter and process it and presets the input signals of th oscillator. The method includes: the phase-discriminator compares the phases of the received reference signal and feedback signal to output error signals to the loop filter, which outputs related control voltages based on said error signal, the holding circuit collects and processes said control voltage and presets the input signals of the oscillator.
Description
[technical field]
The present invention relates to communication technical field, relate in particular to the system and method that a kind of analog phase-locked look realizes keeping function.
[background technology]
Analog phase-locked look is to use more a kind of phase-locked loop in the communications electronics circuit.Phase-locked loop is divided into analog phase-locked look and digital phase-locked loop two classes at present, analog phase-locked look is the electric capacity that changes oscillation circuit by regulation voltage, reaching the purpose that changes frequency, digital phase-locked loop then is to come regulating frequency by the method for regulating frequency dividing ratio (increase, subtract pulse).
At present more common analog phase-locked look as shown in Figure 1.It is composed in series successively by phase discriminator, loop filter and three basic elements of character of voltage controlled oscillator, and wherein the feedback end of the output of voltage controlled oscillator and phase discriminator has been connected to form a feedback loop.Introduce the effect of the basic element of character in loop below respectively.
Phase discriminator is a phase comparison device, is used for phase difference θ e (t) between comparison reference signal Vi (t) and the feedback signal phase place Vo (t), output error signal Ud (t).Wherein, the error signal Ud of output (t) is the function of phase difference signal θ e (t).
Loop filter has low-pass characteristic, and it can play the effect of low pass filter, the more important thing is that it adjusts decisive role to loop parameter.Loop filter is a linear circuit, and an available transmission operator F (P) represents in time domain analysis.Loop filter commonly used has three kinds of RC integration filter, passive proportional-integral filter and active proportional-integral filter.
Voltage controlled oscillator is the converting means of a voltage/frequency, and conduct is by controlled oscillator in loop, and its frequency of oscillation is with input control voltage Uc (t) linear change, so voltage controlled oscillator is an integral element in phase-locked loop.
Phase-locked loop is the phase control unit of a closed loop, phase difference between phase discriminator comparison reference signal and the voltage controlled oscillator output signal (feedback signal), thereby produce the frequency that error control voltage is adjusted voltage controlled oscillator, to reach and reference signal frequency together.When loop was started working, the frequency of oscillation the when frequency of reference signal does not add control voltage with voltage controlled oscillator usually was different.Because have intrinsic difference on the frequency between two signals, the phase difference between them certainly will constantly change, and then make the frequency of voltage controlled oscillator also just within corresponding scope, change.If the frequency of voltage controlled oscillator equates that with the frequency of reference signal voltage controlled oscillator just settles out on this frequency.Reach stable after, the frequency between reference signal and the voltage controlled oscillator output signal is identical, phase difference changes no longer over time, this moment, error control voltage was a fixed value, loop just enters what is called " locking " state.
In order more to help phase discriminator reference signal is carried out bit comparison mutually with feedback signal, the frequency divider of need in feedback loop, connecting.Function of frequency divider is that the frequency with feedback signal reaches the frequency consistent with reference signal by frequency division, has only the frequency of feedback signal and reference signal identical, could participate in phase demodulation.In general all the incoming frequency than voltage controlled oscillator is low to participate in the frequency of reference signal of phase demodulation.If it is identical then need not frequency division certainly to participate in the frequency of frequency and feedback signal of reference signal of phase demodulation, directly as feeding back.
In the prior art, use discrete device to set up analog phase-locked look, with respect to single chip integrated phase-locked loop, it is flexible to have circuit, the performance index height, the advantage that circuit cost is low, and can realize the irrealizable function of some existing integrated phase locks, for example: regulation loop bandwidth and damping coefficient flexibly, because being discrete device, phase-locked loop sets up, so come regulation loop bandwidth and damping coefficient by the value of adjusting peripheral components, so just make phase-locked loop have different filtering characteristics, so the analog phase-locked look that discrete device is set up is widely used in present circuit design, its concrete system block diagram as shown in Figure 2, operation principle is as follows:
Phase difference between the phase place of phase discriminator reference signal detection and the phase place of feedback signal, two control levels of output are input to the positive pole and the negative pole of active low pass proportional-integral filter respectively, active low pass proportional-integral filter output control voltage is adjusted the output of voltage controlled oscillator, and the Fractional-N frequency of this output process frequency divider enters phase discriminator as feedback signal and participates in phase demodulation.
In this scheme, phase discriminator and frequency divider can be realized in logical device, as field programmable gate array (FPGA:Field Programmable Gate Array), CPLD (CPLD:ComplexProgrammable Logical Device) or Erasable Programmable Logic Device (EPLD:Erasable ProgrammableLogic Device), active low pass proportional-integral filter can realize by operational amplifier and peripheral circuit.
Under the situation of normal locking, phase-locked loop is a closed-loop system, and the voltage of active low-pass filter output is a stable voltage, and at this moment the frequency of the output of voltage controlled oscillator is also very stable, is in the lock state.But when the reference signal of input is lost or deterioration the time, phase-locked loop can be in out-of-lock condition, the output meeting of active low-pass filter becomes a uncertain voltage from a stable voltage, and this voltage makes extremely inclined to one side frequency of voltage controlled oscillator output, causes output frequency unavailable.
[summary of the invention]
The technical problem to be solved in the present invention provides the system and method that a kind of analog phase-locked look realizes keeping function, when phase-locked loop input reference source is lost or during deterioration, make phase-locked loop enter " maintenance " pattern, the frequency of remembering when promptly allowing voltage controlled oscillator continue the normal tracking mode of output, like this reference source lose or during deterioration, the frequency of phase-locked loop output can not produce saltus step, has improved the reliability of phase-locked loop output.
The present invention realizes by following technical scheme:
A kind of analog phase-locked look realizes keeping the system of function, comprising:
Phase discriminator, it receives reference signal and feedback signal, and compares the phase place of these two signals, output error signal;
With the loop filter that the output of phase discriminator is connected, it receives described error signal, output control corresponding voltage;
Be connected the holding circuit between loop filter and the voltage controlled oscillator, described holding circuit is from the output acquisition controlling voltage of loop filter, and carry out respective handling, the input signal of given voltage controlled oscillator, wherein, described holding circuit comprises A/D converter, D/A converter, processor, memory and switch element; The output of loop filter is connected with memory by A/D converter; The output of loop filter is connected with the input of voltage controlled oscillator by the first input end and the output of switch element; Processor and memory interconnect; Described memory is connected with the input of voltage controlled oscillator by second input and the output of D/A converter, switch element successively; Described processor is connected with the control end of switch element;
Voltage controlled oscillator, according to the input signal that receives, the signal of corresponding output certain frequency feeds back to the feedback end of phase discriminator by feedback loop;
Wherein, described A/D converter is used for the output acquisition controlling voltage from described loop filter, described processor is used for the average control magnitude of voltage in the one-period is compared with the control magnitude of voltage of at least one collection, and comparative result continuous n time not in preset range and n control described switch element when equaling preset value and disconnect path between described loop filter and the voltage controlled oscillator, connect the path between described D/A converter and the voltage controlled oscillator simultaneously, and comparative result continuous n time not in preset range and n control described switch element during less than preset value and keep path between described loop filter and the voltage controlled oscillator.
Further improvement of the present invention is: also comprise frequency divider, described frequency divider series connection is on the feedback loop between the feedback end of the output of voltage controlled oscillator and phase discriminator.
Further improvement of the present invention is: described loop filter is RC integration filter, passive proportional-integral filter or active proportional-integral filter.
Further improvement of the present invention is: described voltage controlled oscillator is crystal voltage controlled oscillator, LC voltage controlled oscillator or the voltage-controlled multi resonant oscillator that shakes.
Further improvement of the present invention is: described switch element is soft switch or hard switching.
A kind of analog phase-locked look realizes keeping the method for function, may further comprise the steps:
601, phase discriminator compares the reference signal that receives and the phase place of feedback signal, and output error signal is given loop filter, and loop filter is exported corresponding control voltage according to described error signal;
602, holding circuit collection and handle described control voltage, and then the input signal of given voltage controlled oscillator, described holding circuit comprises: A/D converter, D/A converter, memory, processor and switch element, wherein, A/D converter is from the output acquisition controlling voltage of loop filter, and a control magnitude of voltage is kept in the memory; Processor calculating draws the average control magnitude of voltage in the one-period, and this average control magnitude of voltage and control magnitude of voltage that at least one newly collects are compared; If the difference that produced continuous n time not in the error range of presetting, and when n equals preset value, then processor outputs a control signal to switch element, and path between open-loop filter and the voltage controlled oscillator is connected the path between D/A converter and the voltage controlled oscillator simultaneously; If the difference that produced continuous n time not in default error range, and n is during less than preset value, then processor is exported the control signal of path between retaining ring path filter and the voltage controlled oscillator to switch element; If all in default error range, then processor is to the control signal of path between switch element output retaining ring path filter and the voltage controlled oscillator for the difference that is produced.
Described step 602 further comprises: if the difference that produced continuous n time not in the error range of presetting, and when n equals preset value, then memory is not stored this control magnitude of voltage that newly collects, the average control magnitude of voltage of storing in the memory is input to the input of voltage controlled oscillator by switch element after the D/A converter conversion simultaneously.
Described step 602 further comprises: if the difference that produced continuous n time not in default error range, and n then do not store the control magnitude of voltage that this newly collects during less than preset value in the memory, the while counts n again.
Described step 602 further comprises: if the difference that is produced is all in default error range, the then new control magnitude of voltage of gathering replaces in the memory the longest control magnitude of voltage memory time in real time, processor real-time calculates the new mean value of control voltage and replaces old mean value simultaneously, and is kept in the memory.
Owing to adopted above technical scheme, lose or deterioration the time, the output of whole phase-locked loop can not drawn partially when reference source, promptly phase-locked loop has " maintenance " function; Time length and this cycle that can adjust one-period are interior to the times of collection of control voltage and the size of step-up error scope, have improved the degree of freedom that phase-locked loop is used under concrete occasion; Can select to switch to " maintenance " attitude according to the application of reality when what stage reference source corrupts to; Improved the reliability of phase-locked loop output.
[description of drawings]
Fig. 1 is the basic comprising figure of analog phase-locked look.
Fig. 2 is the system block diagram of analog phase-locked look in the prior art.
Fig. 3 is the system block diagram of analog phase-locked look of the present invention.
Fig. 4 is the method flow diagram that analog phase-locked look of the present invention realizes keeping function.
[embodiment]
As shown in Figure 3, system block diagram of the present invention is on the basis of prior art, has increased a holding circuit, i.e. frame of broken lines part among the figure.
This system comprises: phase discriminator, loop filter, holding circuit and voltage controlled oscillator;
Wherein, the feedback signal that phase discriminator receives reference signal and exports from the voltage controlled oscillator output, and the phase place of these two signals of comparison, output error signal is given loop filter; In order to make reference signal consistent, also need in the feedback loop between voltage controlled oscillator and the phase discriminator, seal in a frequency divider with the frequency of feedback signal;
Loop filter is connected with the output of phase discriminator, and loop filter is exported control corresponding voltage according to received error signal;
Holding circuit is connected between loop filter and the voltage controlled oscillator, and it is gathered described control voltage, and through respective handling, the input signal of given voltage controlled oscillator;
The input signal that voltage controlled oscillator receives according to its input, the signal of corresponding output certain frequency is as the output of whole system.
Described holding circuit comprises A/D converter, D/A converter, processor, memory and switch element; The output of loop filter is connected with memory by A/D converter; The output of loop filter is connected with the input of voltage controlled oscillator by the first input end and the output of switch element; Processor and memory interconnect; Described memory is connected with the input of voltage controlled oscillator by second input and the output of D/A converter, switch element successively; Described processor is connected with the control end of switch element.
If whole system is in the state of " locking ", then the control voltage of loop filter output passes through switch element directly as the input signal of voltage controlled oscillator; If reference signal is lost or deterioration, then processor can be exported a control signal corresponding and give switch element, switch element is the path between open-loop filter and the voltage controlled oscillator immediately, connect the path between D/A converter and the voltage controlled oscillator simultaneously, this moment, control voltage of voltage-controlled oscillator was provided by holding circuit.
Described loop filter is a linear circuit, can adopt RC integration filter, passive proportional-integral filter or active proportional-integral filter to realize purpose of the present invention.
Described voltage controlled oscillator is crystal voltage controlled oscillator, LC voltage controlled oscillator or the voltage-controlled multi resonant oscillator that shakes.Wherein, the crystal oscillator frequency stability is the highest, but its refrequency control range is little, and the linearity of control characteristic is the poorest, and control sensitivity is also minimum; Although voltage-controlled multivibrator frequency stability is the poorest, and can only produce square wave, its controlled range maximum, the linearity are best, and control sensitivity is the highest; The performance of LC voltage controlled oscillator falls between.These voltage controlled oscillators replace realizing purpose of the present invention mutually.
Described switch element is soft switch or hard switching, and hard switching is as relay switch etc.
Realize the maintenance function to phase-locked loop, must determine that at first the output of phase-locked loop is in stable status, in general two kinds of schemes are arranged: a kind of is can be by the measurement of input reference source being confirmed whether phase-locked loop is stable; Whether another kind is can stable by the output measurement of phase-locked loop is confirmed; Preceding a kind of scheme can (be integrated in another module by special clock test instrument (as oscilloscope, frequency meter, time interval analyzer) or test circuit, part for communication equipment) the input reference source is measured, for example the test obtain reference source frequency departure in certain normal scope, think that then phase-locked loop is in stable status; A kind of scheme in back can be measured by special clock test instrument or test circuit equally, and the phase-locked loop output frequency deviation of for example testing thinks also that then phase-locked loop is in stable status in certain normal scope.
When phase-locked loop was in normal output state, as shown in Figure 4, the concrete implementation method of the present invention was as follows:
Phase discriminator compares the reference signal that receives and the phase place of feedback signal, and output error signal is given loop filter; Loop filter is according to the corresponding output control of described error signal voltage;
In one-period, A/D converter is gathered M control voltage from the output of loop filter, and this M control magnitude of voltage is kept in the memory; Processor calculating draws the average control magnitude of voltage in the one-period, is kept in the middle of the memory, and this average control magnitude of voltage and control magnitude of voltage that at least one newly collects are compared;
If the difference that produced continuous n time not in default error range (this error range of presetting is kept in the memory), and when n equals preset value (n is an integer) (reference signal is lost or deterioration), then processor to path between switch element output open-loop filter and the voltage controlled oscillator and connect D/A converter and voltage controlled oscillator between the control signal of path, at this moment, memory is not stored this n control magnitude of voltage that newly collects, the average control magnitude of voltage of storing in the memory is after the D/A converter conversion simultaneously, be input to the input of voltage controlled oscillator by switch element, at this moment, the control magnitude of voltage that is added in the voltage controlled oscillator input is: reference signal lose or deterioration before, the analogue value of the average control magnitude of voltage of being stored in the memory after D/A conversion.
If the difference that produced continuous n time not in default error range, but n is less than preset value, at this moment, phase-locked loop may be subjected to clock and disturb, but is unlikely to cause the phase-locked loop losing lock, thinks that still system is in the stable state of exporting; Then processor is to the control signal of path between switch element output retaining ring path filter and the voltage controlled oscillator; Again n is counted simultaneously, and these corresponding with it control magnitudes of voltage that collect are not kept in the memory.
If all in default error range, promptly system itself is in the state of stable output to the difference that is produced; Then processor is to the control signal of path between switch element output retaining ring path filter and the voltage controlled oscillator; At this moment, the new control magnitude of voltage of gathering replaces in the memory the longest control magnitude of voltage memory time in real time, adopt the mode of first in first out to store these rational data, processor real-time calculates the new mean value of control voltage and replaces old mean value simultaneously, and be kept in the memory real-time update.
More specifically implementation procedure is as follows:
After phase-locked loop is in locking, output signal frequency is stable, control voltage also is stable voltage, if be one-period at this moment with Y second, it gathers the words of primary voltage second every A, then just there be M=Y/A magnitude of voltage to be stored in the buffering area in the one-period, this M magnitude of voltage is very close, but can not all be living also, the mean value X that we plant this M voltage just has a new value collected as so-called " good value " every A second, and this value can be made comparisons with X, if very nearly the same (what differ, and the border situation is fixed factually for normal root, promptly the error range of difference is set) think that then this value still is good value, phase-locked loop is still normal, and put into buffering area end with this value this moment, first value of buffering area is shifted out, and the X value is also upgraded simultaneously; If differ big (according to fixed this scope of practical application) then think that this value is a bad value, do not put into buffering area with this value this moment, and the X value is not upgraded yet, if this situation has continued just to have recovered less than n time, then think the deterioration that is not clock, be not enough to cause the losing lock of phase-locked loop; If this situation has continued n time, then can judge the interference that is not clock, but clock interruption or deterioration, phase-locked loop is about to losing lock, at this moment can be with X as control voltage control voltage controlled oscillator.
Because phase-locked loop circuit is used in the communication equipment more, communication equipment is integrated by a plurality of functional circuit module, there is the interconnection and interflow of circuit between each circuit module, might there be some uncertain interference sources the inside and outside of communication equipment, the improper clock that will make that these interference sources are handled is interfered, for example the power-supply system instability, near have stronger electromagnetic radiation source, the thunderbolt or the like, these all might make the reference signal of input be affected.
Described error range can be regulated, and is wide or narrow; The time length of collection period also can be regulated, and is long or short; Times of collection M to control voltage in each collection period also is adjustable, either large or small; The difference that is produced exceeds the preset value of the number of error range continuously also can regulate, either large or small; This will be incompatible fixed according to concrete applied field.Requirement to the stability of phase-locked loop under different occasions is not too identical, and therefore above-mentioned involved parameter is arranged to adjustablely, helps the present invention and is applied to each occasion better.
Claims (9)
1, a kind of analog phase-locked look realizes keeping the system of function, it is characterized in that, comprising:
Phase discriminator, it receives reference signal and feedback signal, and compares the phase place of these two signals, output error signal;
With the loop filter that the output of phase discriminator is connected, it receives described error signal, output control corresponding voltage;
Be connected the holding circuit between loop filter and the voltage controlled oscillator, described holding circuit is from the output acquisition controlling voltage of loop filter, and carry out respective handling, the input signal of given voltage controlled oscillator, wherein, described holding circuit comprises A/D converter, D/A converter, processor, memory and switch element; The output of loop filter is connected with memory by A/D converter; The output of loop filter is connected with the input of voltage controlled oscillator by the first input end and the output of switch element; Processor and memory interconnect; Described memory is connected with the input of voltage controlled oscillator by second input and the output of D/A converter, switch element successively; Described processor is connected with the control end of switch element;
Voltage controlled oscillator, according to the input signal that receives, the signal of corresponding output certain frequency feeds back to the feedback end of phase discriminator by feedback loop;
Wherein, described A/D converter is used for the output acquisition controlling voltage from described loop filter, described processor is used for the average control magnitude of voltage in the one-period is compared with the control magnitude of voltage of at least one collection, and comparative result continuous n time not in preset range and n control described switch element when equaling preset value and disconnect path between described loop filter and the voltage controlled oscillator, connect the path between described D/A converter and the voltage controlled oscillator simultaneously, and comparative result continuous n time not in preset range and n control described switch element during less than preset value and keep path between described loop filter and the voltage controlled oscillator.
2, analog phase-locked look according to claim 1 realizes keeping the system of function, it is characterized in that: also comprise frequency divider, described frequency divider series connection is on the feedback loop between the feedback end of the output of voltage controlled oscillator and phase discriminator.
3, analog phase-locked look according to claim 1 and 2 realizes keeping the system of function, and it is characterized in that: described loop filter is RC integration filter, passive proportional-integral filter or active proportional-integral filter.
4, analog phase-locked look according to claim 1 and 2 realizes keeping the system of function, and it is characterized in that: described voltage controlled oscillator is crystal voltage controlled oscillator, LC voltage controlled oscillator or voltage-controlled multivibrator.
5, analog phase-locked look according to claim 1 and 2 realizes keeping the system of function, and it is characterized in that: described switch element is soft switch or hard switching.
6, a kind of analog phase-locked look realizes keeping the method for function, may further comprise the steps:
601, phase discriminator compares the reference signal that receives and the phase place of feedback signal, and output error signal is given loop filter, and loop filter is exported corresponding control voltage according to described error signal;
602, holding circuit collection and handle described control voltage, and then the input signal of given voltage controlled oscillator, described holding circuit comprises: A/D converter, D/A converter, memory, processor and switch element, wherein, A/D converter is from the output acquisition controlling voltage of loop filter, and a control magnitude of voltage is kept in the memory; Processor calculating draws the average control magnitude of voltage in the one-period, and this average control magnitude of voltage and control magnitude of voltage that at least one newly collects are compared; If the difference that produced continuous n time not in the error range of presetting, and when n equals preset value, then processor outputs a control signal to switch element, and path between open-loop filter and the voltage controlled oscillator is connected the path between D/A converter and the voltage controlled oscillator simultaneously; If the difference that produced continuous n time not in default error range, and n is during less than preset value, then processor is exported the control signal of path between retaining ring path filter and the voltage controlled oscillator to switch element; If all in default error range, then processor is to the control signal of path between switch element output retaining ring path filter and the voltage controlled oscillator for the difference that is produced.
7, analog phase-locked look according to claim 6 realizes keeping the method for function, it is characterized in that, described step 602 further comprises: if the difference that produced continuous n time not in the error range of presetting, and when n equals preset value, then memory is not stored this control magnitude of voltage that newly collects, the average control magnitude of voltage of storing in the memory is input to the input of voltage controlled oscillator by switch element after the D/A converter conversion simultaneously.
8, analog phase-locked look according to claim 6 realizes keeping the method for function, it is characterized in that, described step 602 further comprises: if the difference that produced continuous n time not in the error range of presetting, and n is during less than preset value, then do not store the control magnitude of voltage that this newly collects in the memory, again n is counted simultaneously.
9, analog phase-locked look according to claim 6 realizes keeping the method for function, it is characterized in that, described step 602 further comprises: if the difference that is produced is all in default error range, the then new control magnitude of voltage of gathering replaces in the memory the longest control magnitude of voltage memory time in real time, processor real-time calculates the new mean value of control voltage and replaces old mean value simultaneously, and is kept in the memory.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101007009A CN100512011C (en) | 2005-10-21 | 2005-10-21 | System and method for realizing holding fuction by analogue phase locking loop |
| PCT/CN2006/002755 WO2007045171A1 (en) | 2005-10-21 | 2006-10-18 | Analog phase-locked loop and method of realizing hold function thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101007009A CN100512011C (en) | 2005-10-21 | 2005-10-21 | System and method for realizing holding fuction by analogue phase locking loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1859006A CN1859006A (en) | 2006-11-08 |
| CN100512011C true CN100512011C (en) | 2009-07-08 |
Family
ID=37297875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101007009A Expired - Fee Related CN100512011C (en) | 2005-10-21 | 2005-10-21 | System and method for realizing holding fuction by analogue phase locking loop |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100512011C (en) |
| WO (1) | WO2007045171A1 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101557230B (en) * | 2008-04-10 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | System and method for self calibration of phase-locked loop |
| CN101262287B (en) * | 2008-04-19 | 2012-05-23 | 桂林电子科技大学 | Cluster pulse signal energy synchronization detection method in pulse ultra-broadband communication system |
| JP5159704B2 (en) * | 2009-05-25 | 2013-03-13 | 古野電気株式会社 | Reference frequency generator |
| CN101610123B (en) * | 2009-07-10 | 2013-03-20 | 中兴通讯股份有限公司 | Clock unit and realization method thereof |
| US8446193B2 (en) * | 2011-05-02 | 2013-05-21 | National Semiconductor Corporation | Apparatus and method to hold PLL output frequency when input clock is lost |
| CN103259538B (en) * | 2012-02-15 | 2016-04-06 | 珠海扬智电子科技有限公司 | There is chip and the control method thereof of anti-astonished function |
| CN103580683A (en) * | 2012-08-02 | 2014-02-12 | 中船重工（武汉）凌久电气有限公司 | Method for implementing analog circuit of sine output phase-locked loop |
| CN102868399B (en) * | 2012-10-11 | 2015-01-21 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
| CN104022778B (en) * | 2014-06-24 | 2017-06-27 | 瑞斯康达科技发展股份有限公司 | A kind of analog phase-locked loop circuit and its signal processing method |
| CN104811195B (en) * | 2015-05-26 | 2017-09-19 | 成都西蒙电子技术有限公司 | A kind of frequency calibration device and frequency synthesizer |
| CN107895967A (en) * | 2017-11-21 | 2018-04-10 | 西安许继电力电子技术有限公司 | A kind of grid-connected converter low voltage crossing locks phase improved method |
| CN108551341A (en) * | 2018-05-02 | 2018-09-18 | 上海顺久电子科技有限公司 | A kind of compensation method of phase-locked loop apparatus and phase-locked loop circuit |
| CN109120393B (en) * | 2018-09-27 | 2023-10-27 | 深圳市傲科光电子有限公司 | Low-power consumption clock data recovery circuit and receiver |
| CN110971230B (en) * | 2018-09-30 | 2023-06-30 | 苏州四方杰芯电子科技有限公司 | High-performance phase-locked loop circuit control system |
| CN111222294A (en) * | 2018-11-23 | 2020-06-02 | 深圳市中兴微电子技术有限公司 | Method and device for simulating smooth transition of reference clock in phase-locked loop locking state |
| WO2021016740A1 (en) * | 2019-07-26 | 2021-02-04 | 深圳欣锐科技股份有限公司 | Single-phase adaptive phase-locked apparatus and method |
| CN111106827B (en) * | 2019-12-09 | 2022-05-31 | 中山大学 | Method, system and storage medium for detecting power supply fluctuation in digital chip |
| CN112953518A (en) * | 2021-03-30 | 2021-06-11 | 南京中科微电子有限公司 | Phase-locked loop structure used in superheterodyne two-stage down-conversion receiver |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1286532A (en) * | 1999-08-26 | 2001-03-07 | 阿尔卡塔尔公司 | Phase-locked loop frequency synthesizer |
| CN1474509A (en) * | 2002-08-09 | 2004-02-11 | 华为技术有限公司 | Method for smoothly change-over of main and spare clock for synchronous digital transmission equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2765443B2 (en) * | 1993-08-05 | 1998-06-18 | 日本電気株式会社 | Phase locked loop circuit |
-
2005
- 2005-10-21 CN CNB2005101007009A patent/CN100512011C/en not_active Expired - Fee Related
-
2006
- 2006-10-18 WO PCT/CN2006/002755 patent/WO2007045171A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1286532A (en) * | 1999-08-26 | 2001-03-07 | 阿尔卡塔尔公司 | Phase-locked loop frequency synthesizer |
| CN1474509A (en) * | 2002-08-09 | 2004-02-11 | 华为技术有限公司 | Method for smoothly change-over of main and spare clock for synchronous digital transmission equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007045171A1 (en) | 2007-04-26 |
| CN1859006A (en) | 2006-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100512011C (en) | System and method for realizing holding fuction by analogue phase locking loop | |
| EP0044153B1 (en) | Controlled frequency signal source apparatus including a feedback path for the reduction of phase noise | |
| CN104022778B (en) | A kind of analog phase-locked loop circuit and its signal processing method | |
| CN101151838B (en) | Data cleaning with an asynchronous reference clock | |
| US6069505A (en) | Digitally controlled tuner circuit | |
| US9231562B2 (en) | Decimation filter | |
| US5739727A (en) | Sampled phase locked loop being locked with support from another phase locked loop | |
| EP2140549B1 (en) | Oscillator signal stabilization | |
| US20090108891A1 (en) | Bandwidth control in a mostly-digital pll/fll | |
| CN110890887A (en) | Apparatus and method for preserving PLL output frequency when input clock is lost | |
| CN111900977B (en) | Circuit for carrying out fast gain calibration on digital time converter of phase-locked loop | |
| CN101399542A (en) | Phase lock loop having temperature drift compensation and method thereof | |
| CN107306125A (en) | Signal generating circuit and signal creating method | |
| CN104702275B (en) | A kind of Low phase noise microwave frequency source circuit and device and method | |
| CN106209087A (en) | The calibration system and method for voltage controlled oscillator in phase-locked loop | |
| EP1755218A2 (en) | Tunable resonator for use in active-RC continuous-time filters | |
| US6400932B1 (en) | Low offset automatic frequency tuning circuits for continuous-time filter | |
| CN109698697B (en) | Phase-locked loop device applied to FPGA chip and FPGA chip | |
| CN204272083U (en) | A kind of ultrashort wave frequency hopping station frequency synthesizer | |
| DE19529179C2 (en) | Integrable clock acquisition circuit | |
| CN102075181B (en) | Frequency synthesizer and frequency-locked loop | |
| CN116232318A (en) | Phase-locked loop, chip and electronic equipment | |
| US4646031A (en) | Narrowband phase-lock loop circuit with automatic convergence | |
| CN205510015U (en) | Realize structure of phase -locked loop quick lock in | |
| CN201550097U (en) | Frequency-locked loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170926 Address after: 242100 Anhui province Xuancheng city Langxi County Xuan Guang tea industry company Yu Zhang Xin Village 29 Patentee after: Liu Yu Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090708 Termination date: 20171021 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |