CN201550097U - Frequency-locked loop - Google Patents
Frequency-locked loop Download PDFInfo
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- CN201550097U CN201550097U CN2009202558657U CN200920255865U CN201550097U CN 201550097 U CN201550097 U CN 201550097U CN 2009202558657 U CN2009202558657 U CN 2009202558657U CN 200920255865 U CN200920255865 U CN 200920255865U CN 201550097 U CN201550097 U CN 201550097U
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Abstract
The utility model discloses a frequency-locked loop, comprising a digital loop filter, a data acquisition unit, a comparing unit, an aging correction word generating unit and a correcting unit. The data acquisition unit collects digital data output by the digital loop filter, conducts weighing processing for the digital data so as to obtain a weighing value, and uses the weighing value as current weighing value to supply the weighing value to the comparing unit; the comparing unit compares the current weighing value with a standard weighing value, and supplies the compared result to the aging correction word generating unit; the aging correction word generating unit adjusting the current aging correction word according to the compared result, in order to generate the latest aging correction word; the correcting unit utilizes the latest aging correction word to correct a frequency control word. When a crystal oscillator has aging frequency drift, the effect on output frequency can be eliminated or decreased through drift compensation of an aging compensation feedback loop.
Description
[technical field]
The utility model relates to electronic circuit design field, particularly the compensation technique of FLL.
[background technology]
The frequency of crystal oscillator output all can be drifted about along with variation of temperature, the various frequencies that generate based on the frequency of crystal oscillator output all can be drifted about thereupon like this, in order to solve this technical problem, application number is 200810037670.5, open day is on September 24th, 2008, publication number is the frequency synthesizer that the Chinese patent application of CN101272142A discloses a kind of temperature frequency compensation, and Fig. 1 shows the block diagram of the described frequency synthesizer in this patent application.
As shown in Figure 1, described frequency synthesizer 100 comprises oscillating circuit 101, FLL 107, frequency correction unit 109, digital temperature sensor 103, decode logic unit 105, frequency correction look-up table 111 and interpolation logical block 115.Described oscillating circuit 101 generates reference frequency signal f by crystal oscillator 117
RDescribed FLL 107 is based on described reference frequency signal f
RGenerate the desired output frequency f with frequency correction control word FCW_new
OUTDescribed frequency correction unit 109 is according to temperature and frequency correcting word FCW
TmpCompensation automatic frequency control word FCW
AFCTo obtain frequency correction control word FCW_new, wherein: FCW_new=FCW
AFC+ FCW
TmpDescribed automatic frequency control word FCW
AFCComprise fixed frequency control word FCW and automatic frequency correction word AFC, described automatic frequency control word FCW
AFCCan be expressed as following formula: FCW
AFC=FCW+AFC.
Determine the temperature and frequency correcting value of each discrete temperature spot correspondence in advance according to the temperature frequency indicatrix of crystal oscillator 117, and with these storage in frequency correction look-up table 111, the current temperature value of sensing according to digital temperature sensor 103 finds suitable temperature and frequency correcting word FCW at frequency correction look-up table 111 afterwards
Tmp, afterwards by 115 couples of described suitable temperature and frequency correcting word FCW of interpolation logical block
TmpCarry out interpolation processing to obtain the temperature and frequency correcting word FCW of current temperature value correspondence
Tmp, utilize temperature and frequency correcting word FCW subsequently
TmpTo automatic frequency control word FCW
AFCCarry out the temperature frequency drift compensation to obtain the frequency correction control signal FCW_new behind the temperature and frequency correcting.Like this, just realized compensation to the temperature frequency drift of crystal oscillator.
200810037670.5 the temperature and frequency correcting in number patent application belongs to frequency precorrection, promptly owing to can record the temperature frequency drift curve of crystal oscillator, therefore can pre-configured temperature and frequency correcting word to temperature frequency drift proofread and correct.Yet, crystal oscillator also can produce frequency drift along with wearing out, such as using the initial stage at an electronic equipment, the frequency of the crystal oscillator output in it can be very accurate after process said temperature frequency correction, but after this electronic equipment has used 1 or 2 year, though the frequency of the output of the crystal oscillator in it is passed through temperature and frequency correcting but still can be drifted about.
At present, for crystal oscillator produce frequency drift owing to aging, also do not have very effective, suitable solution.
[utility model content]
The purpose of this part is to summarize some aspects of embodiment of the present utility model and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit scope of the present utility model.
One of the technical problems to be solved in the utility model is to provide a kind of FLL, and it can compensate the aging frequency drift that produces owing to crystal oscillator.
In order to address the above problem, according to an aspect of the present utility model, the utility model provides a kind of FLL, and it comprises digital loop filters, data acquisition unit, comparing unit, aging correct word generation unit and correcting unit.Described data acquisition unit is gathered the numerical data of described digital loop filters output, and described numerical data is carried out weight handle to obtain weight numerical value, and described weight numerical value offered described comparing unit as current weight numerical value, more current weight numerical value of described comparing unit and standard weight numerical value, and comparative result offered described aging correct word generation unit, described aging correct word generation unit is adjusted to generate up-to-date aging correct word current aging correct word according to comparative result, and described correcting unit utilizes described up-to-date aging correct word that described frequency control word is proofreaied and correct.
Further, after described output frequency locking, the numerical data of digital loop filters output is gathered in the data sampling unit, and described numerical data is carried out weight handle and to obtain an initial weight numerical value, and this initial weight numerical value is offered described comparing unit as standard weight numerical value.
Further, be the initial aging correct word that aging correct word generation unit is provided with, when wearing out drift compensation for the first time, current aging correct word is initial aging correct word.
Further, described aging correct word generation unit will constantly be adjusted described current aging correct word, when described current weight numerical value converges on standard weight numerical value till.
Further, the described comparative result of described comparing unit output comprises that current weight numerical value overgauge weight numerical value and current weight numerical value are less than standard weight numerical value, when current weight numerical value overgauge weight numerical value, described aging correct word generation unit need be turned described aging correct word down, during less than standard weight numerical value, described aging correct word generation unit need be transferred big described aging correct word at current weight numerical value.
Further, described correcting unit wears out to described frequency correction word according to following formula and proofreaies and correct or compensation: FCW
ACW=FCW+ACW, wherein FCW
ACWFrequency correction word after expression is proofreaied and correct, FCW represents the frequency correction word, ACW represents aging correct word.
Further, it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, low pass filter, voltage controlled oscillator and frequency digital quantizer, wherein said digit phase accumulator, receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct; Described voltage controlled oscillator is based on input voltage generated frequency signal, and described frequency digital quantizer provides the numerical frequency data flow of the frequency values of the expression frequency signal that described voltage controlled oscillator is exported; The numerical frequency comparator, more described numerical frequency data flow and described reference frequency data flow, and output error signal; Described digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering; Described digital analog converter is connected with digital loop filters, and the output that receives digital loop filters is to generate analog signal; Described low pass filter is used for described analog signal is carried out filtering, and filtered analog signal is used to control the input voltage of described voltage controlled oscillator.
Further, it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, gain controller, digital controlled oscillator and frequency digital quantizer, wherein said digit phase accumulator, receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct; The frequency signal that described digital controlled oscillator generates, described frequency digital quantizer provide the numerical frequency data flow of the frequency values of the expression frequency signal that described digital controlled oscillator is exported; The numerical frequency comparator, more described numerical frequency data flow and described reference frequency data flow, and output error signal; Described digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering; Described gain controller is connected with digital loop filters, and the output that receives digital loop filters is used to control the digital controlled signal of described digital controlled oscillator with generation.
Compared with prior art, when the utility model aging frequency drift occurred at crystal oscillator, by the compensation of ageing feedback loop can to since the aging frequency drift that causes of crystal oscillator compensate, thereby can eliminate or reduce influence to output frequency.
About other purposes of the present utility model, feature and advantage are described in detail in embodiment below in conjunction with accompanying drawing.
[description of drawings]
In conjunction with reaching ensuing detailed description with reference to the accompanying drawings, the utility model will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:
Fig. 1 shows the block diagram of a kind of frequency synthesizer of the prior art;
Fig. 2 shows the block diagram of an embodiment of the frequency synthesizer in the utility model;
Fig. 3 shows the block diagram of an embodiment of the FLL in the utility model;
Fig. 4 shows the block diagram of another embodiment of the FLL in the utility model;
Fig. 5 shows the block diagram of another embodiment of the FLL in the utility model; With
Fig. 6 shows the block diagram of the another one embodiment of the FLL in the utility model.
[embodiment]
Detailed description of the present utility model is mainly come the running of direct or indirect simulation technical solutions of the utility model by program, step, logical block, process or other symbolistic descriptions.Be the thorough the utility model of understanding, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the utility model then may still can be realized.Affiliated those of skill in the art use these descriptions herein and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the purpose of this utility model of avoiding confusion, owing to method, program, composition and the circuit known are readily appreciated that, so they are not described in detail.
Alleged herein " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent the sequence of modules in method, flow chart or the functional block diagram of one or more embodiment and revocablely refer to any particular order, also do not constitute restriction of the present utility model.
Fig. 2 shows the block diagram of an embodiment of the frequency synthesizer 200 in the utility model.Described frequency synthesizer 200 comprises oscillating circuit 201 and FLL 203, and described oscillating circuit 201 generates reference frequency signal f by crystal oscillator 301
R, described FLL 203 is based on reference frequency signal f
RAnd the output frequency f that generation is expected according to frequency control word (Frequency Control word is called for short FCW)
OUTBy defining suitable frequency control word, the output frequency that the user can obtain expecting.Described frequency control word can be represented with binary sequence, binary sequence such as 32,16 or 8, it can be through the frequency control word behind the temperature and frequency correcting, also can be the frequency control word without temperature and frequency correcting, can also be the frequency control word through other processing.Described FLL 203 can detect output frequency f
OUTOwing to the aging frequency drifts that cause of crystal oscillator 301, and according to described frequency drift frequency control word wear out and proofreaies and correct or compensation, utilize the frequency control word after the aging correction to carry out frequency locking subsequently.
Fig. 3 shows the block diagram of an embodiment of the FLL 300 in the utility model, and described FLL 300 can be as the FLL 203 among Fig. 2.Described FLL 300 can be come locking frequency according to the desired output frequency of frequency control word FCW definition, the feedback loop that it comprises phase accumulator 320, numerical frequency comparator 321, digital loop filters 323, D/A (digital-to-analog) transducer 325, low pass filter 327, voltage controlled oscillator (voltage-controlled oscillator is called for short VCO) 329 and comprises frequency divider 333 and frequency digital quantizer 331.
Different at the phase-locked loop of phase region with conventional operation, described FLL 300 is operated in frequency domain, and an advantage of described FLL 300 is that described frequency comparator 321 has high linearity and can be designed as digital logic circuit.Described traditional phase-locked loop realizes with analog circuit usually, its design cost is increased and is difficult to realize free integrated with digital circuit.In addition, described analog phase-locked look is also very sensitive to the variation of technology, voltage and environment.For FLL, can produce any desired output frequency by setting the FCW value, the precision of frequency is by word length and the reference frequency f of FCW
RDecision.For instance, reference frequency f
RBe 50MHz, the word length of FCW is 32, and the precision of frequency can reach so
By using the numerical frequency comparator 321 and the digital loop filters 323 of high linearity, FLL 300 can obtain low noise and high-precision signal.Be used in the frequency signal f that the frequency divider 333 in the feedback path can generate voltage controlled oscillator 329
VCOFrequency division is to intermediate-freuqncy signal f
IF, f wherein
IF=f
VCO/ div_n, div_n are the Frequency Dividing Factors of frequency divider 133.Described frequency digital quantizer 331 provides its input signal of expression f
IFThe numerical frequency data flow Pvco of frequency values.The effect of described frequency digital quantizer 331 is to utilize reference frequency f
RTo input signal f
IFClock cycle (such as rising edge or trailing edge) count, the predetermined clock number is standardized as numerical frequency data flow Pvco, described numerical frequency data flow Pvco will be as an input of numerical frequency comparator 321.Described phase accumulator 320 is with reference frequency f
RGenerate the reference frequency data flow Posc of expression incoming frequency control word FCW setpoint frequency value for the basis.
Behind loop-locking, numerical frequency data flow Pvco should be identical with reference frequency data flow Posc.Described numerical frequency comparator 321 produces an error signal by comparative figures frequency data stream Pvco and reference frequency data flow Posc.Subsequently, 323 pairs of described error signals of described digital loop filters are carried out digital filtering.Described digital loop filters 323 provides the control of loop bandwidth and lock adjustment time.By using described digital loop filters 323, can be according to needs (such as phase noise and adjusting time) the active control loop bandwidth and the lock adjustment time of FLL.The output of described digital loop filters 323 is input to digital analog converter 325 to generate an analog signal.The analog output signal of described digital analog converter 325 is used to control the input voltage of voltage controlled oscillator 329 after the process further low-pass filtering of described low pass filter 327.Behind loop-locking, the output of voltage controlled oscillator 329 is locked to the expected frequency that frequency control word FCW sets.
Yet the aging meeting of crystal oscillator 301 causes reference frequency f
RDrift, thereby can cause the variation of numerical frequency data flow Pvco and reference frequency data flow Posc, though loop still can lock at last, and numerical frequency data flow Pvco is still identical with reference frequency data flow Posc in the locking back, but this moment, drift took place in the output frequency of voltage controlled oscillator 329, and this drift can't be regulated or proofread and correct by above-mentioned loop.In order to proofread and correct or compensate the aging drift that causes owing to crystal oscillator 301, described FLL 300 also disposes data acquisition unit 335, comparing unit 337, aging correct word (aging correction word, be called for short ACW) generation unit 339 and correcting unit 341, these unit can be referred to as the compensation of ageing feedback loop.
Because just be used as the aanalogvoltage of importing voltage controlled oscillator 329 behind the numerical data process digital analog converter 325 of digital loop filters 323 outputs and the low pass filter 327, and at output frequency f
OUTAfter the locking, what described aanalogvoltage should be able to the long period converges near the fixed value, so corresponding, and the numerical data of digital loop filters 323 outputs should also restrain in a long time.Therefore, described data acquisition unit 335 is provided to gather the numerical data of digital loop filters 323 outputs, and described numerical data is carried out weight handle and to obtain a weight numerical value, wherein said weight numerical value is directly corresponding with the aanalogvoltage of input voltage controlled oscillator 329 on physical meaning, that is to say that described weight numerical value can directly reflect the value of the aanalogvoltage of importing voltage controlled oscillator 329.Further, described weight numerical value just can directly reflect the value of the output frequency of voltage controlled oscillator 329, in other words, if the output frequency of voltage controlled oscillator 329 has produced drift, will cause described weight numerical value that drift or variation take place so.
Before described frequency synthesizer or the application of described FLL input or before putting goods on the market, can carry out initialization to each unit in the compensation of ageing feedback loop.In one embodiment, at described output frequency f
OUTAfter the locking, the numerical data of digital loop filters 323 outputs is gathered in data sampling unit 335, and described numerical data is carried out weight handle and to obtain an initial weight numerical value, and this initial weight numerical value is offered described comparing unit 337 as standard weight numerical value.In addition, the initial aging correct word in the aging correct word generation unit 339 can also be set, be 0 such as described initial aging correct word is set.
Through after the initialization, can be provided with every the scheduled time and carry out once aging drift compensation or correction, also wear out in real time drift compensation or correction can be set.At drift compensation or the timing of wearing out, described data acquisition unit 335 is gathered the numerical data of digital loop filters 323 outputs, and described numerical data is carried out weight handle obtaining a weight numerical value, and described weight numerical value is offered comparing unit 337 as current weight numerical value.Described comparing unit 337 more current weight numerical value and standard weight numerical value, and comparative result offered described ACW generation unit 339, described ACW generation unit 339 is adjusted to generate up-to-date ACW current ACW according to comparative result, and described correcting unit 341 utilizes up-to-date ACW that described FCW is proofreaied and correct or compensates.
Subsequently, described data acquisition unit 335 continues to gather the numerical data of digital loop filters 323 outputs, and continue that described numerical data is carried out weight and handle obtaining another weight numerical value, and described another weight numerical value is offered comparing unit 337 as current weight numerical value.Described comparing unit 337 continues more current weight numerical value and standard weight numerical value, and will and comparative result be offered described ACW generation unit 339 once more, described ACW generation unit 339 is adjusted to generate up-to-date ACW current ACW according to comparative result once more, and described correcting unit 341 utilizes up-to-date ACW that described FCW is proofreaied and correct or compensates.Constantly repeat aforesaid operations, when described current weight numerical value converges on standard weight numerical value till.
After aging drift compensation finished, described data acquisition unit 335 and comparing unit 337 just can quit work, and the ACW that described correcting unit 341 then can provide according to ACW generation unit 339 always proofreaies and correct or compensates described frequency control word.Frequency control word after aging correction or the compensation enters described phase accumulator 320, and described phase accumulator 320 is with reference frequency f
RReference frequency data flow Posc for the frequency control word setpoint frequency value after the aging correction of basis generation expression input.It should be noted that comparative result between current weight numerical value and the standard weight numerical value can reflect the trend of frequency drift, therefore 339 of described ACW generation units need to adjust described ACW so that the FCW after the compensation is just passable to opposite trend adjustment.Adjust if carry out for the first time ACW, so described current ACW value is exactly initial ACW, such as being 0.
In one embodiment, described data acquisition unit 335 is gathered the scheduled duration of digital loop filters 323 outputs (such as 3 seconds, time, long-acting more fruit was good more) or predetermined figure (1M position, the long-acting more fruit of figure place is good more) numerical data, and described numerical data is carried out weight handles and to obtain a weight numerical value.When specific implementation, described data acquisition unit 335 can be gathered the numerical data of a period of time, and obtain a weight numerical value, data acquisition unit 335 can then be gathered the numerical data of a period of time more afterwards, and obtain another weight numerical value, judge that afterwards two adjacent weighted values get difference whether in allowed band, if, illustrate that then weight numerical value is stable, weight numerical value after will stablizing subsequently offers described comparing unit 337, otherwise, illustrate that then weight numerical value is still unstable, continue to obtain next weight numerical value subsequently, and continue to judge whether this weight numerical value is stable.Handle in the example weight, described numerical data can be added up, itself and can be used as weight numerical value, be exactly 7 such as the weight numerical value of one 10 binary sequences 1100111101.Handling in example in another weight, described numerical data can be added up, will average afterwards, is exactly 7/10=0.7 such as still 10 the weight numerical value of binary sequence 1100111101.Handle in the example in other weight, can also adopt some complicated smoothing processing algorithms.
In one embodiment, the described comparative result of described comparing unit 337 outputs comprises that current weight numerical value overgauge weight numerical value, current weight numerical value are locked in standard weight numerical value less than standard weight numerical value, current weight numerical value.When current weight numerical value overgauge weight numerical value, described ACW generation unit 339 need be turned described aging correct word ACW down, at current weight numerical value during less than standard weight numerical value, described ACW generation unit 339 needs to transfer big described aging correct word ACW, be locked in standard weight numerical value at described current weight numerical value, described ACW generation unit 339 keeps described aging correct word ACW constant.
In one embodiment, can determine as required that described step-length has directly determined aging frequency compensated speed to the amplitude (being step-length) of each adjustment of ACW.As a rule, the frequency drift of crystal oscillator is generally all very little, and such as several hertz, therefore, described step-length also can be smaller.In another embodiment, described ACW generation unit 339 can be selected according to the difference between current weight numerical value and the initial weight numerical value and adjust step-length, and according to described step-length described ACW is adjusted, and can accelerate regulating the speed of ACW like this.
In one embodiment, described correcting unit 341 wears out to FCW according to following formula and proofreaies and correct or compensation: FCW
ACW=FCW+ACW, the FCW after the correction
ACWEntering phase accumulator 420 handles.
Advantage, characteristics or a benefit of the present utility model are: when aging frequency drift has appearred in crystal oscillator, by the drift compensation of compensation of ageing feedback loop, make output frequency not be affected, and still can be locked on the assigned frequency exactly.In addition,, be easy to realize, and be convenient to integratedly that and the compensation precision of frequency drift is also very high because the compensation of ageing feedback loop all is digital circuit, in theory can be identical with the FREQUENCY CONTROL precision of FCW, can reach 1Hz or above control precision easily.Theoretically, adopt analog circuit also can realize the compensation of aging frequency drift,, expect reaching the precision of 1Hz so, then must can detect 1/10M=10 such as the voltage controlled oscillator (1 volt of the every change of voltage, frequency variation 10MHz) that adopts 10Mhz/V
-7The change in voltage of volt, and this is to be difficult to realize in the analog circuit field.
Fig. 4 shows the block diagram of another embodiment of the FLL 400 in the utility model, and described FLL 400 can be as the FLL 203 among Fig. 2.FLL 400 shown in Fig. 4 includes phase accumulator 420, numerical frequency comparator 421, digital loop filters 423, D/A converter 425, low pass filter 427, voltage controlled oscillator 429, frequency divider 433, frequency digital quantizer 431, data acquisition unit 435, comparing unit 437, ACW generation unit 439 and correcting unit 441.As can be seen, FLL 400 among Fig. 4 is identical with FLL 300 structure major parts among Fig. 3, both are difference: replaced frequency digital quantizer 331 with direct frequency digital quantizer 431 in the FLL 400 in Fig. 4, and the frequency signal f of voltage controlled oscillator 429 outputs
VCODirectly offer described direct frequency digital quantizer 431, the frequency signal f of 433 pairs of voltage controlled oscillators of frequency divider, 429 outputs
VCOCarry out frequency division and obtain output frequency f
OUT
Described direct frequency digital quantizer 431 is used for direct output signal with voltage controlled oscillator 429 and is converted to numerical frequency data flow Pvco.For described direct frequency digital quantizer 431, described frequency sampling is (such as VCO output f by the high frequency output signal
VCO) the known frequency reference frequency f of sampling
RRealize.One of advantage of this framework is owing to the VCO output Pvco with high frequency comes the frequency reference frequency f
RSample, thereby improved the precision of frequency digital quantizer 431.Usually the precision of frequency digital quantizer is and uses sample frequency proportional.Sample frequency is high more, and the result is accurate more, and noise is low more.In addition, this framework has been simplified the design of the frequency divider in the feedback path and has been reduced hardware cost and related power consumption.For different output frequencies, frequency divider 433 can be used to the output f of frequency division voltage controlled oscillator
VCONeeding to obtain output frequency.
Fig. 5 shows the block diagram of another embodiment of the FLL 500 in the utility model, and described FLL 500 can be as the FLL 203 among Fig. 2.FLL 500 shown in Fig. 5 includes phase accumulator 501, numerical frequency comparator 503, digital loop filters 505, gain control unit 507, digital controlled oscillator (digitally controlled oscillator is called for short DCO) 509, frequency divider 511, frequency digital quantizer 513, data acquisition unit 535, comparing unit 537, ACW generation unit 539 and correcting unit 541.As can be seen, FLL 500 among Fig. 5 is identical with FLL 300 structure major parts among Fig. 3, and both are difference: the FLL 500 usefulness gain control units 507 among Fig. 5, digital controlled oscillator 509 have replaced low pass filter 327, the voltage controlled oscillator 329 in the FLL 300 among Fig. 3 respectively.
Described digital controlled oscillator is to finish by the voltage-operated variable capacitor design of using the numerical control capacitor array to substitute in traditional voltage controlled oscillator.Weighting switch binary system electric capacity (such as variable capacitor) array can advance the stages of digital control signal by two and switch to high capacitance pattern or low capacitive.Just can obtain high-resolution capacitance by the numerical control position of using the delta-sigma modulation.As shown in Figure 5, the corresponding module among the frequency divider 511 in phase accumulator 501, numerical frequency comparator 503, digital loop filters 505, the feedback path and frequency digital quantizer 513 and Fig. 3 has identical functions.
The output of described digital loop filters 505 is connected to the input of gain control unit 507, and described gain control unit 507 can generate the digital controlled signal of the weighting switch binary system capacitor array that is used to control digital controlled oscillator.Described gain control unit 507 is used for normalization digital controlled oscillator gain and eliminates the influence to digital controlled oscillator phase place and frequency from technology, voltage and temperature.The frequency signal f that described digital controlled oscillator 609 generates according to the digital signal from gain control unit 507
DCOBehind loop-locking, by using numerical frequency comparator 503, numerical frequency data flow Pvco is locked to reference frequency data flow Posc.Like this, the output of digital controlled oscillator 509 is locked to the expected frequency that frequency control word FCW sets.
As shown in Figure 5, thereby can remove digital analog converter and low pass filter among Fig. 3 by utilizing digital controlled oscillator to substitute voltage controlled oscillator, whole like this FLL 500 can realize by digital logical course.Like this, frequency signal will be not easy to be subjected to the influence of noise and other environment.This framework especially is fit to low pressure, deep-submicron COMS technology, because the traditional analog oscillator the range of linearity owing to low-voltage becomes very little, and has higher gain, this makes analog vco very easily be subjected to the influence of noise and operating point drift, but, adopt digital vco just will be not easy to be subjected to the influence of low-voltage and other factor of environmental.
Same, data acquisition unit 535 in Fig. 5, comparing unit 537, ACW generation unit 539 and correcting unit 541 can be formed the compensation of ageing feedback loop equally, also can be as Fig. 3, to frequency drift that cause well compensates or proofreaies and correct by the aging of crystal oscillator.
Fig. 6 shows the block diagram of the another one embodiment of the FLL 600 in the utility model, and described FLL 600 can be as the FLL 203 among Fig. 2.FLL 600 shown in Fig. 6 includes phase accumulator 601, numerical frequency comparator 603, digital loop filters 605, gain control unit 607, digital controlled oscillator 609, frequency divider 611, direct frequency digital quantizer 613, data acquisition unit 635, comparing unit 637, ACW generation unit 639 and correcting unit 641.As can be seen, FLL 600 among Fig. 6 is identical with FLL 500 structure major parts among Fig. 5, both are difference: replaced the frequency digital quantizer 513 among Fig. 5 with direct frequency digital quantizer 613 in the FLL 600 in Fig. 6, and the frequency signal f of digital controlled oscillator 509 outputs
DCODirectly offer described direct frequency digital quantizer 613, the frequency signal f of 611 pairs of digital controlled oscillators of frequency divider, 609 outputs
DCOCarry out frequency division and obtain output frequency f
OUT
Same, data acquisition unit 635 in Fig. 6, comparing unit 637, ACW generation unit 639 and correcting unit 641 can be formed the compensation of ageing feedback loop equally, also can be as Fig. 3, to frequency drift that cause well compensates or proofreaies and correct by the aging of crystal oscillator.
In one embodiment, also can not use frequency divider that the output signal of described digital controlled oscillator or voltage controlled oscillator is carried out frequency division, and the output signal of directly using described digital controlled oscillator or voltage controlled oscillator is as the desired output frequency.Described frequency digital quantizer in different embodiment and described direct frequency digital quantizer are realizing that on the principle be duplicate, and they can be called the frequency digital quantizer.
The above only is preferred embodiment of the present utility model, and is in order to restriction the utility model, not all within spirit of the present utility model and principle, any modification of being done, is equal to replacement etc., all should be included within the protection range of the present utility model.
Claims (8)
1. FLL is characterized in that it comprises:
Digital loop filters;
Be connected with described digital loop filters, gather the numerical data of described digital loop filters output, and described numerical data is carried out weight handle to obtain the data acquisition unit of weight numerical value;
Be connected with described data acquisition unit, will be from the described weight numerical value of described data acquisition unit as current weight numerical value, the comparing unit of more current weight numerical value and standard weight numerical value;
Be connected with described comparing unit, receive comparative result, and current aging correct word is adjusted to generate the aging correct word generation unit of up-to-date aging correct word according to comparative result from described comparing unit; With
Be connected the correcting unit that utilizes described up-to-date aging correct word that frequency control word is proofreaied and correct with described aging correct word generation unit.
2. FLL as claimed in claim 1, it is characterized in that, the numerical data of digital loop filters output is gathered in described data sampling unit, and described numerical data is carried out weight handle and to obtain an initial weight numerical value, and this initial weight numerical value is offered described comparing unit as standard weight numerical value.
3. FLL as claimed in claim 1 is characterized in that, for aging correct word generation unit is provided with initial aging correct word, when wearing out drift compensation for the first time, current aging correct word is initial aging correct word.
4. FLL as claimed in claim 1 is characterized in that, described aging correct word generation unit will constantly be adjusted described current aging correct word, when described current weight numerical value converges on standard weight numerical value till.
5. FLL as claimed in claim 1, it is characterized in that, comparative result from described comparing unit comprises that current weight numerical value overgauge weight numerical value and current weight numerical value are less than standard weight numerical value, when current weight numerical value overgauge weight numerical value, described aging correct word generation unit need be turned described aging correct word down, during less than standard weight numerical value, described aging correct word generation unit need be transferred big described aging correct word at current weight numerical value.
6. FLL as claimed in claim 1 is characterized in that, described correcting unit according to following formula to described frequency correction word correction: the FCW that wears out
ACW=FCW+ACW, wherein FCW
ACWFrequency correction word after expression is proofreaied and correct, FCW represents the frequency correction word, ACW represents aging correct word.
8. as each described FLL of claim 1-7, it is characterized in that, it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, low pass filter, voltage controlled oscillator and frequency digital quantizer, wherein said digit phase accumulator, receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct;
Described voltage controlled oscillator is based on input voltage generated frequency signal, and described frequency digital quantizer provides the numerical frequency data flow of the frequency values of the expression frequency signal that described voltage controlled oscillator is exported;
The numerical frequency comparator, more described numerical frequency data flow and described reference frequency data flow, and output error signal;
Described digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering;
Described digital analog converter is connected with digital loop filters, and the output that receives digital loop filters is to generate analog signal;
Described low pass filter is used for described analog signal is carried out filtering, and filtered analog signal is used to control the input voltage of described voltage controlled oscillator.
9. as each described FLL of claim 1-7, it is characterized in that, it also comprises digit phase accumulator, numerical frequency comparator, digital analog converter, gain controller, digital controlled oscillator and frequency digital quantizer, wherein said digit phase accumulator, receive the frequency correction control word after proofreading and correct, and the frequency correction control word generation reference frequency data flow based on reference frequency signal and after proofreading and correct;
The frequency signal that described digital controlled oscillator generates, described frequency digital quantizer provide the numerical frequency data flow of the frequency values of the expression frequency signal that described digital controlled oscillator is exported;
The numerical frequency comparator, more described numerical frequency data flow and described reference frequency data flow, and output error signal;
Described digital loop filters is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering;
Described gain controller is connected with digital loop filters, and the output that receives digital loop filters is used to control the digital controlled signal of described digital controlled oscillator with generation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102075181B (en) * | 2009-11-24 | 2012-07-25 | 无锡爱睿芯电子有限公司 | Frequency synthesizer and frequency-locked loop |
| CN103562735A (en) * | 2011-04-29 | 2014-02-05 | 美国亚德诺半导体公司 | System and method for detecting fundamental frequency of electric power system |
| CN103684256A (en) * | 2012-09-12 | 2014-03-26 | 无锡华润矽科微电子有限公司 | High-accuracy digital temperature-compensated crystal oscillator circuit structure with built-in crystal oscillator |
| CN104660255A (en) * | 2015-01-31 | 2015-05-27 | 复旦大学 | S-domain model of integrated frequency-modulated continuous wave digital frequency synthesizer |
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- 2009-11-24 CN CN2009202558657U patent/CN201550097U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075181B (en) * | 2009-11-24 | 2012-07-25 | 无锡爱睿芯电子有限公司 | Frequency synthesizer and frequency-locked loop |
| CN103562735A (en) * | 2011-04-29 | 2014-02-05 | 美国亚德诺半导体公司 | System and method for detecting fundamental frequency of electric power system |
| CN103562735B (en) * | 2011-04-29 | 2016-05-04 | 美国亚德诺半导体公司 | For detection of the system and method for the fundamental frequency of power system |
| US9696355B2 (en) | 2011-04-29 | 2017-07-04 | Analog Devices, Inc. | System and method for detecting a fundamental frequency of an electric power system |
| CN103684256A (en) * | 2012-09-12 | 2014-03-26 | 无锡华润矽科微电子有限公司 | High-accuracy digital temperature-compensated crystal oscillator circuit structure with built-in crystal oscillator |
| CN103684256B (en) * | 2012-09-12 | 2016-06-22 | 无锡华润矽科微电子有限公司 | The high accuracy number temperature compensated oscillator circuit structure of built-in crystal oscillator |
| CN104660255A (en) * | 2015-01-31 | 2015-05-27 | 复旦大学 | S-domain model of integrated frequency-modulated continuous wave digital frequency synthesizer |
| CN104660255B (en) * | 2015-01-31 | 2017-12-01 | 复旦大学 | A kind of s domain models of integrated CW with frequency modulation digital frequency synthesizer |
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