KR20240044134A - Phase locked loop and operation method thereof - Google Patents

Abstract

The phase locked loop includes a phase frequency detector that receives an input signal and a divided output signal, compares the frequency of the input signal and the frequency of the divided output signal, and generates an up/down signal; a control voltage generator that receives the up/down signals and generates a control voltage; a voltage control oscillator that receives the control voltage and generates a voltage control oscillator output signal; a frequency divider that divides the output signal of the voltage control oscillator to generate the divided output signal; and a gain adjuster that generates a first control signal for controlling the operation of the voltage controlled oscillator.

Description

Phase locked loop and its operation method {PHASE LOCKED LOOP AND OPERATION METHOD THEREOF}

The present invention relates to a phase-locked loop that can adaptively adjust bandwidth by adjusting the gain of a voltage-controlled oscillator and a method of operating the phase-locked loop.

Figure 1 shows a configuration diagram of a conventional phase locked loop 100.

As can be seen from Figure 1, the conventional phase locked loop 100 includes a phase frequency detection unit 110, a control voltage generator 120, a voltage control oscillator 130, and a frequency divider 140. do.

The phase frequency detection unit 110 receives the input signal Fin and the divided output signal Fdiv, compares the frequencies, and then generates an up signal or a down signal (UP, DOWN). Here, the input signal Fin is a signal input from outside the phase locked loop 100.

The control voltage generator 120 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL).

Specifically, the control voltage generator 120 includes a charge pump 121 and a loop filter 122. Since the charge pump 121 charges or discharges an amount of charge equal to the difference between the up/down signals (UP, DOWN), a current gain (Ip) exists in the process of converting the pulse to current, and this current gain (Ip) Affects the performance of the phase locked loop 100, including lock time. In addition, the loop filter 122 may be configured as a low-pass filter structure, filters noise containing harmonic output components generated during operation, and controls the voltage control oscillator 130 through changes in the amount of charge accumulated using a capacitor. Outputs the control voltage (VCTRL) to be controlled.

That is, the control voltage generator 120 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL) from which noise has been removed.

The voltage controlled oscillator 130 receives the control voltage VCTRL and generates the voltage controlled oscillator output signal FOUT. The voltage-controlled oscillator output signal (FOUT) becomes an output clock signal output from the phase-locked loop 100. Specifically, the voltage controlled oscillator 130 includes a voltage buffer 131 and a voltage controlled oscillator 133.

The voltage buffer 131 supplies driving voltages supplied as a power voltage from the control voltage VCTRL to the ring oscillator included in the voltage controlled oscillator 133. The driving voltage includes a first driving voltage (VCP) and a second driving voltage (VCN).

The voltage-controlled oscillator 133 generates a voltage-controlled oscillator output signal (Fout) by oscillating using the first driving voltage (VCP) and the second driving voltage (VCN).

The frequency divider 140 divides the voltage control oscillator output signal (Fout) to generate the divided output signal (Fdiv). That is, a divided output signal (Fdiv) is generated having a frequency divided by dividing the frequency of the output signal (Fout) of the voltage control oscillator by the dividing ratio (N).

The transfer function of the conventional phase locked loop 100 can be expressed as follows [Equation 1].

In [Equation 1], H(S)open is the open loop transfer function, Ip is the current of the charge pump 121, R is the resistance value of the loop filter 122, C is the capacitor value of the loop filter 122, Kvco represents the gain of the voltage controlled oscillator 133, and N represents the division ratio of the frequency divider 140.

Additionally, the open-loop transfer function can be expressed as follows [Equation 2].

In addition, the loop bandwidth can be expressed as [Equation 3] below.

The loop bandwidth of the phase locked loop 100 is the current (Ip) of the charge pump 121, the gain (Kvco) of the voltage controlled oscillator 133, the resistance (R) and capacitor (C) of the loop filter 122, and , has a fixed value determined by the division ratio (N) of the frequency divider 140. Specifically, the loop bandwidth is determined to be 1/10 to 1/20 the size of the input signal (Fin), and depending on the input signal (Fin), there are cases where the loop bandwidth does not meet an appropriate range.

The present invention aims to solve the technical problems described above, and provides a phase-locked loop whose bandwidth can be adaptively adjusted by adjusting Kvco, the gain of a voltage-controlled oscillator, and a method of operating the phase-locked loop. The purpose is to provide.

A phase locked loop according to an embodiment of the present invention includes a phase and frequency detector (PFD) that detects the phase and frequency of an input signal (Fin); a control voltage generator 220 including a charge pump that reacts in response to the up/down output signals of the phase and frequency detector; Voltage control oscillator 330; A gain adjuster 250 connected to the output of the control voltage generator (VCTRL) to adjust the gain of the voltage control oscillator (VCO); It is characterized in that it includes a frequency divider that converts the output signal of the voltage control oscillator 330 into a divided signal (Fdiv).

A phase locked loop according to another embodiment of the present invention includes a phase and frequency detector (PFD) that detects the phase and frequency of an input signal (Fin); a control voltage generator 320 including a charge pump that reacts in response to the up/down signals output from the phase and frequency detector; Voltage control oscillator 330; a frequency divider 340 that converts the output signal of the voltage controlled oscillator 330 into a divided signal (Fdiv); It is characterized in that it includes a selector 350 that generates a control voltage for adjusting the division ratio of the frequency divider 340.

The method of operating a phase locked loop according to an embodiment of the present invention compares the frequency of the input signal (FIN) and the frequency of the divided output signal (FDIV) to generate up/down signals (UP, DOWN). Step (S110); receiving the up/down signals (UP, DOWN) and generating a control voltage (VCTRL) (S120); receiving the control voltage (VCTRL) and generating gain adjustment signals (C12 to C14, C21 to C24) (S125); Generating an output signal (FOUT) of the voltage control oscillator in response to the driving voltages (VCN, VCP) and gain control signals (C12 to C14, C21 to C24) (S130); dividing the output signal (FOUT) of the voltage control oscillator to generate a divided output signal (FDIV) (S140); and

and receiving the control voltage (VCTRL) and generating the driving voltages (VCP, VCN) (S150).

A method of operating a phase locked loop according to another embodiment of the present invention includes comparing the frequency of the input signal (FIN) and the frequency of the divided output signal (FDIV) to generate up/down signals (UP, DOWN). (S210); receiving the up/down signals (UP, DOWN) and generating a control voltage (VCTRL) (S220); A step (S230) of receiving the control voltage (VCTRL) and generating driving voltages (VCN, VCP) and gain adjustment signals (C11 to C24) of the power supply voltage of the voltage control oscillator; Generating an output signal (FOUT) of the voltage controlled oscillator using the driving signals (VCN, VCP) and the gain control signals (C11 to C24) (S235); Generating mode selection signals (MODE_8, MODE_2) using the frequency selection signal (F_SEL) and the manufacturing process variable signal (S2) (S250); and generating a divided signal (FDIV) by dividing the output frequency (FOUT) of the voltage controlled oscillator at a division rate determined by the mode selection signals (MODE_8, MODE_2) (S240). do.

According to the phase locked loop and the operating method of the phase locked loop of the present invention, the bandwidth can be adaptively adjusted by adjusting Kvco, which is the gain of the voltage controlled oscillator.

1 is a configuration diagram of a conventional phase-locked loop.
2 is a configuration diagram of a phase locked loop according to the first embodiment.
Figure 3 is a configuration diagram of a gain adjustment unit according to the first embodiment.
Figure 4 is a configuration diagram of a multiplexer according to the first embodiment.
5 is a configuration diagram of a voltage-controlled oscillator according to the first embodiment.
6 is a graph of an input signal depending on the control voltage of a phase-locked loop according to the first embodiment.
Figure 7 is a configuration diagram of a phase locked loop according to the second embodiment.
Figure 8 is a configuration diagram of a selector according to the second embodiment.
Figure 9 is an example setting according to a process correction signal and a selection signal.
10 is a flowchart of a method of operating a phase locked loop according to the first embodiment.
11 is a flowchart of a method of operating a phase-locked loop according to a second embodiment.

Hereinafter, an adaptive bandwidth phase locked loop with a Kvco adjustment function and a method of operating the phase locked loop according to embodiments of the present invention will be described in detail with reference to the attached drawings.

Of course, the following examples of the present invention are only intended to embody the present invention and do not limit or limit the scope of the present invention. Anything that can be easily inferred by an expert in the technical field to which the present invention belongs from the detailed description and embodiments of the present invention will be interpreted as falling within the scope of the rights of the present invention.

Figure 2 shows a configuration diagram of the phase locked loop 200 according to the first embodiment.

As can be seen from FIG. 2, the phase locked loop 200 according to the first embodiment includes a phase frequency detector 210, a control voltage generator 220, a voltage control oscillator 230, and a frequency divider 240. and a gain adjustment unit 250. For reference, each configuration of the phase locked loop 200 according to the first embodiment may be implemented by at least one of a circuit, a processor, and a combination of a circuit and a processor. In addition, the phase locked loop 200 according to the first embodiment can be manufactured as a single semiconductor chip.

The phase frequency detection unit 210 receives the input signal FIN and the divided output signal FDIV, compares the frequency of the input signal FIN and the frequency of the divided output signal FDIV, and generates an up/down signal. Creates (UP, DOWN). Here, the input signal FIN is a signal input from outside the phase locked loop 200. The control voltage generator 220 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL).

The voltage controlled oscillator 230 receives the control voltage VCTRL and generates the voltage controlled oscillator output signal FOUT. Here, the voltage-controlled oscillator output signal (FOUT) becomes an output clock signal output from the phase-locked loop 200.

The frequency divider 240 divides the voltage control oscillator output signal (FOUT) to generate the divided output signal (FDIV). In other words, a divided output signal (FDIV) is generated having a frequency divided by the frequency of the output signal (FOUT) of the voltage control oscillator by the dividing ratio (N). Here, N is a natural number greater than or equal to 2.

In addition, the gain adjuster 250 serves to generate a first control signal (CKVCO[1:0]) to control the operation of the voltage controlled oscillator 230.

3 and 4 are configuration diagrams of the gain adjustment unit 250 according to the first embodiment.

As can be seen from FIG. 3, the gain adjustment unit 250 may be configured to include a multi-bit flash analog-to-digital converter 251, and may receive a control voltage (VCTRL) and generate a multi-bit first control signal (VCTRL). CKVCO[1:0]) can be created. In the embodiment of the present invention, for convenience, multi-bit is assumed to be 2 bits.

Specifically, the control voltage generator 220 includes a charge pump 221 and a loop filter 222. Since the charge pump 221 additionally charges or discharges an amount of charge equal to the difference between the up/down signals (UP, DOWN), a current gain (Ip) exists in the process of converting the pulse to current, and this current gain (Ip) affects the performance of the phase locked loop 200, including lock time. In addition, the loop filter 222 is composed of a low-pass filter structure, filters noise containing harmonic output components generated during operation, and controls the voltage control oscillator 230 through changes in the amount of charge accumulated using a capacitor. Outputs control voltage (VCTRL).

That is, the control voltage generator 220 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL) from which noise has been removed.

Specifically, the voltage controlled oscillator 230 includes a voltage buffer 231 and a voltage controlled oscillator 233.

The voltage buffer 231 is a first driving voltage (VCP) and a second driving voltage ( Create a VCN).

Figure 4 shows a configuration diagram of the multiplexer 252 included in the gain adjustment unit 250 according to the first embodiment.

The multiplexer 252 may include a first multiplexer 252a and a second multiplexer 252b. In addition, the first multiplexer 252a and the second multiplexer 252b may be configured to include switches SW1 and SW2, respectively.

The first multiplexer 252a receives the first driving voltage (VCP) and the first control signal (CKVCO[1:0]) and outputs the 1-1 gain control signal to the 1-M gain control signal (C11, C12). , C13, C14) are output. Specifically, the first multiplexer 252a controls one of the 1-1 gain control signals to the 1-M gain control signals (C11, C12, C13, and C14) according to the first control signal (CKVCO[1:0]). At least some of the selected ones are output at the same voltage level as the first driving voltage (VCP), and the remaining ones that are not selected among the 1-1 gain control signal to the 1-M gain control signal (C11, C12, C13, and C14) are output at the same voltage level as the first driving voltage (VCP). Output in high state. That is, the P-MOS transistor of the delay cell included in the voltage control oscillator 233 by the first multiplexer 252a operates in the on state when a voltage equal to the first driving voltage VCP is applied, When a high state voltage is applied, it operates in an off state.

Likewise, the second multiplexer 252b receives the second driving voltage (VCN) and the first control signal (CKVCO[1:0]) and outputs the 2-1 gain control signal to the 2-M gain control signal (C21). , C22, C23, C24) are output. The second multiplexer 252b controls at least a portion selected from the 2-1 gain control signal to the 2-M gain control signal (C21, C22, C23, C24) according to the first control signal (CKVCO[1:0]). Outputs the same voltage as the second driving voltage (VCN), and the remaining ones that are not selected among the 2-1 gain control signal to the 2-M gain control signal (C21, C22, C23, C24) are in a low state. Print out. That is, the N-MOS transistor included in the delay cell of the voltage controlled oscillator 233 by the second multiplexer 252b operates in the on state when a voltage equal to the second driving voltage VCN is applied, When a low voltage is applied, it operates in an off state.

For reference, in FIG. 4, M is illustrated as 4, but M may be a natural number of 2 or more.

Figure 5 shows a configuration diagram of the voltage controlled oscillator 233 according to the first embodiment.

As can be seen from FIG. 5, the voltage controlled oscillator 233 according to the first embodiment is configured to include a plurality of delay cells 233a.

Each delay cell 233a may use a current starved inverter structure. In addition, the current flowing in each delay cell 233a is the 1-1st gain control signal to the 1-M gain control signal (C11, C12, C13, C14) and the 2-1st gain control signal to the 2-th gain control signal. It is controlled by the M gain control signal (C21, C22, C23, C24).

That is, when the multiplexer 232 outputs the 1-K gain control signal at the same voltage as the first driving voltage (VCP) by the first control signal (CKVCO[1:0]), the 2-K gain The control signal is output at the same voltage as the second driving voltage (VCN). Here, the 1-K gain control signal and the 2-K gain control signal are each connected to the gate terminal of the P-MS transistor located on one current path in each delay cell 233a included in the voltage controlled oscillator 233. and is input to the gate terminal of the N-MOS transistor. Here, K is a natural number greater than or equal to 1 and less than or equal to M.

That is, the 1-K gain control signal and the 2-K gain control signal are one pair, and turn on or turn off both the P-MOS transistor and the N-MOS transistor located on one current path. I order it.

If the same voltage as the first driving voltage (VCP) is output to the 1-1 gain control signal to the 1-M gain control signal (C11, C12, C13, C14), and the 2-1 gain control signal to the second When the same voltage as the second driving voltage VCP is output through the -M gain control signals C21, C22, C23, and C24, the current flowing in the delay cell 233a will be the largest.

As can be seen from the above description of the phase locked loop 200 according to the first embodiment, the voltage control oscillator output signal ( Kvco, which is the ratio of the frequencies of FOUT), is controlled.

The transfer function and loop bandwidth of the phase locked loop 200 according to the first embodiment can also be expressed as [Equation 1] and [Equation 3] in [Background Technology of the Invention].

As can be seen from [Equation 3], the phase locked loop 200 according to the first embodiment adjusts Kvco to adjust the value of the loop bandwidth to 1/10 to 1/ of the input signal FIN, which is an input signal. Easy to maintain in size 20.

FIG. 6 shows a graph of the input signal FIN according to the control voltage VCTRL of the phase locked loop 200 according to the first embodiment.

In the phase locked loop 200 according to the first embodiment, the Kvco value of the voltage controlled oscillator 233 is adjusted to the input signal (FIN) by the first control signal (CKVCO[1:0]) of the gain adjuster 250. It is adjusted according to the control voltage (VCTRL), which is proportional to .

When the phase locked loop 200 starts operating, the phase locked loop 200 is first locked in the case where the Kvco value is the largest, and in the locked state, the Kvco value is changed using the control voltage (VCTRL). Then, the locking operation of the phase lock loop 200 is performed again according to the changed Kvco value. In addition, when the control voltage (VCTRL) reaches an appropriate value in accordance with the input signal (FIN), the Kvco value is fixed, and the phase-locked loop 200 is locked according to the fixed Kvco value to operate the normal phase-locked loop 200. This goes on.

In general, the division ratio, which is the ratio of the loop bandwidth of the phase locked loop 100 and the input clock, changes according to the change of the input clock for changing the output in the phase locked loop 100. However, according to the phase locked loop 200 according to the first embodiment, when the Kvco value is changed, the loop bandwidth is changed so that the division rate according to the changed input clock can be kept constant.

Figure 7 shows a configuration diagram of the phase locked loop 300 according to the second embodiment.

As can be seen from FIG. 7, the phase locked loop 300 according to the second embodiment includes a phase frequency detector 310, a control voltage generator 320, a voltage control oscillator 330, and a frequency divider 340. and a selector 350. For reference, each configuration of the phase locked loop 300 according to the second embodiment may be implemented by at least one of a circuit, a processor, and a combination of a circuit and a processor. In addition, the phase locked loop 300 according to the second embodiment can be manufactured as a single semiconductor chip.

It goes without saying that the phase locked loop 300 according to the second embodiment includes all the features of the phase locked loop 200 according to the first embodiment, unless otherwise described. That is, if each part of the phase locked loop 300 according to the second embodiment has the same name as each part of the phase locked loop 200 according to the first embodiment, unless otherwise specified, each part has the same name. The parts may be configured identically to each other.

The phase frequency detection unit 310 receives the input signal FIN and the divided output signal FDIV, compares the frequency of the input signal FIN and the frequency of the divided output signal FDIV, and generates an up/down signal. Creates (UP, DOWN). Here, the input signal FIN is a signal input from outside the phase locked loop 300. The control voltage generator 320 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL).

The control voltage generator 320 includes a charge pump 321 and a loop filter 322. The charge pump 321 additionally charges or discharges an amount of charge equal to the difference between the up/down signals (UP, DOWN), so a current gain (Ip) exists in the process of converting the pulse to current, and this current gain ( Ip) affects the performance of the phase locked loop 300, including lock time. In addition, the loop filter 322 may be configured as a low-pass filter structure and filters noise containing harmonic output components generated during operation. Additionally, a control voltage (VCTRL) that controls the voltage control oscillator 330 is output through changes in the amount of charge accumulated using a capacitor.

That is, the control voltage generator 320 receives up/down signals (UP, DOWN) and generates a control voltage (VCTRL) from which noise has been removed.

The voltage controlled oscillator 330 includes a voltage buffer 331 and a voltage controlled oscillator (VCO, 333). The voltage buffer 331 generates VCP and VCN, which are first and second driving voltages, from the control voltage VCTRL to supply a power voltage to the ring oscillator of the delay cell included in the voltage controlled oscillator 333. The voltage buffer 331 may generate the above-described gain adjustment signals (C11 to C14, C21 to C24). The oscillation frequency of the ring oscillator can be changed by these signals. The time delay of the delay cell constituting the voltage control oscillator (VCO, 333) is controlled by various signals transmitted from the voltage buffer 331. As a result, the frequency of the voltage-controlled oscillator output signal (FOUT) is controlled.

The voltage controlled oscillator 333 according to the second embodiment is configured to include a plurality of delay cells (not shown). That is, the voltage-controlled oscillator 333 according to the second embodiment may be composed of the same circuit as the voltage-controlled oscillator 233 according to the first embodiment and the circuit operation may also be the same.

The frequency divider 340 divides the voltage control oscillator output signal (FOUT) to generate the divided output signal (FDIV). In other words, a divided output signal (FDIV) is generated having a frequency divided by the frequency of the output signal (FOUT) of the voltage control oscillator by the dividing ratio (N). Here, N is a natural number greater than or equal to 2. At this time, the division rate can be selectively varied by the output signals of the selector 350.

The selector 332 may be configured to include an appropriate logic circuit as shown in FIG. 8. In addition, the selector 350 receives at least one external input signal or at least one preset signal and provides a division selection signal SCODE[1:0] and a mode selection signal to control the operation of the frequency divider 340. Outputs MODE_8 and MODE_2 signals. These signals may be generated by a combination of logic circuits constituting the selector 350, as illustrated in FIG. 8.

Therefore, the second embodiment of the present invention illustrated in FIGS. 7 and 8, unlike the first embodiment where the gain of the voltage controlled oscillator 333 is adjusted, changes the division ratio by the selector 350. This is the method by which the phase locked loop 300 is controlled.

Figure 8 is a configuration diagram of the selector 350 according to the second embodiment.

8, the selector 350 according to the second embodiment will be described in more detail.

The input signal F_SEL[1:0] of the selector 350 consists of 2 bits and is used to selectively divide the frequency. Another input signal S2 of the selector 350 may be a process correction signal for correcting changes in the manufacturing process of the phase locked loop 300. That is, changes due to the process can be corrected by varying the value of the process correction signal S2 according to process conditions when manufacturing a semiconductor chip including the phase locked loop 300.

The selector 350 outputs various division selection signals SCODE[1:0] and mode selection signals MODE_8 and MODE_2 so that an appropriate division ratio can be selected according to the logical combination of the two input signals.

The frequency divider 340 divides the output for the frequency of the voltage control oscillator output signal (FOUT) by the division selection signal SCODE[1:0] and the mode selection signal MODE_8 and MODE_2 signals output from the selector 350. The division rate N, which is the ratio of the frequency of the signal (FDIV), is selectively controlled.

Figure 9 is an example setting according to the process correction signal (S2) and the selection signal (S1).

In FIG. 9, 'corner' refers to the semiconductor process conditions, and it can be seen that the process correction signal (S2) is set according to the semiconductor process conditions. The process correction signal may be set auxiliary to the selection signal (F_SEL[1:0]). In addition, as shown in FIG. 9, according to the selection signal (F_SEL[1:0]), the division ratio N value, which is the ratio of the frequency of the divided output signal (FDIV) to the frequency of the voltage control oscillator output signal (FOUT), can be controlled. You can.

In the phase locked loop 300 according to the second embodiment, the first control signal (CKVCO[1:0]) is changed in accordance with the selection signal (F_SEL[1:0]), and the first control signal (CKVCO As the value of [1:0]) increases, the gain of the voltage-controlled oscillator can be controlled by increasing the current flowing in the delay cell.

Figure 10 shows a flowchart of a method of operating the phase locked loop 200 according to the first embodiment. Since the method of operating the phase locked loop 200 according to the first embodiment uses the phase locked loop 200 according to the first embodiment, unless otherwise stated, the phase locked loop 200 according to the first embodiment is used. ), of course, includes all of the features.

As can be seen from FIG. 10, the method of operating the phase locked loop 200 according to the first embodiment is to receive the input signal FIN and the divided output signal FDIV, and adjust the frequency of the input signal FIN. Comparing the frequencies of the divided output signal (FDIV) and generating up/down signals (UP, DOWN) (S110); Step (S120) of receiving up/down signals (UP, DOWN) and generating a control voltage (VCTRL); Step (S125) of receiving the control voltage (VCTRL) and generating gain adjustment signals (C12 to C14, C21 to C24); Generating an output signal (FOUT) of the voltage control oscillator in response to the driving voltages (VCN, VCP) and gain control signals (C12 to C14, C21 to C24) (S130); Generating a divided output signal (FDIV) by dividing the voltage control oscillator output signal (FOUT) (S140); and a step (S150) of receiving a control voltage (VCTRL) for controlling the operation of step S130 and generating driving voltages (VCP, VCN).

In step S130, Kvco, which is the ratio of the frequency of the voltage control oscillator output signal (FOUT) to the control voltage (VCTRL), is controlled by the first control signal (CKVCO[1:0]).

Specifically, step S150 receives the control voltage (VCTRL) and generates a first control signal (CKVCO[1:0]).

In addition, step S130 is a step of receiving the control voltage (VCTRL) and generating a first driving voltage (VCP) for driving the P-MOS transistor and a second driving voltage (VCN) for driving the N-MOS transistor ( S131); Receives the first driving voltage (VCP) and the first control signal (CKVCO[1:0]) and outputs the 1-1 gain control signal to the 1-M gain control signal (C11, C12, C13, C14) , receives the second driving voltage (VCN) and the first control signal (CKVCO[1:0]) and outputs the 2-1 gain control signal to the 2-M gain control signal (C21, C22, C23, C24) Step (S132); and generating a voltage-controlled oscillator output signal (FOUT) by a circuit including a plurality of delay cells (S133). Here, M is a natural number of 2 or more.

Specifically, in step S132, at least some of the 1-1 gain adjustment signal to the 1-M gain adjustment signal (C11, C12, C13, C14) are adjusted according to the first control signal (CKVCO[1:0]). 1 Outputs the same voltage as the driving voltage (VCP), and outputs the 2-1st gain control signal to the 2-M gain control signal (C21, C22, C23) according to the first control signal (CKVCO[1:0]). , C24) outputs at the same voltage level as the second driving voltage VCN.

In addition, each of the plurality of delay cells has a 1-1 gain control signal to a 1-M gain control signal (C11, C12, C13, C14) and a 2-1 gain control signal to a 2-M gain control signal ( The flowing current is controlled by C21, C22, C23, and C24). Additionally, in step S132, when the 1-K gain control signal is output at the same voltage as the first driving voltage (VCP), the 2-K gain control signal is output at the same voltage as the second driving voltage (VCN). . Here, the 1-K gain control signal and the 2-K gain control signal are input to the gate terminal of the P-MOS transistor and the gate terminal of the N-MOS transistor, respectively, located on one current path in each of the plurality of delay cells. do. Here, K is a natural number greater than or equal to 1 and less than or equal to M.

Figure 11 shows a flowchart of a method of operating the phase locked loop 200 according to the second embodiment. Since the method of operating the phase locked loop 300 according to the second embodiment uses the phase locked loop 300 according to the second embodiment, unless otherwise specified, the phase locked loop 300 according to the second embodiment is used. ), of course, includes all of the features.

As can be seen from FIG. 11, the method of operating the phase locked loop 300 according to the second embodiment is to receive the input signal FIN and the divided output signal FDIV, and adjust the frequency of the input signal FIN. Comparing the frequencies of the divided output signal (FDIV) and generating up/down signals (UP, DOWN) (S210); Step (S220) of receiving up/down signals (UP, DOWN) and generating a control voltage (VCTRL); A step (S230) of receiving a control voltage (VCTRL) and generating driving signals (VCN, VCP) and gain adjustment signals (C11 to C24) of the power voltage of the voltage control oscillator; Generating an output signal (FOUT) of the voltage controlled oscillator using the driving signals (VCN, VCP) and gain control signals (C11 to C24) (S235); Generating a divided signal (FDIV) by dividing the output frequency (FOUT) of the voltage control oscillator at a division rate determined by the frequency mode selection signals (MODE_8...) (S240); and generating a frequency selection signal and a mode selection signal (MODE_8, MODE_2) using the frequency selection signal (F_SEL) and the manufacturing process variable signal (S2) (S250).

Specifically, step S250 receives at least one external input signal or at least one preset signal and generates a first control signal (CKVCO[1:0]) and other control signals.

In addition, step S230 is a first driving voltage (VCP) for driving the P-MOS transistor of the ring oscillator constituting the voltage control oscillator by receiving the control voltage (VCTRL) and a second driving voltage (VCP) for driving the N-MOS transistor. Generating a driving voltage (VCN) (S231); Receives the first driving voltage (VCP) and the first control signal (CKVCO[1:0]) and outputs the 1-1 gain control signal to the 1-M gain control signal (C11, C12, C13, C14) , receives the second driving voltage (VCN) and the first control signal (CKVCO[1:0]) and outputs the 2-1 gain control signal to the 2-M gain control signal (C21, C22, C23, C24) Step (S232); and generating a voltage-controlled oscillator output signal (FOUT) by a circuit including a plurality of delay cells (S233). Here, M is a natural number of 2 or more.

Specifically, in step S232, at least some of the 1-1 gain adjustment signal to the 1-M gain adjustment signal (C11, C12, C13, C14) are adjusted according to the first control signal (CKVCO[1:0]). 1 Outputs the same voltage as the driving voltage (VCP), and outputs the 2-1st gain control signal to the 2-M gain control signal (C21, C22, C23) according to the first control signal (CKVCO[1:0]). , C24) outputs at the same voltage level as the second driving voltage VCN.

In addition, each of the plurality of delay cells has a 1-1 gain control signal to a 1-M gain control signal (C11, C12, C13, C14) and a 2-1 gain control signal to a 2-M gain control signal ( The flowing current is controlled by C21, C22, C23, and C24). Additionally, in step S132, when the 1-K gain control signal is output at the same voltage as the first driving voltage (VCP), the 2-K gain control signal is output at the same voltage as the second driving voltage (VCN). . Here, the 1-K gain control signal and the 2-K gain control signal are input to the gate terminal of the P-MOS transistor and the gate terminal of the N-MOS transistor, respectively, located on one current path in each of the plurality of delay cells. do. Here, K is a natural number greater than or equal to 1 and less than or equal to M.

At least one of the at least one external input signal or at least one preset signal in step S250 is a process correction signal S2 for correcting changes in the manufacturing process of the phase locked loop 300.

In addition, step S250 includes a process correction signal (S2); Alternatively, the first control signal (CKVCO[1:0]) is generated by a selection signal (S1) that is at least another one of at least one external input signal or at least one preset signal. In addition, step S250 generates a second control signal (CON2) based on the selection signal (S1). In step S240, the ratio of the frequency of the divided output signal (FDIV) to the frequency of the voltage control oscillator output signal (FOUT) is controlled by the second control signal (CON2).

As described above, according to the phase locked loops 200 and 300 of the present invention and the operation method of the phase locked loop, the bandwidth can be adaptively adjusted by adjusting Kvco, which is the gain of the voltage controlled oscillators 233 and 333. You can see that there is.

100, 200, 300: Phase locked loop (PLL)
110, 210, 310: Phase frequency detection unit (PFD)
120, 220, 320: Control voltage generator
130, 230, 330: Voltage control oscillator
140, 240, 340: Frequency divider
250: gain control unit 350: selector
121, 221, 321: Charge pump
122, 222, 322: Loop filter
131, 231, 331: Voltage buffer
232: multiplexer
133, 233, 333: Voltage controlled oscillator

Claims (18)

A phase and frequency detection unit that detects the phase and frequency of the input signal;
a control voltage generator including a charge pump that responds to the up/down output signals of the phase and frequency detector;
Voltage controlled oscillator;
a gain adjuster connected to the output of the control voltage generator (VCTRL) to adjust the gain of the voltage controlled oscillator (VCO);
A phase locked loop comprising a frequency divider that converts the output signal of the voltage controlled oscillator into a divided signal. The control voltage generator of claim 1, wherein
A phase locked loop comprising a loop filter consisting of a combination of a resistor and a capacitor. The method of claim 1, wherein the phase frequency detection unit,
A phase-locked loop, characterized in that the operation corresponds to the difference between the input signal and the divided signal. The gain control unit of claim 1,
A phase-locked loop comprising an analog-to-digital converter and one or more multiplexers. The analog-to-digital converter of claim 4,
A phase-locked loop characterized as a flash type that generates a digital code of at least 2 bits. According to clause 1,
A phase locked loop, characterized in that the voltage control oscillator includes a voltage buffer. The method of claim 1, wherein the voltage controlled oscillator,
A phase-locked loop characterized in that one or more delay cells are connected in series to form a ring. A phase and frequency detection unit that detects the phase and frequency of the input signal;
a control voltage generator including a charge pump that responds to the up/down signals output from the phase and frequency detector;
Voltage controlled oscillator;
a frequency divider that converts the output signal of the voltage controlled oscillator into a divided signal;
A selector that generates a control voltage to adjust the voltage gain of the voltage control oscillator according to the division ratio of the frequency divider. The method of claim 8, wherein the selector is:
A phase-locked loop characterized in that one or more variables representing changes in the manufacturing process are input. The method of claim 8, wherein the selector is:
A phase-locked loop characterized by consisting of a combination of logic circuits. Comparing the frequency of the input signal and the frequency of the divided output signal to generate up/down signals;
receiving the up/down signals and generating a control voltage;
receiving the control voltage and generating gain adjustment signals;
generating an output signal of a voltage controlled oscillator responsive to the driving voltages and gain control signals;
dividing the output signal of the voltage controlled oscillator to generate a divided output signal; and
A method of operating a phase locked loop comprising: receiving the control voltage and generating the driving voltages (S150). Generating up/down signals by comparing the frequency of the input signal and the frequency of the divided output signal (S210);
receiving the up/down signals and generating a control voltage (S220);
receiving the control voltage and generating gain adjustment signals using the driving voltages of the power voltage of the voltage control oscillator and the signal generated by the selector (S230);
Generating an output signal of the voltage controlled oscillator using the driving signals and the gain control signals (S235);
Generating mode selection signals and gain adjustment signals using the frequency selection signal and the manufacturing process variable signal (S250); and
generating a divided signal by dividing the output frequency of the voltage-controlled oscillator at a division rate determined by the mode selection signals (S240);
Method of operation of a phase locked loop including. The method of claim 11 or 12, wherein the voltage controlled oscillator,
A method of operating a phase-locked loop, comprising oscillating a ring oscillator. The ring oscillator of claim 11 or 12 included in the voltage controlled oscillator,
A method of operating a phase locked loop, characterized in that it is driven by a driving voltage generated by the control voltage. The ring oscillator of claim 11 or 12 included in the voltage controlled oscillator,
A method of operating a phase-locked loop, characterized in that the oscillation frequency is changed by a gain control signal. The ring oscillator of claim 11 or 12 included in the voltage controlled oscillator,
A method of operating a phase-locked loop, characterized in that one or more delay cells are connected in series to form a ring. The method of claim 11 or 12, wherein generating the control voltage comprises:
A method of operating a phase-locked loop, characterized in that it is achieved by a loop filter consisting of a combination of a resistor and a capacitor. The method of claim 12, wherein step S250,
A method of operating a phase-locked loop, characterized by a combination of logic circuits.