JPH11122101A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the PLL circuit that reduces noise in an output signal while reducing a lockup time. SOLUTION: A phase comparator 1 outputs pulse signals ϕR, ϕP with a pulse width in response to a frequency difference between a reference signal fr and an output signal fvco. A smooth circuit 2 smoothes the pulse signals ϕR, ϕP into a DC voltage and outputs the DC voltage as an output voltage Vrp. A DC amplifier 3 amplifies the output voltage Vrp and outputs an amplified voltage signal Vc. A voltage controlled oscillator 4 outputs the output signal fvco with a frequency based on the voltage of the voltage signal Vc. A gain control means 5 increases a gain of the DC amplifier 3 when the frequency of the output signal fvco is apart from the frequency of a reference signal fr by >= a prescribed frequency and the gain control means 5 decreases the gain of the DC amplifier 3 when the frequency of the output signal fvco is close to the frequency of the reference signal fr by < a prescribed frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL circuit that operates so that the frequency of an output signal matches a desired frequency.

In recent years, PLL circuits have been used in mobile communication devices such as mobile phones and mobile phones. Such a P
The LL circuit is required to reduce the noise of the output signal and reduce the time required for locking the frequency of the output signal to a desired frequency, that is, the so-called lock-up time.

[0003]

FIG. 8 shows a conventional PLL circuit 10. As shown in FIG.
The reference frequency divider 11 outputs to the phase comparator 12 a reference signal fr obtained by dividing a crystal oscillation signal having a natural frequency based on the oscillation of the crystal resonator. The comparison frequency divider 13 outputs to the phase comparator 12 a comparison signal fp obtained by dividing the output signal fvco of a voltage controlled oscillator (hereinafter referred to as VCO) 16. The phase comparator 12 outputs to the charge pump 14 pulse signals φR and φP corresponding to the frequency difference between the reference signal fr and the comparison signal fp.

The charge pump 14 includes a phase comparator 1
The output current SCP is output to a low-pass filter (hereinafter, referred to as LPF) 15 based on the pulse signals φR and φP output from 2. The output current SCP changes according to the phase difference between the pulse signals φR and φP.

The LPF 15 converts a DC voltage obtained by smoothing the output current SCP of the charge pump 14 into an output signal SLPF.
And outputs it to the VCO 16. VCO 16 is the LP
An output signal fvco having a frequency corresponding to the voltage value of the output signal SLPF of F15 is output to an external circuit and to the comparison frequency divider 13.

In the PLL circuit 10 configured as described above, when the frequency of the output signal fvco becomes lower than the desired frequency, the frequency of the comparison signal fp becomes lower than the frequency of the reference signal fr. Then, the phase comparator 12 detects the state shown in FIG.
As shown in (a), the pulse width T1 of the pulse signal φR is made longer and the pulse width T2 of the pulse signal φP is made shorter.

When the pulse width T1 of the pulse signal φR becomes longer and the pulse width T2 of the pulse signal φP becomes shorter, the charge pump 14 supplies an output current SCP to the LPF 15 to increase the voltage value of the output signal SLPF of the LPF 15. . When the voltage value of the output signal SLPF rises, the VCO
16 increases the frequency of the output signal fvco.

When the frequency of the output signal fvco becomes higher than the desired frequency, the frequency of the comparison signal fp becomes higher than the frequency of the reference signal fr. Then, the phase comparator 1
2 shortens the pulse width T1 of the pulse signal φR and increases the pulse width T2 of the pulse signal φP, as shown in FIG.

When the pulse width T1 of the pulse signal φR becomes shorter and the pulse width T2 of the pulse signal φP becomes longer, the charge pump 14 draws the output current SCP from the LPF 15 and lowers the voltage value of the output signal SLPF of the LPF 15. When the voltage value of the output signal SLPF falls, V
The CO 16 lowers the frequency of the output signal fvco.

In the PLL circuit 10, the frequency of the output signal fvco output from the VCO 16 is locked to a desired frequency by repeating such an operation.

Incidentally, in order to shorten the lock-up time of the PLL circuit 10 having the above configuration, for example, the following (1) to (5)
There is a means shown in (4). (1) a reference signal fr output from the reference frequency divider 11;
The frequency of the comparison signal fp output from the comparison frequency divider 13 is set high.

The high-frequency reference signal fr and the comparison signal fp are input to the phase comparator 12. for that reason,
The speed of the comparison operation of the phase comparator 12 is increased. As a result, the frequency of the pulse signals φR and φP increases, and the response speed of the output current SCP of the charge pump 14 to changes in the reference signal fr and the comparison signal fp improves.

(2) Output current SC of charge pump 14
The current value of P is set to be large. The LPF 15 provided at the next stage of the charge pump 14 is configured by a CR (capacitance / resistance) integration circuit. Therefore, when the current value of the output current SCP of the charge pump 14 is increased, the time for charging up (charging) the capacitance of the integration circuit is reduced. As a result, the response speed of the output signal SLPF of the LPF 15 to changes in the reference signal fr and the comparison signal fp is improved.

(3) The time constant of the LPF 15 is set small. The LPF 15 has a CR (capacitance / resistance) as described above.
It is composed of an integrating circuit. Therefore, when the time constant of the LPF 15 is set to be small, the charge-up (charging) time of the capacitance of the integration circuit is shortened as described above. as a result,
LPF1 for changes in reference signal fr and comparison signal fp
5 improves the response speed of the output signal SLPF.

(4) A VCO 16 having a high frequency conversion gain is used. The VCO 16 outputs an output signal fvco having a frequency corresponding to the voltage value of the output signal SLPF of the LPF 15. Therefore, the VCO 16 having a high frequency conversion gain
Is used, the ratio of the change in the frequency of the output signal fvco to the change in the voltage value of the output signal SLPF increases. As a result, VC with respect to a change in the voltage value of output signal SLPF
The response speed of the output signal fvco of O16 is improved.

Therefore, the frequency of the output signal fvco of the VCO 16 can be quickly brought close to a desired frequency by using any of the above-mentioned means (1) to (4), and thus the PLL is used.
The lock-up time of the circuit 10 can be reduced.

[0017]

However, the above (1)
In any of the means (4) to (4), the lock-up time can be reduced, but there is a problem in that noise is generated in the output signal fvco because each output signal changes excessively.

Therefore, in general, in order to reduce noise, the current value of the output current SCP of the charge pump 14 is set to be small, the time constant of the LPF 15 is set to be large, or the gain of the VCO 16 is reduced. However, these conflict with the above-mentioned means (2) to (4), so that the lock-up time of the PLL circuit 10 becomes long.

Therefore, in the above-described conventional PLL circuit 10, it is difficult to achieve both a reduction in lock-up time and a reduction in noise. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL circuit capable of reducing output signal noise while shortening a lock-up time.

[0020]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the phase comparator 1 compares the frequency of the reference signal fr with the frequency of the output signal fvco, and outputs pulse signals φR and φP having a pulse width corresponding to the frequency difference. The smoothing circuit 2 smoothes the pulse signals φR and φP of the phase comparator 1 and converts them into a DC voltage, and outputs the DC voltage as an output voltage Vrp. The DC amplifier 3 receives the output voltage Vrp of the smoothing circuit 2 and outputs a voltage signal Vc obtained by amplifying the output voltage Vrp. The voltage controlled oscillator 4 outputs the output signal fvco having a frequency based on the voltage value of the voltage signal Vc of the DC amplifier 3. The gain control means 5
When the frequency of the output signal fvco of the voltage controlled oscillator 4 is separated from the frequency of the reference signal fr by a predetermined value or more, the gain of the DC amplifier 3 is increased, and the frequency of the output signal fvco is changed to the reference signal fr. When the frequency approaches the frequency fr, the gain of the DC amplifier 3 is reduced.

According to a second aspect of the present invention, the phase comparator is configured to output two pulse signals each having a pulse width corresponding to a frequency difference between a reference signal and an output signal,
The smoothing circuit is configured to smooth each of the pulse signals of the phase comparator and convert the pulse signal to a DC voltage, and output the DC voltage as an output voltage, respectively, and the DC amplifier converts an output voltage of the smoothing circuit to an output voltage. It is configured by a differential operational amplifier that inputs each and outputs a voltage signal obtained by amplifying a potential difference of each output voltage.

According to a third aspect of the present invention, the gain control means obtains a phase difference between the pulse signals of the phase comparator,
A determination detection circuit that determines whether the obtained phase difference is equal to or greater than a predetermined value or less than a predetermined value, and outputs a determination signal thereof,
Based on a determination signal that the phase difference is determined to be equal to or greater than a predetermined value in the determination detection circuit, a gain control signal for increasing the gain of the operation operational amplifier is output to the operation operational amplifier, and the phase difference is determined by the determination detection circuit. And a gain control circuit for outputting a gain control signal for lowering the gain of the operational operational amplifier to the operational operational amplifier based on the determination signal determined to be less than the predetermined value.

(Operation) Therefore, according to the first and second aspects of the present invention, when the frequency of the output signal is separated from the frequency of the reference signal, the direct current amplifier (differential operational amplifier) is controlled by the gain control means. Is operated so that the frequency of the output signal quickly matches the desired frequency. Therefore, the lock-up time can be reduced. In addition, when the frequency of the output signal is close to the frequency of the reference signal, the gain of the DC amplifier (differential operational amplifier) is reduced by the gain control means, and the frequency of the output signal gradually rises near the desired frequency. It works to change. Therefore, since an excessive change of the output signal is suppressed,
Noise of the output signal can be reduced.

According to the third aspect of the present invention, the determination detection circuit determines the phase difference between the respective pulse signals of the phase comparator and determines whether the obtained phase difference is equal to or greater than a predetermined value or less than the predetermined value. I do. The gain control circuit controls the gain of the differential operational amplifier based on the determination. Therefore, the determination and the gain control can be performed reliably and easily.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, the same components as those in the related art shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 2 shows a PLL circuit 20 according to the present embodiment. This PLL circuit 20 is a conventional PLL circuit shown in FIG.
The charge pump 14 and the LPF 15 of the circuit 10 include integration circuits 21a and 21b, an operational amplifier 22, a detection circuit 23,
And a gain control circuit 24.

The pulse signals φR and φP from the phase comparator 12 are input to the integration circuits 21a and 21b, respectively. The integration circuits 21a and 21b are composed of CR (capacitance / resistance) integration circuits, and their time constants are set to be sufficiently larger than the pulse widths of the pulse signals φR and φP from the phase comparator 12. Then, the integration circuits 21a and 21b output the voltage signals obtained by smoothing the pulse signals φR and φP to the respective input terminals of the operational amplifier 22 as output voltages Vr and Vp.

The operational amplifier 22 is a variable operational amplifier of a variable gain type. The operational amplifier 22 outputs a voltage signal corresponding to the potential difference between the input output voltages Vr and Vp to the VCO 16 as an output signal Vc. VCO16
Outputs an output signal fvco having a frequency corresponding to the voltage value of the output signal Vc. The gain of the operational amplifier 22 is controlled by a detection circuit 23 and a gain control circuit 24.

The detection circuit 23 receives the pulse signals φR and φP from the phase comparator 12, and the detection circuit 23 detects a phase difference between the pulse signals φR and φP. Where VCO
The more the frequency of the 16 output signal fvco deviates from the desired frequency, the greater the phase difference between the pulse signals φR and φP becomes.
It is determined that the frequency of the output signal fvco is separated from the desired frequency by a predetermined value or more, and the H-level control signal C
NT is output to the gain control circuit 24.

As the frequency of the output signal fvco of the VCO 16 approaches the desired frequency, the pulse signals φR, φR
When the phase difference of P becomes small and the phase difference becomes smaller than a predetermined value, the detection circuit 23 determines that the frequency of the output signal fvco is closer to the desired frequency and is smaller than the predetermined value, and the L-level control signal CNT To the gain control circuit 24.

The gain control circuit 24 outputs a control voltage VCNT for changing the gain to the operational amplifier 22 based on the control signal CNT output from the detection circuit 23.

That is, the H-level control signal CNT
Is input, the gain control circuit 24 outputs an H level control voltage VCNT, and the operational amplifier 22
To increase the gain. Therefore, the ratio of the change of the output signal Vc of the operational amplifier 22 to the change of the output voltages Vr and Vp increases.

The control signal CNT of L level
Is input, the gain control circuit 24 outputs an L level control voltage VCNT, and the operational amplifier 22
To lower the gain. Therefore, the ratio of the change of the output signal Vc of the operational amplifier 22 to the change of the output voltages Vr and Vp becomes small.

FIG. 3 shows a specific configuration of the detection circuit 23. Pulse signals φR, φP from the phase comparator 12
Is input to the EOR circuit 31. The output signal SG of the EOR circuit 31 is input as data D to the preceding flip-flop FF1 of the synchronous counter 32 having a three-stage configuration. The reference clock signal CK is input to the flip-flop circuits FF1 to FF3.

The flip-flop circuits FF1 to FF3
Are output to the NAND circuit 33. N
The output signal of the AND circuit 33 is inverted via the inverter circuit 34 and output as the control signal CNT.

The detection circuit 23 thus configured outputs the output signal SG in which the phase difference between the pulse signals φR and φP is H level.
Is input to the synchronous counter 32. And FIG.
As shown in FIG. 7, when the reference clock signal CK rises three times after the output signal SG goes high, both the output signals Q of the flip-flop circuits FF1 to FF3 become high.
Level, and the control signal CNT is at H level until the next reference clock signal CK rises.

FIG. 5 shows a specific configuration of the gain control circuit 24. A terminal TCNT to which the control signal CNT is input is connected to a power supply VCC as a high-potential-side power supply via a resistor R1, and an NPN transistor (hereinafter simply referred to as a transistor) via a resistor R2.
Connected to the emitter of Tr1. The collector and the base of the transistor Tr1 are connected to a power supply VCC via a resistor R3.

The transistor Tr2 has a collector connected to a resistor R4.
Is connected to a power supply VCC, and the emitter is connected to a ground GND as a low-potential-side power supply via a transistor Tr11 and a resistor R5. An activation signal VCS supplied from the outside is input to the base of the transistor Tr11, and the transistor Tr11 is normally kept on. Also, the transistor T
The base of r2 is connected to the power supply VCC via the resistor R3.

The transistor Tr3 has a collector connected to a resistor R6.
And the emitter is connected to the ground GND via the transistor Tr12 and the resistor R7. The activation signal VCS is input to the base of the transistor Tr12, and is normally kept on. Also,
An externally supplied constant voltage signal VBIAS is input to the base of the transistor Tr3. And the transistor T
A resistor R is connected between the emitter of the transistor Tr2 and the emitter of the transistor Tr2.
8 are interposed.

The transistor Tr4 has a collector connected to the power supply VCC.
And the emitter is a transistor Tr13 and a resistor R
9 to the ground GND. The activation signal VCS is input to the base of the transistor Tr13, and the transistor Tr13 is normally kept on. Also, the transistor T
The base of r4 is connected to the power supply VCC via the resistor R6. Then, the control voltage VCNT is output from the emitter of the transistor Tr4.

In the thus configured gain control circuit 24, when the control signal CNT from the detection circuit 23 goes from L level to H level (VCC level), the potential of the terminal TCNT goes to H level. Then, since the potential difference between the base and the emitter of the transistor Tr1 becomes smaller, the collector current I1 of the transistor Tr1 decreases, and the base potential of the transistor Tr2 increases.

The base potential of the transistor Tr2 rises,
Eventually, the constant voltage signal VBIAS supplied to the transistor Tr3
, The collector current I3 of the transistor Tr3 becomes smaller than the collector current I2 of the transistor Tr2. Then, the base potential of the transistor Tr4 increases, and the collector current I4 of the transistor Tr4 increases. When the collector current I4 of the transistor Tr4 increases, the control voltage VCNT increases.

When the control signal CNT from the detection circuit 23 changes from H level to L level, the terminal T
The potential of CNT becomes L level. Then, the transistor T
Since the potential difference between the base and the emitter of r1 increases, the collector current I1 of the transistor Tr1 increases,
The base potential of the transistor Tr2 drops.

The base potential of the transistor Tr2 drops,
Eventually, the constant voltage signal VBIAS supplied to the transistor Tr3
, The collector current I3 of the transistor Tr3 becomes larger than the collector current I2 of the transistor Tr2. Then, the base potential of the transistor Tr4 decreases, and the collector current I4 of the transistor Tr4 decreases. When the collector current I4 of the transistor Tr4 decreases, the control voltage VCNT decreases.

FIG. 6 shows a specific configuration of the operational amplifier 22. The collectors of the transistors Tr5 and Tr6 are connected to the power supply VCC via the resistors R10 and R11, respectively. Node N between the collector of transistor Tr5 and resistor R10
1 is connected to the ground GND via the capacitor C. The emitter of the transistor Tr5 is connected to the resistors R12 and R1.
3 is connected to the emitter of the transistor Tr6.

A node N0 between the resistors R12 and R13
Is connected to the ground GND via the variable current source 35. The control voltage VCNT from the gain control circuit 24 is input to the variable current source 35.
When the control voltage VCNT rises, the variable current source 35 increases the activation current I5, and the control voltage VCN
When T decreases, the activation current I5 decreases.

The output voltage Vr from the integration circuit 21a is input to the base of the transistor Tr5, and the output voltage Vp from the integration circuit 21b is input to the base of the transistor Tr6. The output signal Vc is output from a node N2 between the collector of the transistor Tr6 and the resistor R12.

In the operational amplifier 22 configured as described above, when the voltage value of the output voltage Vr becomes higher than the voltage value of the output voltage Vp, the collector current I5 of the transistor Tr5 increases and the collector current I6 of the transistor Tr6 decreases. Then, the potential of the node N2 rises, that is, the output signal V
The voltage value of c increases.

The output voltage Vr is equal to the output voltage Vr.
When the voltage becomes lower than the voltage value of p, the collector current I5 of the transistor Tr5 decreases and the collector current I6 of the transistor Tr6 increases. Then, the potential of the node N2 decreases, that is, the voltage value of the output signal Vc decreases. Note that the voltage value of the output signal Vc changes in proportion to the potential difference between the output voltages Vr and Vp.

Here, when the control voltage VCNT rises, the variable current source 35 increases the activation current I5. Therefore, the change in the collector currents I5 and I6 of the transistors Tr5 and Tr6 based on the change in the output voltages Vr and Vp is reduced. growing. Therefore, the output signal Vc output from the node N2
Becomes large.

When the control voltage VCNT drops, the variable current source 35 decreases the activation current I5, so that the change in the collector currents I5 and I6 of the transistors Tr5 and Tr6 based on the change in the output voltages Vr and Vp is small. Become. Therefore, the amplitude of the output signal Vc output from the node N2 decreases.

Next, the operation of the PLL circuit 20 configured as described above will be described. When the frequency of the output signal fvco of the VCO 16 becomes lower than the desired frequency, the comparison signal f
The frequency of p becomes lower than the frequency of the reference signal fr. As described above, the phase comparator 12 increases the pulse width T1 of the pulse signal φR and shortens the pulse width T2 of the pulse signal φP, as shown in FIG.

Then, the integrating circuits 21a and 21b output the smoothed output voltages V of the pulse signals φR and φP, respectively.
r and Vp are output to each input terminal of the operational amplifier 22. In this case, the voltage value of the output voltage Vr becomes larger than the voltage value of the output voltage Vp, and the operational amplifier 22 outputs the output signal Vc
The voltage value of is increased. When the voltage value of the output signal Vc increases, the VCO 16 increases the frequency of the output signal fvco.

Here, the phase difference between the pulse signals φR and φP becomes an H-level output signal SG in the detection circuit 23 shown in FIGS. After the output signal SG becomes H level, the reference clock signal CK input to the synchronous counter 32 rises three times, that is, when the reference clock signal CK exceeds the predetermined value, the detection is performed until the next reference clock signal CK rises. The circuit 23 has an H level control signal CN.
Output T. That is, the H-level control signal CNT means that the frequency of the output signal fvco of the VCO 16 is separated from the desired frequency.

Then, the H level control signal CN
Based on T, the gain control circuit 24 increases the control voltage VCNT, and increases the gain of the operational amplifier 22. Then, the change of the output signal Vc of the operational amplifier 22 with respect to the change of the output voltages Vr and Vp becomes large. Accordingly, when the frequency of the output signal fvco of the VCO 16 is separated from the desired frequency, the PLL circuit 20 quickly increases the frequency of the output signal fvco.

On the other hand, the phase difference between the pulse signals φR and φP, that is, the output signal SG of H level in the detection circuit 23
However, when the reference clock signal CK input to the synchronous counter 32 falls to L level before rising three times, that is, when the reference clock signal CK is less than the predetermined value, the detection circuit 23 outputs an L level control signal CNT. In other words, this L-level control signal CNT means that the frequency of the output signal fvco of the VCO 16 is close to the desired frequency.

Then, the L-level control signal CN
Based on T, the gain control circuit 24 lowers the control voltage VCNT and lowers the gain of the operational amplifier 22. Then, the change of the output signal Vc of the operational amplifier 22 with respect to the change of the output voltages Vr and Vp becomes small. Therefore, when the frequency of the output signal fvco of the VCO 16 is close to the desired frequency, the PLL circuit 20 gradually increases the frequency of the output signal fvco.

When the frequency of the output signal fvco of the VCO 16 becomes higher than the desired frequency, the frequency of the comparison signal fp becomes higher than the frequency of the reference signal fr. As described above, the phase comparator 12 shortens the pulse width T1 of the pulse signal φR, as shown in FIG.
Is increased.

Then, the integration circuits 21a and 21b output the output voltages V obtained by smoothing the pulse signals φR and φP, respectively.
r and Vp are output to each input terminal of the operational amplifier 22. In this case, the voltage value of the output voltage Vr becomes smaller than the voltage value of the output voltage Vp, and the operational amplifier 22 outputs the output signal Vc
The voltage value of is decreased. Then, when the voltage value of the output signal Vc decreases, the VCO 16 lowers the frequency of the output signal fvco.

Here, the phase difference between the pulse signals φR and φP, that is, the H level output signal SG in the detection circuit 23
When the reference clock signal CK input to the synchronous counter 32 rises three times from the rise, that is, when the reference clock signal CK exceeds the predetermined value, the detection circuit 23 keeps the H level until the next reference clock signal CK rises. Outputs control signal CNT.

Then, in the same manner as described above, the gain control circuit 24 increases the control voltage VCNT and increases the gain of the operational amplifier 22 based on the H-level control signal CNT. Then, the change of the output signal Vc of the operational amplifier 22 with respect to the change of the output voltages Vr and Vp becomes large. Therefore, when the frequency of the output signal fvco of the VCO 16 is separated from the desired frequency, the PLL circuit 20 immediately lowers the frequency of the output signal fvco.

On the other hand, the phase difference between the pulse signals φR and φP, that is, the output signal SG of H level in the detection circuit 23
However, when the reference clock signal CK input to the synchronous counter 32 falls to L level before rising three times, that is, when the reference clock signal CK is less than the predetermined value, the detection circuit 23 outputs an L level control signal CNT.

Then, as described above, the gain control circuit 24 lowers the control voltage VCNT based on the L-level control signal CNT, and lowers the gain of the operational amplifier 22. Then, the change of the output signal Vc of the operational amplifier 22 with respect to the change of the output voltages Vr and Vp becomes small. Accordingly, the PLL circuit 20 gradually lowers the frequency of the output signal fvco when the frequency of the output signal fvco of the VCO 16 is close to the desired frequency.

As a result, the PLL circuit 20 of the present embodiment
Operates when the frequency of the output signal fvco of the VCO 16 is away from the desired frequency so that the frequency of the output signal fvco quickly matches the desired frequency, and the frequency of the output signal fvco becomes the desired frequency. When they are close to each other, they operate so that the frequency of the output signal fvco gradually changes near the desired frequency. The PLL circuit 20 locks the frequency of the output signal fvco output from the VCO 16 to a desired frequency by repeating such an operation.

As described above, this embodiment has the following functions and effects. (1) The PLL circuit 20 of the present embodiment includes the integration circuits 21a and 21b and the operational amplifier 22 on the PLL loop, and the gain of the operational amplifier 22 is controlled by the detection circuit 23 and the gain control circuit 24. And
When the frequency of the output signal fvco of the VCO 16 is separated from the desired frequency, the PLL circuit 20 operates so that the frequency of the output signal fvco quickly matches the desired frequency. Therefore, the lock-up time can be reduced. In addition, when the frequency of the output signal fvco is close to the desired frequency, the PLL circuit 20 operates so that the frequency of the output signal fvco gradually changes near the desired frequency. Accordingly, excessive change of the output signal fvco is suppressed, so that noise of the output signal fvco can be reduced. That is, the noise of the output signal fvco can be reduced while shortening the lock-up time.

(2) The detection circuit 23 obtains the phase difference between the pulse signals φR and φP of the phase comparator 12 and, based on the obtained phase difference, changes the frequency of the output signal fvco from the desired frequency. It is configured to determine whether the frequency is present or close to a desired frequency. Then, the gain control circuit 24 is configured to control the gain of the operational amplifier 22 based on the determination. Therefore, the determination and the gain control can be performed reliably and easily.

(3) The integration circuits 21a, 21b
(Capacitance / resistance) Integrator circuit. Therefore, a simple circuit configuration can be obtained. (Second Embodiment) Hereinafter, a second embodiment will be described with reference to FIG. In this embodiment, a lock detection circuit 40 of a PLL circuit shown in FIG. 7 is used instead of the detection circuit 23 of the first embodiment shown in FIG.

The pulse signals φR and φP from the phase comparator 12 are input to the EOR circuit 41 of the lock detection circuit 40, and the EOR circuit 41 outputs an output signal S1 based on the pulse signals φR and φP.

The output signal S1 is input to the flip-flop circuit FF4 as data D, and the reference clock signal C
K is input. The flip-flop circuit FF4 outputs an output signal Q (S2) based on the output signal S1 in synchronization with the rising edge of the reference clock signal CK.

The output signals S1,
S2 is input, and the NAND circuit 42 outputs the output signals S1,
An output signal based on S2 is output. The output signal of the NAND circuit 42 is inverted by the inverter circuit 43, and the inverted signal S3 is input to the flip-flop circuit FF5 as data D.

The reference clock signal CK is input to the flip-flop circuit FF5. Flip-flop circuit F
F5 outputs an output signal Q (S4) based on the inverted signal S3 in synchronization with the rising edge of the reference clock signal CK.

The output signal S1 of the EOR circuit 41 is inverted by the inverter circuit 44, and the inverted signal S1 is supplied to the flip-flop circuits FF6 to FF8 by the clock signal C.
Input as K.

The output signal S4 of the flip-flop circuit FF5 is inverted by the inverter circuit 45, and the inverted signal S4 is input as data D to the flip-flop circuit FF6. The flip-flop circuit FF6 outputs the rising edge of the inverted signal S1, that is, the output signal S1.
1 in synchronization with the falling edge of
4 based on the output signal Q (S5).

The output signal S5 is input as data D to the flip-flop circuit FF7. The flip-flop circuit FF7 outputs an output signal Q (S6) based on the output signal S5 in synchronization with the falling edge of the output signal S1 as described above.

The output signal S6 is input as data D to the flip-flop circuit FF8. The flip-flop circuit FF8 outputs an output signal Q (S7) based on the output signal S6 in synchronization with the falling edge of the output signal S1 as described above.

Output signals S5 to S7 are supplied to NAND circuit 46.
And the NAND circuit 46 outputs the output signals S5 to S7.
And outputs an output signal based on. The output signal of the NAND circuit 46 is inverted by the inverter circuit 47, and the inverted signal is output as the lock detection signal LD and used as the control signal CNT.

The lock detecting circuit 40 thus configured
When one of the pulse signals φR and φP goes high, the output signal S1 of the EOR circuit 41 goes high. When the reference clock signal CK rises after the output signal S1 goes high, the flip-flop FF4
Output signal S2 attains an H level.

Only when both output signals S1 and S2 attain H level, inverted signal S3 attains H level. And
When the reference clock signal CK rises after the inverted signal S3 goes high, the output signal S4 of the flip-flop FF5 goes high.

That is, when the reference clock signal CK rises twice or more after the output signal S1 goes high, that is, when the phase difference between the pulse signals φR and φP exceeds the predetermined value, the output signal S4 goes high. . This output signal S4
When the output signal S1 falls to the L level during the period of the H level, the output signal S5 of the flip-flop circuit FF6 is output.
Becomes L level. As a result, the output signal of the NAND circuit 46 becomes H level, the L level lock detection signal LD is output, and the unlocked state is detected.

The output signal S1 falls to the L level before the reference clock signal CK rises twice.
That is, when the phase difference between the pulse signals φR and φP becomes smaller than the predetermined value, the output signal S4 becomes L level. Then, when the output signal S1 sequentially falls to the L level before the reference clock signal CK rises twice, the output signals S5 to S7 of the flip-flops FF6 to FF8 sequentially go to the H level. When the output signals S5 to S7 are all at H level,
The output signal of the NAND circuit 46 becomes L level, the lock detection signal LD of H level is output, and the locked state is detected.

If the lock detection signal LD that changes in this way is used as the control signal CNT, the PLL circuit 20 of the first embodiment can be operated in the same manner.

The present invention may be embodied in the following modes other than the above embodiment. In the above embodiments, the gain control means is configured by the detection circuit 23 or the lock detection circuit 40 and the gain control circuit 24, and the gain of the operational amplifier 22 is controlled by the control means. However, the present invention is not limited to this, and the gain of the operational amplifier 22 may be controlled by another configuration. For example, the configuration may be as follows.

Although the detailed description of the reference frequency divider 11 is omitted in the above description, in detail, the reference frequency divider 11 divides the crystal oscillation signal based on an arbitrarily set division ratio and outputs it as the reference signal fr. It is configured. In this case, the reference frequency divider 11
, A load enable signal is input from the outside when setting the frequency division ratio. In such a reference frequency divider 11, the frequency of the output signal fvco is often separated from the desired frequency immediately after setting the frequency division ratio. Therefore,
The gain of the operational amplifier 22 is increased for a predetermined time after the load enable signal is input.
The gain control means may be configured to operate so as to lower the gain of No. 2.

In the above embodiments, the integration circuit 21
Although a and 21b are configured by CR (capacitance / resistance) integration circuits, the circuit configuration is not limited as long as the pulse signals φR and φP can be respectively smoothed to generate output voltages Vr and Vp as voltage signals. .

In the above embodiments, the operational amplifier 22
Is configured as shown in FIG. 6, but the circuit configuration is not limited to this as long as it can operate in the same manner as described above. In the above embodiments, the gain control circuit 24
Was configured as shown in FIG. 5, but the circuit configuration is not limited to this as long as the circuit can operate in the same manner as described above.

The technical ideas other than the claims that can be grasped from the above embodiments will be described below together with their effects. (A) The smoothing circuit comprises a CR integration circuit.
The PLL circuit according to any one of claims 1 to 3. With this configuration, a simple circuit configuration can be obtained.

[0087]

As described in detail above, according to the present invention,
It is possible to provide a PLL circuit that can reduce noise of an output signal while shortening a lock-up time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a PLL circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of a detection circuit.

FIG. 4 is a waveform chart showing an operation of the detection circuit.

FIG. 5 is a circuit diagram showing a specific configuration of a gain control circuit.

FIG. 6 is a circuit diagram showing a specific configuration of the operational amplifier.

FIG. 7 is a circuit diagram illustrating a specific configuration of a detection circuit according to a second embodiment.

FIG. 8 is a block diagram showing a conventional PLL circuit.

FIG. 9 is a waveform diagram showing a pulse signal and an output voltage.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 smoothing circuit 3 DC amplifier 4 voltage controlled oscillator 5 gain control means fr reference signal fvco output signal Vc voltage signal Vrp output voltage φR, φP pulse signal

Continued on the front page (72) Inventor Kazumi Ogawa 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Inc. (72) Inventor Shuji Sumi 2-844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu VSI Inside the corporation

Claims (3)

[Claims] A phase comparator that compares a frequency of a reference signal with an output signal and outputs a pulse signal having a pulse width corresponding to the frequency difference; and smoothes the pulse signal of the phase comparator to a DC voltage. A smoothing circuit that converts and outputs the DC voltage as an output voltage; a DC amplifier that receives an output voltage of the smoothing circuit and outputs a voltage signal obtained by amplifying the output voltage; and a voltage value of a voltage signal of the DC amplifier. A voltage-controlled oscillator that outputs the output signal having a frequency based on: When the frequency of the output signal of the voltage-controlled oscillator is separated from the frequency of the reference signal by a predetermined value or more,
Gain control means for increasing the gain of the DC amplifier, and reducing the gain of the DC amplifier when the frequency of the output signal approaches a frequency less than a predetermined value with respect to the frequency of the reference signal. PLL circuit. 2. The phase comparator outputs two pulse signals each having a pulse width corresponding to a frequency difference between a reference signal and an output signal, and the smoothing circuit outputs a pulse signal of the phase comparator. Are each converted into a DC voltage by smoothing the DC voltage, and the DC voltage is output as an output voltage.The DC amplifier inputs the output voltage of the smoothing circuit, and amplifies the potential difference between the output voltages. 2. The PLL circuit according to claim 1, comprising a differential operational amplifier that outputs a voltage signal. 3. The gain control means calculates a phase difference between the pulse signals of the phase comparator, determines whether the calculated phase difference is equal to or greater than a predetermined value, or less than a predetermined value, and outputs the determination signal. And a gain control signal for increasing the gain of the operational operational amplifier is output to the operational operational amplifier based on the determination signal that the phase difference is determined to be equal to or greater than a predetermined value. 3. The PLL according to claim 2, further comprising: a gain control circuit that outputs a gain control signal for lowering the gain of the operational operational amplifier to the operational operational amplifier based on a determination signal that the circuit determines that the phase difference is less than a predetermined value. circuit.