JPH05276033A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce a rough tuning time because the rough tuning is implemented at a high speed when a frequency step is large by varying a rough tuning output depending on a difference between a count of a counter and a setting frequency. CONSTITUTION:A subtractor 43 obtains a difference QDIF between a count QVCO by a counter 41 counting an oscillating frequency fVCO of a VCO and a preset frequency digital signal frequency DSET. The output data QDIF are inputted to digital comparators 44-47, in which how much the frequency fVCO is larger or smaller than upper and lower limit frequency data D1, D2, -D1, -D1 is obtained. That is, in the case of the frequency difference QDIF>D1 and the difference QDIF<-D1, since the frequency fVCO is sufficiently apart from the upper/lower limit frequency data, a large voltage +V1 or -V1 is outputted as a control signal VP and the rough tuning is implemented quickly. Thus, the rough tuning time when a frequency step is large is reduced by changing the rough tuning output in response to the difference between the count of the counter and the setting frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to reduction of coarse tuning time of a coarse tuning circuit.

[0002]

2. Description of the Related Art Generally, a phase locked circuit (Phase Locked Loo
In a p Circuit: hereinafter referred to as a PLL circuit, a coarse tuning circuit has been conventionally used in order to drive an oscillation frequency of a voltage controlled oscillator (hereinafter referred to as a VCO) to a synchronizable range.

FIG. 3 is a circuit showing an example of a conventional PLL circuit.
Block diagram, Fig. 4 is the block of coarse tuning circuit used in Fig. 3.
It is a figure. In the figure, the output of VCO 1 is divided by frequency converter 2.
After being divided, the phase comparator 3 outputs the reference signal generator 4.
Force and phase are compared. The output of the phase comparator 3 is loop
The DC component is extracted by the filter 5 and added to the VCO 1,
The oscillation frequency is controlled. The output of loop filter 5 is
It is also added to the integrator 60 of the coarse tuning circuit 6,
The output voltage of is input to the voltage comparator 61. The input
Voltage signal V_XIs preset in the voltage comparator 61
Upper limit comparison voltage V_BAnd lower limit comparison voltage V_ACompared to
It The up / down counter 62 outputs the voltage from the voltage comparator 61.
V by signal_X<V_AOr V_B<V_XCorresponding to black
Clock from the clock pulse generator 63
Or down count, V_A≤V _X≤V_BWhen it comes to
Stop und. Output of the up / down counter 62
Is input to the adder 64 and is set by the setting circuit 65.
The digital value for use is added. The output of the adder 64 is D /
It is converted into an analog signal by the A converter 66, and the VCO1 coarse
Input to the tuning control terminal.

As a result, the coarse tuning frequency applied to the VCO 1 also increases / decreases in response to the increase / decrease in the output of the adder 64, so that the oscillation frequency of the VCO 1 is held at a frequency that can be synchronized.

However, in the above-mentioned conventional synchronous phase circuit, the coarse tuning circuit includes analog circuits such as an integrator, a voltage comparator, a setting circuit, and a D / A converter, which is disadvantageous in miniaturization and IC integration. ..

Therefore, the applicant of the present invention has filed an application for Japanese Patent Application No. 2-12002 (hereinafter referred to as prior application 1) as a phase-locked circuit which can easily make a coarse tuning circuit small and integrated. FIG. 5 is a block diagram of a main part of the coarse tuning circuit according to the prior application 1. The same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. 1 is a VCO, 3 is a phase comparator for comparing the phase of the reference signal and the phase of the output of the frequency converter 2, 1
Reference numeral 0 is an analog adder whose output is added to the loop filter 5 with the output of the phase comparator 3 as one input, and 9 is a coarse tuning circuit for adding a control signal corresponding to the output of the VCO 1 to the other input of the adder 10. Is.

FIG. 6 is a circuit diagram showing the details of the coarse tuning circuit 9 shown in FIG. Reference numeral 91 is a counter for counting the output of the VCO 1, 92 is a first register for holding the output of the counter 91, 93 is a second register for which an upper limit frequency is preset, and 94 is a third register for which a lower limit frequency is preset. A register, 95 is a first digital comparator for comparing the sizes of the registers 92 and 93, 96 is a second digital comparator for comparing the sizes of the registers 92 and 94, 97-
99 is a logic circuit for generating a switch drive signal corresponding to the outputs of the digital comparators 95 and 96;
Switches 0 and 101 are connected to the positive voltage + V and the negative voltage -V, respectively, and are driven by the outputs of the logic circuits 97 and 99, respectively. The clock signal f _CK is the counter 9
1 clear terminal, register 92 clock terminal and AN
It is added to the input terminals of the D circuits 97 and 99.

In the phase locked loop circuit of FIG. 5, when phase locking is performed, the output frequency f _I of the frequency converter 2 becomes equal to the reference frequency f _R. In this case, the output V of the coarse tuning circuit 9
_P becomes 0, and the output of the phase comparator 3 is directly input to the frequency control terminal of the VCO 1 via the loop filter 5.

When the phase synchronization is lost, VC
O1 when the oscillation frequency _{f VCO} is higher than the upper limit frequency of the output control signal _{V P,} such as to lower the oscillation frequency _{f VCO} from coarse tuning circuit 9, VCO 1 in the oscillation frequency f
Oscillation frequency f when _VCO is lower than the lower limit frequency
A control signal V _P that raises the _VCO is output from the coarse tuning circuit 9.

FIG. 7 is a timing chart showing the operation of the coarse tuning circuit 9 of FIG. The output of the VCO 1 is counted by the counter 91 only while the clock signal f _CK is at the L level. The contents of the counter 91 are transferred to the register 92 and compared with the contents of the registers 93 and 94 by digital comparators 95 and 96, respectively. Oscillation frequency f _{VC O}
When it is desired to tune to between the lower limit frequency f ₁ and the upper limit frequency f ₂ , the data shown by the following equation is set in advance in the terminals D _{0 to} D ₇ of the registers 93 and 94.

Data of register 94 = f ₁ × T Data of register 93 = f ₂ × T Since f _VCO × T is input to the register 92, control is performed by operations of the logic circuits 97 to 99 and the switches 100 and 101. the output _{V P} becomes _{V P = + V f 1 <} V P = -V when _{V P = 0 f VCO ≧ f} 2 when _f VCO _{<f 2} when _{f VCO} ≦ _{f 1} (Fig. 7 (E) ).

FIG. 8 shows the oscillation frequency f during the coarse tuning operation.
It is a change explanatory view of _VCO , (a) shows the case where a frequency step is small, (b) has shown the case where a frequency step is large. Here, the coarse tuning time t _s is df _VCO / dt (equal to the slope of FIG. 8) for changing the oscillation frequency f _{V CO} proportional to the value of the voltage V, and Δf _VCO (f of FIG. 8) for the frequency step. When ₁ -f _0), becomes _{t s = Δf VCO / (df} VCO / dt).

As is clear from the above equation, the coarse tuning time t _s
In order to shorten .DELTA.f _VCO , df _VCO / dt may be increased or .DELTA.f _VCO may be decreased. However, df
_{If VCO} / dt is made too large, the clock signal f of FIG.
Oscillation frequency f due to delay of coarse tuning equal to cycle T of _{CK
Since the VCO} may oscillate near the target frequency f ₁ as shown in FIG. 9, it is necessary to make df _VCO / dt as small as possible. That is, there is a trade-off between the oscillation frequency f _VCO and the coarse tuning time, and when the oscillation frequency f _VCO is large, the coarse tuning time will inevitably become long.

Therefore, as a countermeasure against this problem, the applicant of the present invention has applied for Japanese Patent Application No. 3-43642 (hereinafter referred to as prior application 2). FIG. 10 is a block diagram of a main part of a coarse tuning circuit which performs coarse tuning operation in two stages according to the prior application 2. The configuration other than the coarse tuning circuit 9 is the same as that of the phase locked loop circuit of FIG. In the figure, 21 is a counter that counts the oscillation frequency of the VCO 1, 22 is a register that holds the count value of the counter 21, 23 is a first data selector that selects one of two types of lower limit frequency data, and 24 is two types. Of the upper limit frequency data, 25 is a gate generation circuit for generating two kinds of gate signals for determining the counting time of the counter 21, and 26 is a gate signal output of the gate generation circuit 25. Changeover switch for selecting and controlling the counter 21 and the register 22, 2
Reference numeral 7 is a first digital comparator for comparing the output value of the register 22 with the output value of the data selector 23, and 28 is a second digital comparator for comparing the output value of the register 22 with the output value of the data selector 24. The AND circuits 29 and 30 and the change-over switches 32 to 37 constitute an output circuit that generates control signals V _P of different magnitudes corresponding to the counting times based on the outputs of the digital comparators 27 and 28. ± V ₁ and ± V ₂ are positive and negative voltage sources having different magnitudes. However, V ₁ > V ₂ . 31 is a frequency setting input and digital comparators 27, 28
Is a switching circuit for controlling the data selectors 23, 24 and the selector switches 26, 32, 33 in accordance with the output of the.

The operation of the circuit of FIG. 10 will be described with reference to the operation explanatory view of FIG. 11 and the timing chart of FIG.
Oscillation frequency f _{VCO of VCO} 1 by new frequency setting
.., the switching circuit 31 switches the coarse tuning circuit to the fast coarse tuning mode. At this time, the gate generation circuit 25
The selector switch 26 selects the counting time T ₁ , the data selectors 23 and 24 select the frequency data D ₁ and D ₃ , and the output selector switch 32,
At 33, the side a is selected. Then, when the loop capture range is f _C , the target frequency is f _T , and the window width ratio is N as shown in FIG. 11, the lower limit data D ₁ and the upper limit data D ₃ are set as follows.

D ₁ = (f _T −N · f _C ) · T ₁ D ₃ = (f _T + N · f _C ) · T _{1 Further} , the count value Q _VCO in the counter 21 is Q _VCO = f _VCO · T since _1, the output a of the digital comparator 27, 28 when the _{f VCO <f T -N · f} C
<B, A ≦ B is 1, the output of the AND circuit 29 is 1, the changeover switch 34 is turned on, and the coarse tuning output V _P is + V.
₁ is output and f _VCO rises (FIG. 11). Similarly, when f _VCO > f _T + N · f _C , −V ₁ is output as the coarse tuning output V _P , and f
Lower the _VCO (Figs. 11 and 12).

When f _T −N · f _C ≦ f _VCO ≦ f _T + N · f _C , the switching circuit 31 switches the coarse tuning operation to the high resolution coarse tuning mode. That is, the counting time T ₂ longer than T ₁ , the frequency data D ₂ and D ₄ , and the output changeover switch b are selected. Here, the lower limit data D ₂ and the upper limit data D ₄ are set as follows.

D ₂ = (f _T −f _C ) · T ₂ D ₄ = (f _T + f _C ) · T _{2 Since} the count value Q _VCO in the counter 21 is Q _VCO = f _VCO · T ₂ , , F _VCO <f _T −f _C , the f _VCO is raised by + V ₂ (FIG. 11), and when f _VCO > f _T + f _C , the −V ₂ lowers f _VCO (FIG. 11, FIG. 1).
2).

When f _T -f _C ≤f _VCO ≤f _T + f _C , the coarse tuning operation is terminated.

According to the phase-locked loop circuit of the prior application 2 having such a configuration, when the coarse tuning operation is performed in two stages and the oscillation frequency of the VCO is changed, when the oscillation frequency is far from the capture range, a short counting time is obtained. The coarse tuning time can be shortened by performing coarse tuning with and performing coarse tuning with high resolution due to a long counting time when approaching the capture range.

[0021]

However, in the configuration of the prior application 2 as described above, when the counting time is switched, the count value before the switching becomes invalid, and therefore, as shown in FIG. It is necessary to provide a section T ₃ during which coarse tuning is suspended.

Further, since there are many switching portions, the circuit structure becomes complicated. The present invention has been made in view of such a problem, and an object thereof is to change the coarse tuning output according to the difference between the count value of the counter and the set frequency, so that the coarse step when the frequency step is large is performed. It is to shorten the tuning time.

[0023]

A phase locked loop circuit according to the present invention is a phase locked loop circuit in which a coarse tuning circuit controls the oscillation frequency of a voltage controlled oscillator to a synchronizable range. A counter for counting the oscillation frequency of the counter, a subtractor for obtaining a difference between the count value of the counter and preset frequency data, output data of the subtractor, and preset plural sets of different upper and lower limit frequency data. Is provided with a plurality of sets of digital comparators for comparing the above and an output circuit that generates control signals of different magnitudes based on the outputs of these digital comparators, and is configured to perform a coarse tuning operation in two or more stages. ..

[0024]

According to the difference between the count value of the counter and the preset frequency data, different coarse tuning control signals are output.

As a result, when the difference between the count value of the counter and the set frequency data is large, the coarse tuning operation can be performed at high speed, and the coarse tuning time can be shortened.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, showing an example of selectively outputting two sets of coarse tuning control signals ± V ₁ and ± V ₂ . In the figure, 41 is VCO1
Counter for counting the oscillation frequency _{f VCO} of the 42 registers are used to hold the count value _{Q VCO} counter 41, 43 is subtracted for obtaining a difference _{Q DIF} between preset frequency data _{D SET} and the count value _{Q VCO} counter 41 It is a vessel.
The output data Q _DIF of the subtractor 43 is input to the digital comparators 44 to 47 and preset upper and lower limit frequency data D ₁ , D ₂ , -D ₁ , -D ₂ (D ₁ > D ₂ ).
Compared to. 48 is a decoder, 49-52 are changeover switches driven by the output of the decoder 48, ± V ₁ , ± V ₂
(V ₁ > V ₂ ) are positive and negative voltage sources of different magnitudes,
These constitute an output circuit that selectively outputs control signals V _P of different magnitudes based on the outputs of the digital comparators 44 to 47.

The operation of the circuit of FIG. 1 will be described with reference to the operation explanatory diagram of FIG. The subtracter 43 obtains the difference Q _DIF between the count value Q _VCO of the oscillation frequency f _VCO of the _{VCO 1 by} the counter 41 and the preset frequency data D _SET . The output data Q _DIF of the subtractor 43 is input to the digital comparators 44 to 47, and the oscillation frequency f _VCO is the upper and lower limit frequency data D ₁ , D ₂ , -D ₁ ,-.
How large (or small) D ₂ is required. _{Here, Q} DIF> _{D 1} or _{Q DI} F <-D
_In the case of ₁ , since the oscillation frequency f _VCO is sufficiently far from the upper and lower limit frequency data, there is no fear of vibration as shown in FIG.
A large voltage + V ₁ or −V ₁ is output as the control signal V _P to quickly perform the coarse tuning operation.

Then, D ₂ <Q _DIF ≤ D ₁ or -D
_{When 1} ≤ Q _DIF <-D ₂ and the oscillation frequency f _VCO approaches the set frequency to some extent, the coarse tuning operation is performed sufficiently slowly, and -D ₂ ≤ Q _DIF ≤ D ₂ and the oscillation frequency f
_{When the VCO} enters the capture range, the coarse tuning operation is finished.

In the case of the prior application 2, since there is only one set of digital comparators, the frequency switching speed always starts from the fastest state and the frequency step is passed in the inside of a large window. There were many things. On the other hand, the present invention is particularly effective when the step width is narrow because it starts at an appropriate speed. For example, when the frequency step is 320 MHz, both of the prior application 2 and the present invention are about 80 μs, but when the frequency step is 10 MHz, the prior application 2 is about 60 μs, whereas in the present invention it is shortened to about 20 μs. ..

The coarse tuning operation is not limited to two steps, but can be performed in arbitrary plural steps. Further, the circuit of the present invention and the circuit of the prior application 2 may be combined. Further, by providing a frequency divider in the preceding stage of the counter, it is possible to use even a high frequency region.

[0031]

According to the present invention described in detail above, since the coarse tuning control signal of different magnitude is output according to the difference between the count value of the counter and the preset frequency data, the counter measurement is performed. When the difference between the numerical value and the set frequency data is large, the coarse tuning operation can be performed at high speed and the coarse tuning time can be shortened.

Since all the circuits can be constituted by digital circuits, it is possible to realize a phase-locked circuit which can be miniaturized by IC integration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is a block diagram showing a conventional phase locked loop circuit.

FIG. 4 is a block diagram of a main part configuration showing a coarse tuning circuit of the circuit of FIG.

FIG. 5 is a block diagram showing a phase synchronization circuit according to Prior Application 1.

FIG. 6 is a block diagram of a main part configuration of a coarse tuning circuit of the prior application 1.

FIG. 7 is a timing chart showing the operation of FIG.

8 is an explanatory diagram of the operation of FIG.

9 is an operation explanatory diagram of FIG. 6;

FIG. 10 is a configuration block diagram of a main part of a coarse tuning circuit according to Prior Application 2.

11 is an explanatory diagram of the operation of FIG.

12 is a timing chart showing the operation of FIG.

[Explanation of symbols]

 1 Voltage Controlled Oscillator (VCO) 9 Coarse Tuning Circuit 41 Counter 42 Register 43 Subtractor 44-47 Digital Comparator 48 Decoder 49-52 Changeover Switch

Claims (1)

[Claims] 1. A phase-locked circuit for controlling an oscillation frequency of a voltage-controlled oscillator to a synchronizable range by a coarse tuning circuit, wherein the coarse tuning circuit counts an oscillation frequency of the voltage-controlled oscillator, and a counter of the counter. A subtractor for obtaining a difference between a numerical value and preset frequency data, and a plurality of sets of digital comparators for comparing the output data of the subtractor with a plurality of preset different upper and lower limit frequency data,
A phase locked loop circuit comprising an output circuit for generating control signals of different magnitudes based on the outputs of these digital comparators, and configured to perform a coarse tuning operation in two or more stages.