JPH08130467A - Pll circuit - Google Patents

Abstract

PURPOSE: To provide a PLL circuit for which the lock-up time of PLL is short. CONSTITUTION: While the phase compared result of the oscillated output signal of a voltage controlled oscillator(VCO) 1 and a reference signal is not outputted from a phase comparator 5, the frequency of that oscillated output signal is measured by a frequency counter 8 and corresponding to this measured result, the oscillation frequency of the VCO 1 is controlled. Thus, even when the output of the phase comparator 5 is set in a high impedance state, the oscillation frequency of the VCO 1 is controlled so that the lock-up time of PLL can be shortened.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a PLL (Phase L).
particularly, a locked loop circuit, which compares the phase of the oscillation output signal of the voltage controlled oscillator with the reference signal and controls the oscillation frequency of the voltage controlled oscillator according to the comparison result.
Regarding the LL circuit.

[0002]

2. Description of the Related Art A conventional PLL circuit will be described with reference to FIG.

In the figure, a conventional PLL circuit includes a voltage controlled oscillator 1 and an output frequency fVC of the voltage controlled oscillator 1.
A programmable divider 2 for dividing O 2 and an N value setting register 3 for setting a division value N of the programmable divider 2 are included.

Further, the conventional PLL circuit has a reference frequency fre.
A reference frequency generator 4 for generating an output signal of f, and a phase comparator 5 for comparing the phase of this reference frequency fref with the frequency fN of the divided output signal of the programmable divider 2.
And a charge pump circuit 6 that outputs a voltage of a predetermined level according to the comparison result, and a low-pass filter circuit 7 that converts the output of the charge pump circuit 6 into a control DC voltage for the voltage controlled oscillator 1. Has been done.

In such a configuration, the frequency fVCO output from the voltage controlled oscillator 1 is input to the programmable divider 2. The programmable divider 2 divides the frequency by a value preset in the N-value setting register 3, and the divided frequency fN is used together with the reference frequency fref generated by the reference frequency generator 4 in the phase comparator. 5
Is input to The phase comparator 5 compares the phases of the divided frequency fN and the reference frequency fref, and outputs the comparison result as an output signal DWN (inverted value) or an output signal UP (inverted value).

In this case, if the frequency fref> fN, the comparison result is sent as the output signal UP (inverted value), and if the frequency fref <fN, the comparison result is sent as the output signal DWN (inverted value). As a result, the charge pump circuit 6
Is low level if frequency fref> fN, frequency f
If ref <fN, high-level output is performed. If frequency fref = fN, high-impedance output is performed. The charge pump circuit 6 outputs the output signal DW as shown in the figure.
It is composed of a P-type transistor whose gate input is N (inverted value) and an N-type transistor whose gate input is an inverted signal of the output signal UP (inverted value), and one of these transistors is turned on or both are turned off. To work.

The output of the charge pump circuit 6 is input to the low pass filter circuit 7 to change the charge amount of the capacitor inside the circuit. The voltage VT (Tuning Vol) applied to the voltage controlled oscillator 1 due to the change in the charge amount.
The value of (stage) changes and its output frequency fVCO changes. By thus forming the feedback circuit, the output frequency fVCO of the voltage controlled oscillator 1 is finally obtained.
Is controlled so as to match the phase of the reference frequency fref. At this time, frequency fVCO and reference frequency fre
There is a relationship of fVCO = N · fref with f, and setting the frequency division value (N value) to (N + 1) means increasing the frequency fVCO by the amount corresponding to the reference frequency fref. .

A state in which the phases match each other is called a lock state, and a voltage value given to the voltage controlled oscillator 1 at that time is called a lockup voltage.

The internal structure of the low-pass filter circuit 7 will be described with reference to FIG.

As shown in the drawing, the low pass filter circuit 7 includes transistors Q1 and Q2 and capacitors C1 and C.
2 and resistors R1 to R3. Then, according to the output of the charge pump circuit 6, the capacitor C
The charge / discharge control of 1 changes the value of the voltage VT applied to the voltage controlled oscillator 1.

Next, the operations of the phase comparator 5 and the charge pump circuit 6 will be described with reference to FIG.

First, the frequency fref> fN is shown in FIG.
The waveform in the case of is shown. In the figure, the frequency f
Since the frequency fN is smaller than ref, the output signal UP (inverted value) is output according to the phase difference. Specifically, during the fall timing of both signals, the output signal UP
(Inverted value) becomes low level.

Then, the charge pump circuit 6 outputs the output E1 shown in response to the output signal UP (inverted value). At this time, the low-pass filter circuit 7 is controlled while the output E1 is at the low level, but is not controlled at all during the high impedance output period a while the output E1 is at the high level.

Next, the frequency fref <fN is shown in FIG.
The waveform in the case of is shown. In the figure, the frequency f
Since the frequency fN is larger than ref, the output signal DWN (inverted value) is output according to the phase difference. Specifically, during the fall timing of both signals, the output signal D
WN (inverted value) becomes low level.

In response to the output signal DWN (inverted value), the charge pump circuit 6 outputs the illustrated output E1.
Is sent. At this time, the low-pass filter circuit 7 is controlled while the output E1 is at the high level, but is not controlled at all during the high impedance output period a while the output E1 is at the low level.

Further, the frequency fref = fN is shown in FIG.
The waveform in the case of is shown. In the figure, the frequency f
Since ref and frequency fN are equal, neither output signal UP (inverted value) nor output signal DWN (inverted value) is output. Specifically, both the output signal UP (inverted value) and the output signal DWN (inverted value) remain at the high level.

Therefore, the output E1 is not sent from the charge pump circuit 6 and the high impedance state is established ("Hi-Z" in the figure).

[0018]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
In the circuit, as shown in FIG. 8, the output waveform of the charge pump circuit 6 until the PLL changes from the unlocked state to the locked state after setting the frequency division value in the N value setting register. Has a high impedance output period a. Therefore, there is a drawback that the time (lock-up time) until the PLL changes to the locked state is long. In particular, when the frequency division value is switched to a large value, it takes a very long time to change to the locked state.

In Japanese Patent Laid-Open No. 1-220523, the purpose (solved problem) is to prevent the occurrence of the pseudo lock state, and therefore, the known art cannot shorten the lockup time.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a PLL circuit having a short PLL lock-up time.

[0021]

A PLL circuit according to the present invention is a first comparison circuit which compares a phase of a voltage controlled oscillator with that of an oscillation output signal and a reference signal and outputs a comparison result signal corresponding to the comparison result. Means for controlling the oscillation frequency of the voltage controlled oscillator according to the comparison result signal.
A circuit, a measuring means for measuring the frequency of the oscillation output signal when the comparison result signal is not output,
A control means for controlling the oscillation frequency of the voltage controlled oscillator according to the measurement result is included.

[0022]

The frequency of the oscillation output signal is measured when the phase comparison result between the oscillation output signal of the voltage controlled oscillator and the reference signal is not output. The oscillation frequency of the voltage controlled oscillator is controlled according to the measurement result.

[0023]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a PLL circuit according to the present invention. In the figure, FIG.
The same parts as those in the middle are designated by the same reference numerals and the description thereof will be omitted.

The PLL circuit according to the first embodiment of the present invention is different from the conventional circuit in that the output from the charge pump circuit 6 is E1.
In the high impedance state in which no voltage is transmitted, the frequency of the oscillation output signal fVCO is measured, and the voltage controlled oscillator 1 is controlled via the low pass filter 7 according to the measurement result.

That is, the PLL circuit according to the present embodiment is
A frequency counter control circuit 9 for controlling the frequency division frequency counter 8 according to the output of the programmable divider 2, and a frequency division frequency counter 8 for performing a counting operation in response to a signal from the control circuit 9 according to a clock of frequency fCLK.
And a count buffer 1 that temporarily holds this count value
4 is included.

Further, the PLL circuit according to the present embodiment holds a desired cycle setting register 10 for externally setting a cycle value corresponding to a frequency to be set, a value set in the register 10 and a buffer 14. The output signal UP (inverted value) and the output signal DWN (inverted value) are set in advance, and the output control that outputs these signals according to the comparison result of the comparator circuit 11 The circuit 13 and the output signal UP (inverted value),
And a charge pump circuit 12 for sending and outputting an output E2 for changing the voltage VT applied to the voltage controlled oscillator 1 by charging / discharging a capacitor inside the low pass filter circuit 7 according to the signal DWN (inverted value). Has been done.

In such a configuration, the output frequency fVCO of the voltage controlled oscillator 1 is divided by the programmable divider 2, and the divided frequency fN is the frequency counter control circuit 9
Is input to The frequency counter control circuit 9 sends out a signal for controlling count start and count reset of the frequency division frequency counter 8.

The divided frequency counter 8 continues the counting operation from the count start to the count reset,
This count value is stored in the count buffer 14 for each cycle of the divided frequency fN. That is, the count buffer 14 stores a value obtained by counting one cycle of the divided frequency fN with the pulse width counting clock (frequency fCLK).

A count value corresponding to the pulse width of the desired frequency division frequency is set in advance in the desired cycle setting register 10, and is stored in the count buffer 14 at the rising timing of this set value and the comparison signal to be generated next. The calculated count value is compared in the comparison circuit 11.

The output control circuit 13 continues to output a preset value until the comparison result shows a match. in this case,
High-level and low-level voltage values for controlling the charge pump circuit 12 are set in advance in the output control circuit 13, and these voltage values are set in accordance with the set value (dividing value) of the N-value setting register 3. Send as an alternative. Then, after the comparison result shows a match, the output E2 of the charge pump circuit 12 is in a high impedance state. This allows
This does not affect the portion (phase comparator 5 and charge pump circuit 6) corresponding to the conventional circuit.

Further, the operation of this PLL circuit will be described with reference to FIG.

At time T S, when the frequency division value is set in the N value setting register 3, the frequency counter control is performed in response to the rising timing of the output signal (frequency fN) of the programmable divider 2 (at the time when the rising edge is detected). The circuit 9 outputs a register comparison signal, a counter reset signal, and a counter start signal. In this case, since these signals are sequentially output within one cycle of the clock of frequency fCLK as shown in the figure, they do not affect the counting operation of the next division frequency counter. Further, together with the output of these signals, the fact that the frequency division value has been set is transmitted to the output control circuit 13 by a signal line (not shown), and the output control circuit 13 starts outputting the preset value. As a result,
The output E2 of the charge pump circuit 12 is the output control circuit 13
The value depends on the setting value of.

On the other hand, when the counter start signal is input, the divided frequency counter 8 starts the counting operation according to the clock of the frequency fCLK. In this case, the count-up cycle is 1 / fCLK. The frequency fCLK
Is the frequency f of the output signal of the programmable divider 2.
Sufficiently higher than N (period is sufficiently short).

The counting operation of the divided frequency counter 8 is performed until the next rising timing of the output signal of the programmable divider 2, and the register comparison signal, the counter reset signal, the counter start from the frequency counter control circuit 9 at the next rising timing. The signal is output. In response to the register comparison signal, the count value of the frequency division frequency counter 8 at that time is input to and held in the count buffer 14. That is, by counting up for one cycle of the output signal (frequency fN) of the programmable divider 2, one cycle is measured and the measurement result is held in the count buffer 14.

The comparison circuit 11 compares the held count value (“x” in the figure) with the set value of the desired cycle setting register 10 (“n” in the figure). As a result of this comparison, since the two do not match, the divided frequency counter 8 resets the count value by the counter reset signal and then starts counting up again by the counter start signal.

Similarly to the above, the counting operation of the divided frequency counter 8 is performed until the next rising timing of the output signal of the programmable divider 2. Then, at the next rising timing, the count value is changed to the count buffer 1
The count value (“y” in the figure) that has been input to 4 and the set value of the desired period setting register 10 (“n” in the figure) are compared by the comparison circuit 11.

As a result of this comparison, since the two do not match,
The frequency dividing frequency counter 8 is reset in the same manner as above, and then starts counting up again. The output E2 of the charge pump circuit 12 remains at a value according to the set value of the output control circuit 13.

At the next rising timing, the count value (“n” in the figure) of the frequency dividing frequency counter 8 input to the count buffer 14 and the set value (“n” in the figure) of the desired cycle setting register 10 are set. Are compared by the comparison circuit 11. As a result of this comparison, the two match, so the comparison circuit 1
The coincidence output is sent from 1, the output control circuit 13 stops the output, and the output E2 of the charge pump circuit 12 becomes a high impedance state.

By the above operation, the high impedance state which has occurred in the conventional circuit is eliminated, so that the change of the capacitance value of the capacitor C1 in the low pass filter circuit 7 can be accelerated. Therefore, the lockup time of the PLL can be shortened. This lockup time will be described with reference to FIG.

FIG. 3 is a characteristic diagram showing the lockup time of the PLL circuit of FIG. FIG. 3 shows the state transition of the output voltage VT of the low pass filter 7 from the change of the frequency division value (N value) in the locked state of the PLL to the new locked state.

As shown in the figure, in general, the PLL is in an oscillating state in which overshoot and undershoot are repeated alternately from the unlocked state to the locked state, and after this oscillating state, the PLL is stabilized. Therefore,
Suppressing this vibration and shortening the time during which it is vibrating to speed up stabilization shortens the time from the unlocked state to the locked state.

Therefore, the control by the configuration added in this embodiment is performed up to just before the desired frequency division frequency fN.
After that, by switching to the control similar to the conventional one, the above-mentioned vibration state can be suppressed. Specifically, in the present embodiment, by masking the lower several bits of the desired period setting register 10, the control is switched to the control similar to the conventional one just before the desired frequency division frequency fN.

In the figure, A is the state transition by the conventional PLL circuit, B is the state transition by the PLL circuit of this embodiment (when switching to the conventional control immediately before the lockup voltage VLOCK is reached), and C is the output voltage VT. Is the lockup voltage VLO
The respective state transitions when switching to the conventional control when they become equal to CK are shown.

If the frequency division value of the PLL is changed at time T0 in the figure, in the state transition A by the conventional PLL circuit, the output voltage VT of the low pass filter circuit 7 has a high impedance period. Vibration continues for a long time. Therefore, at time T5, the lock state is reached,
Lockup time becomes longer.

On the other hand, if it is assumed that the frequency division value of the PLL is changed at the time T0, the state transition C is switched to the conventional control when the output voltage VT becomes the lockup voltage (time T2). , The overshoot after the switching becomes large. Therefore, the lock state is set at time T4, and the lockup time is shorter than that in the case of state transition A, but the time from time T2 to time T4 becomes longer.

On the other hand, in the state transition B, immediately before the output voltage VT becomes the lockup voltage VLOCK (time T1).
Switching to conventional control. That is, when the value of the output voltage VT becomes a voltage value between the current oscillation frequency of the voltage controlled oscillator and the lock frequency at which the PLL should be locked, and a voltage value near the lock frequency, It is switching to control. As a result, vibration can be suppressed, and the lock state is set at time T3.
As a result, the lockup time becomes shorter than that of the state transitions A and C.

Next, another embodiment of the PLL circuit according to the present invention will be described.

FIG. 4 is a block diagram showing the configuration of the second embodiment of the PLL circuit according to the present invention. In the figure, the same parts as those in FIGS. 1 and 6 are designated by the same reference numerals, and the description thereof will be omitted.

Also in this embodiment, similar to the circuit of the first embodiment, the frequency counter control circuit 9 for controlling the divided frequency counter 8 according to the output signal of the programmable divider 2 and the control circuit 9 from this control circuit 9. A frequency dividing counter 8 that performs a counting operation in response to a signal in response to a clock of frequency fCLK, a count buffer 14 that temporarily holds this count value, an output signal UP (inversion value) and an output signal DWN (inversion value) in advance. And the output control circuit 13 for outputting these signals, and the output signal UP
(Inverted value), a charge pump circuit 12 for changing the voltage VT applied to the voltage controlled oscillator 1 by controlling charge / discharge of a capacitor inside the low-pass filter circuit 7 according to the signal DWN (inverted value). There is.

The PLL circuit according to the present embodiment is different from the PLL circuit according to the first embodiment in that the RAM 17 for setting the cycle value corresponding to the frequency to be set, the set value and the count in the count buffer 14. The point is that it has a microcontroller 16 that compares the value and controls the output control circuit 13 according to the comparison result, and an interrupt generation circuit 15 that interrupts the controller 16. The controller 16 also sets the frequency division value N in the programmable divider 2.

In such a configuration, the output signal (frequency fN) of the programmable divider 2 is input to the frequency counter control circuit 9, and this control circuit 9 sends out a signal for controlling the frequency division counter 8 to generate the frequency division frequency. The point that the counter 8 performs the counting operation and the count value is stored in the count buffer 14 is the same as the operation in the case of the first embodiment. The operation of the circuit of this embodiment differs from that of the first embodiment in the following points.

That is, in this embodiment, when the measurement of the cycle of the output signal of the programmable divider 2 is completed, the measurement result is stored in the count buffer 14 and the interrupt generation circuit 15 interrupts the controller 16. I do. At the time of this interruption, the controller 16 reads the value of the count buffer 14 and compares the value with a desired cycle count value preset in the RAM 17. According to the comparison result, the controller 16 outputs a predetermined output level (low level, high level,
High impedance) to the output control circuit. With the above operation, the same effect as in the first embodiment can be obtained.

Software (firmware) for realizing the above operation will be described with reference to FIG.
5A is a flowchart showing the operation of the PLL circuit of FIG. 4, and FIG. 5B is a flowchart showing the interrupt processing operation.

In FIG. 5 (a), first, the frequency division value for the current programmable divider 2 is set to Nnn, and the changed frequency division value is set to Nn + 1.

Dividing value Nn + 1 in the programmable divider
Is set (step 501), the following operation is performed in response to this.

First, the frequency division value Nn and the frequency division value Nn + 1 are compared. If the frequency division value Nn> Nn + 1 is the result of this comparison, a high level output request signal is sent to the output control circuit 13. (Steps 502 → 503 → 504 → 505). on the other hand,
If the frequency division value Nn <Nn + 1 as a result of the comparison, a low level output request signal is similarly transmitted (step 502 → 503 →
504 → 506).

In step 503, when the frequency division value Nn and the frequency division value Nn + 1 are compared and the two are equal, a high impedance output request signal is issued to the output control circuit 13 to switch to the control similar to the conventional one. (Step 503 → 5
10).

After that, an interrupt is generated after the measurement of the frequency counter 8 is completed (step 507), and the process moves to FIG. In the interrupt processing, the value of the frequency division count buffer 14 is read (step 511), and the read value and RA
The value is compared with the value corresponding to the desired frequency division period set in M17 (step 512). Thereafter, the interrupt processing is resumed (step 513), the process moves to (a) in the figure, and if the results of the above comparison indicate that the two match, interrupt processing is prohibited (step 509) and then the output control circuit 13 is instructed. A high impedance output request signal is issued and the control is switched to the conventional control (step 510).

As a result of the above comparison, if they do not match, the reading of the value of the count buffer 14 by the interrupt processing and the comparison between the read value and the set value of the RAM 17 are continued (step 508).

Since the controller 16 performs the operations shown in FIGS. 5 (a) and 5 (b), the amount of hardware is smaller than that in the first embodiment, and the same effect can be obtained with an inexpensive structure. You can do it.

As described above, according to the present invention, the wasteful high impedance output period that occurs in the conventional circuit until the transition from the unlocked state to the locked state is eliminated, and the high level or By continuing to output the low level signal, the lockup time can be greatly shortened, especially when the frequency division value is greatly changed.

[0063]

As described above, the present invention measures the frequency of the oscillation output signal when the phase comparison result of the oscillation output signal of the voltage controlled oscillator and the reference signal is not output,
By controlling the oscillation frequency of the voltage controlled oscillator according to the measurement result, there is an effect that the lockup time of the PLL can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the PLL circuit of FIG.

FIG. 3 is a characteristic diagram showing a lockup time of the PLL circuit of FIG.

FIG. 4 is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention.

5A is a flowchart showing an operation of the PLL circuit of FIG. 4, and FIG. 5B is a flowchart showing an interrupt processing operation.

FIG. 6 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 7 is a circuit diagram showing an internal configuration of a low pass filter circuit in FIG.

8A and 8B are time charts showing the operation of the PLL circuit of FIG. 6, where FIG. 8A is an operation when the frequency dividing frequency is lower than the reference frequency, and FIG. 8B is a case where the frequency dividing frequency is higher than the reference frequency. And (c) shows the operation when the reference frequency and the divided frequency are equal.

[Explanation of symbols]

 1 Voltage controlled oscillator 2 Programmable divider 3 N value setting register 4 Reference frequency generator 5 Phase comparator 6, 12 Charge pump circuit 7 Low pass filter circuit 8 Dividing frequency counter 9 Frequency counter control circuit 10 Desired period setting register 11 Comparison circuit 13 Output Control Circuit 14 Count Buffer 15 Interrupt Generation Circuit 16 Controller 17 RAM

Claims (4)

[Claims] 1. A voltage control oscillator, and first comparison means for comparing the phases of the oscillation output signal and a reference signal and outputting a comparison result signal according to the comparison result. A PLL circuit that controls the oscillation frequency of the voltage controlled oscillator according to the above, and a measuring unit that measures the frequency of the oscillation output signal when the comparison result signal is not output, and the voltage according to the measurement result. A PLL circuit comprising: a control unit that controls an oscillation frequency of a controlled oscillator. 2. The control means includes second comparing means for comparing the measurement result with a predetermined value, and a first control voltage for increasing the oscillation frequency of the voltage controlled oscillator according to the comparison result. 2. The PLL circuit according to claim 1, further comprising voltage output means for selectively inputting a second control voltage for lowering an oscillation frequency to the voltage controlled oscillator. 3. The measuring means has a clocking means for counting during one cycle of the oscillation output signal, and the second comparing means is constituted so that a predetermined value can be set from the outside, and the predetermined value and the clocking time. 3. The PLL circuit according to claim 2, wherein the count value by the means is compared. 4. The predetermined value is set to a value between the current oscillation frequency of the voltage controlled oscillator and the lock frequency at which the PLL should be locked, and a value near the lock frequency. Item 3. The PLL circuit according to Item 3.