JPH01220523A - Pseudo lock preventing circuit for pll circuit - Google Patents

Abstract

PURPOSE:To prevent a pseudo lock state from being generated by providing an output frequency detection circuit for a voltage controlled oscillator and a correction signal superposition circuit to generate a correction control signal by the output of the detection circuit and to superpose it on the control signal of the voltage controlled oscillator. CONSTITUTION:The output signal A of the terminal Q4 of a down counter 51 is inverted at every count value 8 of a reference signal fi, then, it becomes a signal B, and the signal C of -RC terminal resets an up counter 61 and a latch circuit 81 at the time of detecting the completion of a cycle. The output frequency detection circuit 6 is constituted of a four bit counter 61, and counts the output F0 of the VCO being added via a NAND circuit N while the signal A is set at (1), and when it is f0=2f1, stops counting by controlling the NAND circuit N by using a carrier signal, the inverse of RC. The output of the counter 61, after being processed at a logic circuit 7, is controlled by the signals B and C, and triggers DH and UH are issued from the correction signal superposition circuit 8 including capacitors C1 and C2 and diodes D1 and D2, and they are superposed on the phase signals DF and UF of a charge pump 2, and the control signal S is fluctuated by charging/discharging the capacitance of an LPF3, then, a PLL circuit can be held in a normal lock state.

Description

[Detailed Description of the Invention] [Already Required] Regarding a pseudo-lock prevention circuit for a PLL circuit that is added to prevent the occurrence of a pseudo-lock in a PLL circuit, the present invention is capable of detecting the occurrence of a pseudo-lock state in a voltage controlled oscillator. , applying a signal superimposed on the control voltage of the voltage controlled oscillator,
The purpose is to provide a method for forcibly leaving the pseudo-lock state to avoid the occurrence of a pseudo-lock state, and it uses a phase comparator and a phase comparator that feeds back the output signal output from the voltage controlled oscillator and compares the phase with a reference signal. , an output frequency detection circuit that is connected to a PLL circuit that controls the period of the voltage-controlled oscillator according to a control signal output from the phase comparator, and that detects the output frequency of the voltage-controlled oscillator; The correction signal superimposing circuit generates and sends a correction signal which is converted into a correction signal and superimposed on the control signal 18 of the voltage controlled oscillator.

[Industrial application field]

The present invention relates to a pseudo-lock prevention circuit for a PLL circuit that is added to prevent the occurrence of a pseudo-lock in a PLL circuit.

P L L (Phase-Locked Loop
) circuit is widely used in timing generation circuits for motor speed control, etc.

However, the PLL circuit is a circuit that compares the phases of the reference signal and the output signal and controls the signal period of the voltage-controlled oscillator so that the phases match. If the phases match, unexpected output signals with those periods may be generated.

There is a need for a method to avoid generation of an output signal in such a pseudo-locked state in a PLL circuit.

[Conventional technology]

FIG. 6 is a diagram illustrating a conventional PLL circuit.

[Refer to "Digital PLLIC and its Overview" on page 125 of "rPLL Utilization Guide" published by Seibundo Shinkosha].

As shown in FIG. 6, in the PLL circuit, the reference signal f
By comparing the phase of the output signal fO fed back from the output of the voltage controlled oscillator 4 with the phase of the output signal fO fed back from the output of the voltage controlled oscillator 4, the phase advance signal U, Alternatively, a phase delayed signal is generated.

These signals U and D are input to a charge pump circuit 2, and the charge pump circuit 2 outputs a signal UF that increases or decreases the charge of the capacitor Co (FIG. 7) in the low-pass filter 3 in accordance with the signals U and D.
, generates DF.

The control signal voltage S of the voltage controlled oscillator 4 is changed by increasing or decreasing the charge of the capacitor CO.

The voltage controlled oscillator 4 is controlled by changes in the control signal voltage S so that the output signal fo matches the phase of the reference signal fi.

[Problem to be solved by the invention]

In this conventional PLL circuit, the digital phase comparator to low-pass filter section has a phase transfer characteristic as shown in FIG.

That is, the output of the low-pass filter is in the same state as the output signal fo and the reference signal fi, which are integral multiples of the phase difference 2π.

Therefore, even if the frequencies of the output signal fo and the reference signal fi are in a relationship of - or an integer multiple, the phases are synchronized.
The PLL circuit enters a pseudo-lock state.

That is, the relationship between the two signals is f O = (1/2') f t or fo = 2''-fi (n: integer). In particular, the frequency of the output signal fo and the reference signal fi is -1/2 or False locks are twice as likely to occur, and often occur when the circuit power is turned on.

One way to avoid these pseudo-lock states is to limit the oscillation frequency range of the voltage-controlled oscillator, but CR oscillators are generally used as voltage-controlled oscillators, and oscillations may occur due to variations in constant values of circuit components or temperature fluctuations. It is difficult to limit the frequency range to a desired range.

The present invention was created in view of these points, and detects the occurrence of a pseudo-lock state in a voltage-controlled oscillator, applies a signal superimposed on the control voltage of the voltage-controlled oscillator, and removes the pseudo-lock state from the pseudo-lock state. The purpose of this invention is to provide a method for forcibly leaving the system and avoiding the occurrence of a pseudo-locked state.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention has a PLL circuit as shown in the block diagram showing the principle configuration of FIG.
an output frequency detection circuit 6 that detects the output signal fO of the voltage controlled oscillator 4; and a correction signal superimposition circuit 8 that generates a correction control signal from the output of the output frequency detection circuit 6 and superimposes it on the control signal voltage of the voltage controlled oscillator 4. A false lock prevention circuit 10 is configured.

(Function) In the present invention, the output frequency detection circuit 6 that detects the output frequency within a predetermined cycle of the timing circuit 5 detects the output frequency, and the correction signal superimposition circuit 8 controls the voltage controlled oscillator 4 based on this detection output. The signal voltage S is varied by a superimposed control signal.

This variation in the control signal voltage S forces the voltage controlled oscillator 4 to leave the locked state and transition to another locked state in the direction indicated by the logic signal. In other words, the pseudo lock state is brought to a normal lock state.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the pseudo lock prevention circuit of the PLL circuit of the present invention, FIG. 3 is a diagram explaining timing, and FIG. 4 is a table explaining control logic.

Note that the same reference numerals refer to the same objects throughout the plan.

As shown in FIG. 4, the down counter 51
The frequency of the reference signal fi input to the terminal is counted.

A 4-bit count value is output from the Q1 to Q4 terminals of the down counter 51, and a carry signal is generated from the terminal at (2).

As shown in FIG.
The signal output from the four terminals is inverted every count value of 8, that is, (1000), of the input reference signal fi.

Signal B is an inverted signal of signal A, and signal C is a signal output from a terminal at 100 and is a pulse signal generated when the counter returns to (0000).

Then, the signal C resets the up counter 61 and the latch circuit 81 at the end of the l detection cycle.

The output signal counting circuit 6 includes a 4-bit up counter 61
The up counter 61 is reset by the signal C from the timing circuit 5, and counts the output signal fo applied via the NAND circuit 1IIN while the signal A is rlJ.

The up counter 61 outputs the count value of the output signal fo while the signal A is rlJ from its terminals Ql~4.

And when fowfi, rloooJfo-fi/
2, ro 100Jfo-2fi, r
l 0000J.

However, in the case of fo-2fi, rlooooJ cannot be output with the 4-bit up counter 61, so rl 1
Using the carry signal Hyakuho due to the fact that it became 11J,
The NAND circuit N is controlled to stop the up counter from counting.

The output of the up counter 61 is converted into X and Y signals by the logic circuit 7 according to the following conversion formula.

X-C4・C3+Q4・C3-Q2 Y=Q4・C3・C2・Ql Then, it is set in the latch circuit 81 by the signal B.

FIG. 4 shows a table explaining the control logic of the logic circuit.

Normally, fowfi is the input signal of the logic circuit 7 (1000
), the input signals of the launch circuit 81 are X-o, yo, and the output signals are X'-rlJ, Y'-rOJ.

For example, if fo<fi/2 and the up counter 61 could not be increased to ro 101J or more between "l" of signal A, the input signal of the launch circuit 81 with signal C becomes x-
o, y-o, and the output signal is X'-rOJ
, Y'=rOJ. At this point, the phase delay correction signal DH signal is generated.

Here, the reason why the output range of the up-counter 61 is shifted by 1 from the ideal count value mentioned above is because the up-counter 61 is set. This is because of consideration.

The correction signal superimposition circuit 8 includes a latch circuit 81 and a capacitor C1.
, C2 and the diode D1. D2, and forms a differentiating circuit and a rectifying circuit for the output signal of the launch circuit 81.

Then, only the necessary signal components are converted into trigger pulses DH and UH.
The phase delay signal DF and phase lead signal U output from the charge pump circuit 2 of the PLL circuit to the low-pass filter 3 as
Superimpose it on F.

In this way, the capacitor CO of the low-pass filter shown in FIG. 7 is charged and discharged.

The amount of correction signal superimposition is determined by the output change rate (rise or fall time) of the latch circuit, the capacitance of the differentiator circuit, and the input impedance of the low-pass filter 3. The optimum value is determined by the capacitance of capacitors C1 and C2 of No.8.

The pulse signal generated by the correction signal superimposition circuit 8 temporarily increases or decreases the electric charge of the capacitance of the low-pass filter 3, so that the control signal voltage S of the voltage-controlled oscillator 4 fluctuates, and the frequency of the voltage-controlled oscillator 4, i.e. fo will be pulled into the frequency of the normal lock state.

〔Effect of the invention〕

As is clear from the above explanation, since the output signal frequency is constantly detected according to the present invention, it is possible to avoid a false lock state even when an unexpected abnormality or temperature fluctuation occurs even when the power is not turned on. This makes it possible to construct a highly reliable and stable PLL circuit, which is extremely useful industrially.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a pseudo-lock prevention circuit for a PLL circuit of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a diagram explaining timing, Figure 4 is a table explaining the control logic, Figure 5 is a diagram explaining the transfer characteristics from the digital phase comparator to the low-pass filter section, Figure 6 is a diagram explaining a conventional PLL circuit, and Figure 7 is a diagram explaining the low-pass filter section. This is an example of a filter circuit diagram. In the figure, 1 is a digital phase comparator, 4 is a voltage controlled oscillator, 6 is an output frequency detection circuit, 8 is a correction signal superimposition circuit, and 100 is a PLL circuit. The principle of non-invention To the bed tne f1 et al. 7 Figure 1 Figure 2
Picture stitch mpvPiX' G K198t3H. Fig. 4 Fig. 5 ES, Example of filter mounting distance R Fig. 7

Claims (1)

[Claims] A phase comparator (1) that feeds back the output signal output from the voltage controlled oscillator (4) and compares the phase with a reference signal; an output frequency detection circuit (6) connected to the PLL circuit (100) that controls the cycle and detects the output frequency of the voltage controlled oscillator (4); and converts the output of the output frequency detection circuit (6) into a correction signal. A correction signal superimposition circuit (8) for generating and sending out a correction signal to be superimposed on the control signal of the voltage controlled oscillator (4).