JP2008060688A - Phase-locked loop circuit and signal generator unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit and a signal generator unit having the above circuit, capable of promptly outputting a signal of desired frequency without greatly increasing the circuit scale. <P>SOLUTION: A phase-locked loop circuit 1 includes a PLL 10 and a pretune signal generator 20 for generating a pretune signal S26 to bring the frequency of a signal S1 output from the PLL 10 into the frequency of signal S1 into the tuning frequency band of the PLL 10. The pretune signal generator 20 includes a counter 21 for counting the frequency of the signal S1 op from the PLL 10, an error decision section 23 for deciding whether or not an error value indicative of an error between the frequency of the signal S1 counted by the counter 21 and the pretune frequency is smaller than a predetermined threshold, and a memory 25 for storing the pretune signal S26 given to the PLL 10 when the error value becomes smaller than the predetermined threshold by the decision in the error decision section 23. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase-locked loop circuit and a signal generator including the circuit.

  The signal generator is an apparatus that generates a standard signal in a wide frequency band based on an internal or external reference signal. A typical example of this signal generator is a PLL frequency synthesizer including a phase-locked loop circuit (PLL (Phase Locked Loop) circuit). In recent years, a phase-locked loop having a pretune circuit for drawing the frequency of an output signal at high speed into the tuning frequency band of the phase-locked loop circuit has been developed.

  FIG. 8 is a block diagram showing a configuration of a conventional phase-locked loop circuit. As shown in FIG. 8, the conventional phase-locked loop circuit 100 includes an oscillator 101, a phase detector 102, a loop filter 103, an adder 104, a voltage controlled oscillator (hereinafter referred to as VCO) 105, and a pretune circuit 106. The output signal of the oscillator 101 is input to one input terminal of the phase detector 102, and the output signal of the phase detector 102 is input to one input terminal of the adder 104 via the loop filter 103. The output signal of the adder 104 is input to the VCO 105 as a control signal. The output signal of the VCO 105 is output to the outside, and is input to the other input terminal of the adder 104 via the other input terminal of the phase detector 102 and the pretune circuit 106.

  FIG. 9 is a block diagram showing a configuration of pretune circuit 106 in FIG. In FIG. 9, the same blocks as those shown in FIG. 8 are denoted by the same reference numerals. As shown in FIG. 9, the pretune circuit 106 includes a counter 111, a reference frequency source 112, a reciprocal count type reference counter 113, and a comparator 114. The counter 111 counts up the frequency of the output signal of the VCO 105 as a clock, and outputs a divided pulse P101 every time a certain number is counted. The reference frequency source 112 outputs a reference pulse P100 having a predetermined frequency.

  The reference counter 113 receives the divided pulse P101 output from the counter 111 and the reference pulse P100 output from the reference frequency source 112, and the reference frequency source 112 while the divided pulse P101 is output from the counter 111. The reference pulse P100 is counted and the count data is output. The comparator 114 compares the count data output from the reference counter 113 with the frequency setting value input via the setting terminal T101, and the frequency indicated by the count data is separated from the frequency setting value by a predetermined frequency. If so, a control pulse for driving the switch 108 is output. One end of the switch 108 is connected to the current source 107, and the other end of the switch 108 is connected to a connection point between the VCO 105 and the capacitor 109.

  In the above configuration, when a signal is output from the VCO 105, this signal is output to the outside and input to the other input terminal of the phase detector 102 and the pretune circuit 106. When the output signal of the VCO 105 is input to the pretune circuit 106, the frequency is counted by the counter 111 and a divided pulse P101 is output to the reference counter 113 every time a predetermined number is counted. When the divided pulse P101 is input, the reference counter 113 counts the reference pulse P100 output from the reference frequency source 112 and outputs the count data.

The comparator 114 compares the frequency indicated by the count data of the reference counter 113 with the frequency setting value input via the setting terminal T101, and the frequency indicated by the count data is separated from the frequency setting value by a predetermined frequency. If so, a control pulse for driving the switch 108 is output. When the switch 108 is driven and turned on, the control voltage of the VCO 105 rises, thereby increasing the frequency of the output signal of the VCO 105. The pretune circuit 106 repeats the above operation until the frequency of the output signal of the VCO 105 falls within a preset frequency band, so that the frequency of the signal output from the phase locked loop circuit 100 is tuned to the phase locked loop circuit 100. It will be drawn into the frequency band at high speed. For details of the conventional phase-locked loop circuit described above, refer to the following patent documents.
JP 2004-158940 A

  By the way, in the pretune circuit 106 included in the conventional phase locked loop circuit 100 described above, when the divided pulse P101 is output from the counter 111, the reference pulse P100 output from the reference frequency source 112 is counted by the reference counter 113. is doing. For this reason, a reference frequency 112 for outputting a reference pulse P100 having a frequency higher than that of the frequency-divided pulse P101 output from the counter 111 is required. Further, in order to stabilize the frequency, the oscillation frequency of the crystal oscillator is used as a reference. It is necessary to provide a phase-locked loop circuit, and the circuit scale is expected to increase.

  In the conventional pretune circuit 106, the count and control of the switch 108 are repeated until the frequency of the signal output from the phase locked loop circuit 100 falls within the set frequency band. For this reason, there is a problem that it takes time until the frequency of the signal output from the phase-locked loop circuit 100 is converged to the target frequency to obtain movement synchronization.

  The present invention has been made in view of the above circumstances, and a phase-locked loop circuit that can output a signal having a desired frequency at an early stage without causing a significant increase in circuit scale, and a signal generation including the circuit An object is to provide an apparatus.

In order to solve the above problems, a phase-locked loop circuit according to the present invention includes a control signal generation unit (14) that generates a control signal (S12) and a frequency corresponding to the control signal output from the control signal generation unit. A phase locked loop circuit (1, 2) comprising an oscillator (15) for outputting a signal (S1) having a detector (21, 22, 23) for detecting a frequency of a signal output from the oscillator; An error value (ΔF) indicating a difference between a frequency detected by the detection unit and a preset frequency (Fp) that defines an initial value of a frequency of a signal output from the oscillator is smaller than a predetermined value (ΔFt). The processing units (23, 24) for giving the control signal generation unit a control value (S26) for varying the control signal generated by the control signal generation unit, and the error value is smaller than the predetermined value. Before And a storage unit (25) for storing the control value given to the control signal generation unit.
According to the present invention, the frequency of the signal output from the oscillator is detected by the detector, and an error value indicating the difference between the detected frequency and the preset frequency is obtained, and the error value is made smaller than the predetermined value. The control value given to the control signal generator is varied, and the control value when the error value is smaller than the predetermined value is stored in the storage unit.
The phase-locked loop circuit of the present invention includes a comparison unit (12) that compares a frequency reference signal (S0) having a predetermined frequency with a signal output from the oscillator, the comparison unit, and the control signal generation unit. And a switch part (13) provided between the two.
In the phase-locked loop circuit of the present invention, when the processing unit generates the control value to be stored in the storage unit, the switch unit is opened.
The phase-locked loop circuit of the present invention further includes a frequency dividing circuit (11) that divides the frequency reference signal by a predetermined frequency dividing ratio, and the detection unit gates a signal output from the frequency dividing circuit. A counter (21) that counts the frequency of a signal output from the oscillator as a signal is provided.
The phase-locked loop circuit according to the present invention is characterized in that, when the processing unit starts an operation as a phase-locked loop, the control value stored in the storage unit is given to the control signal generating unit. Yes.
The phase-locked loop circuit of the present invention further includes a timer unit (17) that closes the switch unit after a predetermined time has elapsed since the control value stored in the storage unit is given to the control signal generation unit. It is characterized by that.
The phase locked loop circuit of the present invention is characterized in that the control signal generator operates as a loop filter during operation as a phase locked loop.
Furthermore, the phase-locked loop circuit of the present invention includes a conversion unit (41) that converts a signal output from the oscillator into a signal having a lower frequency, and only a signal having a necessary frequency from the signal converted by the conversion unit. And a filter unit (42) that outputs the signal to the comparison unit.
A signal generator according to the present invention includes any one of the phase locked loop circuits described above, and generates a standard signal having a predetermined frequency using the signal (S1) output from the phase locked loop circuit. It is a feature.

According to the present invention, the detection unit detects the frequency of the signal output from the oscillator, obtains an error value indicating the difference between the detected frequency and the preset frequency, and the error value is smaller than a predetermined value. As described above, the control value given to the control signal generation unit is varied, and the control value when the error value is smaller than the predetermined value is stored in the storage unit. When starting the operation as a phase-locked loop, the control value stored in the storage unit is given to the control signal generation unit, so that the frequency of the signal output from the controlled oscillator in a very short time is desired. There is an effect that it can be set to a frequency of.
In addition, since the frequency of the signal output from the oscillator is detected by using the signal obtained by dividing the frequency reference signal by the frequency dividing circuit as the gate signal, it is necessary to separately include an oscillator or the like to generate the gate signal. Therefore, there is an effect that the circuit scale and cost can be reduced.
In addition, since the detection unit that detects the frequency of the signal output from the oscillator is provided, it is not necessary to prepare a frequency counter outside when storing the control value in the storage unit. For this reason, while manufacturing a signal generator provided with a phase-locked loop circuit, an equipment burden is reduced, and a control value can be obtained without unpacking the signal generator.
In addition, the signal output from the oscillator is converted into a signal with a lower frequency, and only the signal with the required frequency is passed through the converted signal and output to the comparison unit, resulting in a significant increase in circuit scale. However, there is an effect that the frequency of the signal output from the oscillator can be controlled with higher accuracy.

  Hereinafter, a phase locked loop circuit and a signal generator according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a phase locked loop circuit according to an embodiment of the present invention. 1 is provided in a signal generator such as a PLL frequency synthesizer. As shown in FIG. 1, the phase-locked loop circuit 1 of the present embodiment includes a PLL unit 10 that outputs a signal S1 that has the same frequency and phase as the input frequency reference signal S0, and a signal S1 that is output from the PLL unit 10. And a pretune signal generation unit 20 for generating a pretune signal for pulling the frequency of the frequency into the tuning frequency band of the PLL unit 10 at high speed. Note that the frequency of the frequency reference signal S0 is, for example, 1 GHz.

  The PLL unit 10 includes a frequency divider 11, a phase frequency comparator 12 (comparator), a switch 13 (switch unit), a frequency control signal generator 14 (control signal generator), a control oscillator 15 (oscillator), a digital / An analog converter (hereinafter referred to as a D / A converter) 16 and a timer 17 (timer unit) are provided. The frequency dividing circuit 11 divides the frequency reference signal S0 by a frequency dividing ratio specified by the frequency division setting signal S2 input from the outside. The phase frequency comparator 12 compares the frequency and phase of the signal S11 output from the frequency dividing circuit 11 and the signal S1 output from the control oscillator 15, and outputs a signal indicating the comparison result. The switch 13 is connected to the output terminal of the phase frequency comparator 12 and one input terminal of the frequency control signal generation circuit 14, and corresponds to the pretune switch control signal S 27 output from the pretune signal generation unit 20. The space between them is opened or closed.

  The frequency control signal generation circuit 14 is output from the control type oscillator 15 based on the signal S11 output from the phase frequency comparator 12 via the switch 13 and the signal S13 output from the D / A converter 16. A frequency adjustment signal S12 (control signal) for adjusting the frequency of the signal S1 is output. The controlled oscillator 15 outputs a signal S1 having a frequency corresponding to the frequency adjustment signal S12 output from the frequency control signal generation circuit 14. Here, the control type oscillator 15 may be either one that controls the frequency according to the input voltage value or one that controls the frequency according to the input current value, and the frequency adjustment signal S12. May be a voltage or a current according to the controlled oscillator 15. The signal S1 output from the controlled oscillator 15 is output to the outside, fed back to the phase frequency comparator 12, and further input to the pretune signal generator 20.

  The D / A converter 16 receives the pretune signal S26 and the load signal S24 from the pretune signal generator 20, and outputs the pretune signal S26 when the load signal S24 is output from the pretune signal generator 20. The pretune signal S26 is captured and converted into an analog signal, and is output to the frequency control signal generation circuit 14 as a signal S13. The timer 17 receives the load signal S24 from the pretune signal generation unit 20, receives the load signal S24 from the pretune signal generation unit 20, measures the time for a predetermined time, and indicates when the time measurement is completed. The status signal S14 is output to the pretune signal generation unit 20.

  The pretune signal generation unit 20 includes a counter 21 (detection unit), a counter value register 22 (detection unit), an error determination unit 23 (detection unit, processing unit), a processing unit 24, a memory 25 (storage unit), a D / A A value register 26 and an OR circuit 27 are provided. The counter 21 receives a counter enable setting signal S3 for enabling the count operation of the counter 21, a signal S11 output from the frequency divider 11 of the PLL unit 10, and a signal S1 output from the control oscillator 15. When the counter enable setting signal S3 is enabled, the signal S1 output from the control oscillator 15 is counted using the signal S11 output from the frequency divider circuit 11 as a gate signal. The counter 21 outputs a count end signal S22 every time the signal S11 output from the frequency dividing circuit 11 falls. The counter value register 22 receives the counter value S21 of the counter 21 and the count end signal S22, and takes in the counter value S21 and temporarily holds it when the count end signal S22 is input.

  When the error calculation command signal S4 is input from the outside, the error determination unit 23 is the difference between the frequency Fo of the signal S1 output from the PLL unit 10 and the pretune frequency Fp (preliminary setting frequency) input from the outside. Is determined, and it is determined whether or not the error value ΔF is greater than or equal to a preset threshold value ΔFt. The error determination unit 23 includes a counter value S23 held in the counter value register 22, a count end signal S22 output from the counter 21, a frequency division setting signal S2, an error calculation command signal S4, A conversion coefficient signal S5 indicating a conversion coefficient K for converting a counter value into a frequency, a threshold signal S6 indicating a threshold ΔFt, and a pretune frequency signal S7 indicating a pretune frequency Fp are input. Specifically, the following procedure is performed. The above error value ΔF is obtained. It is also possible to convert the frequency into a counter value using the conversion coefficient K.

  First, when the error calculation signal S4 is input, the error determination unit 23 takes in the counter value S23 held in the counter value register 22 when the count end signal S22 from the counter 21 is input. Next, the counter value taken in using the conversion coefficient K indicated by the conversion coefficient signal S5 is converted into a frequency, and this frequency is multiplied by the reciprocal of the frequency division ratio specified by the frequency division setting signal S2, so that the PLL unit 10 The frequency Fo of the signal S1 output from is obtained (detected). Next, a difference between the obtained frequency Fo and the pretune frequency Fp indicated by the pretune frequency signal S7 is calculated to obtain an error value ΔF = | Fo−Fp |. Then, it is determined whether or not the error value ΔF is greater than or equal to a threshold value ΔFt indicated by the threshold signal S6.

  The processing unit 24 determines the data (pretune signal S26) to be held in the D / A value register 16, stores the data in the memory 25 based on the determination result of the error determination unit 23, and causes the PLL circuit unit 10 to The opening / closing process of the provided switch 13, the process of fetching the pretune signal S 16 from the D / A value register 26, and the process of starting the timer 17 are performed. The memory 25 inputs data (pretune signal S26) held in the D / A value register 26 when the error value ΔF is smaller than the threshold value ΔFt under the control of the processing unit 24 from the outside. And stored in association with the pretune frequency Fp indicated by the pretune frequency signal S7.

  The D / A value register 26 holds the data determined by the processing unit 24 (pretune signal S26 to be given to the D / A converter 16 of the PLL unit 10). The OR circuit 27 calculates a logical sum of the interrupt signal S25 output from the processing unit 24 and the timer status signal S14 output from the timer 17 of the PLL unit 10, and the calculation result is used as a pretune switch control signal S27. Output to the switch 13 of the PLL unit 10.

  Here, an internal configuration of the frequency control signal generation circuit 14 provided in the PLL unit 10 will be described. FIG. 2 is a diagram illustrating an example of an internal configuration of the frequency control signal generation circuit 14 provided in the PLL unit 10. In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 2, the frequency control signal generation circuit 14 includes a resistor 31, an operational amplifier 32, a resistor 33, a capacitor 34, and a switching circuit 35. A resistor 31 is connected between the negative input terminal of the operational amplifier 32 and the switch 13, and the positive input terminal of the operational amplifier 32 is grounded. Depending on the type of phase frequency comparator 12 (for example, charge pump type), the positive input terminal of the operational amplifier 32 may be a fixed voltage. A resistor 33 and a capacitor 34 are connected in series between the output terminal and the negative input terminal of the operational amplifier 32. A loop filter is configured by the circuit including the resistor 31, the operational amplifier 32, the resistor 33, and the capacitor 34.

  The switching circuit 35 includes a circuit in which a resistor 36 and a switch 37 are connected in series between the output terminal and the negative input terminal of the operational amplifier 32 and connected in parallel to the circuit including the resistor 33 and the capacitor 34, and a switch 37 and a D / A converter 16, and a circuit in which a switch 38 and a resistor 39 are connected in series. The switches 37 and 38 are controlled to be opened and closed by a pretune switch control signal S27 output from the OR circuit 27. In other words, the switches 37 and 38 are closed when the pretune switch control signal S27 is output from the OR circuit 27, and are opened when the pretune switch control signal S27 is not output. .

  When the switches 37 and 38 are in the open state, the frequency control signal generation circuit 14 operates as a loop filter by the circuit including the resistor 31, the operational amplifier 32, the resistor 33, and the capacitor 34 as described above. On the other hand, when the switches 37 and 38 are in the closed state, the frequency control signal generation circuit 14 operates as an inverting amplifier. When the switches 37 and 38 are in the closed state, the capacitor 34 is charged according to the signal S13 output from the D / A converter 16 (the convergence value is determined by the ratio of the resistor 39 and the resistor 36). The frequency adjustment signal S12 can be varied by the signal from the D / A converter 16. When the frequency control signal generation circuit 14 operates as a loop filter, the D / A converter 16 is electrically disconnected from the frequency control signal generation circuit 14. For this reason, noise superimposed on the signal S13 output from the D / A converter 16 does not adversely affect the signal S1 output from the PLL unit 10.

  Next, the operation of the phase locked loop circuit 1 of the present embodiment will be described. Here, the operation of the phase-locked loop circuit 1 of the present embodiment includes a first operation for obtaining an initial value of the pretune signal S16 to be supplied to the D / A converter 16 of the PLL unit 10, and an input frequency reference signal S0. The signal S1 having the same frequency and phase can be broadly classified into a second operation in which the PLL unit 10 generates the signal S1. Hereinafter, the first operation and the second operation will be described in order.

<First operation>
FIG. 3 is a flowchart showing a first operation of the phase-locked loop circuit 1, and FIG. 4 is a timing chart showing signal waveforms at various parts during the first operation of the phase-locked loop circuit 1. Note that a frequency reference signal S0 having a predetermined frequency (for example, 1 GHz) and a frequency division setting signal S2 are input to the PLL unit 10 from the outside, and the frequency reference signal S0 is divided by the frequency dividing circuit 11. Assume that frequency division is performed at a frequency division ratio specified in S2.

  When the first operation of the phase locked loop circuit 1 is started, an interrupt signal S25 is first output from the processing unit 24 provided in the pretune signal generation unit 20. The interrupt signal S25 is output to the PLL unit 10 as the pretune switch control signal S27 via the OR circuit 27. Thereby, the switch 13 provided in the PLL unit 10 is opened (step ST11). It should be noted that the switches 38 and 39 provided in the frequency control signal generation circuit 14 shown in FIG. 2 are closed when the pretune switch control signal S27 is output, whereby the frequency control signal generation circuit 14 operates as an inverting amplifier. To do. During the first operation, the interrupt signal S25 is always output from the processing unit 24. As shown in FIG. 4, the pretune switch control signal S27 is always in the H (high) state.

  Next, the processing unit 24 reads data (default data) stored in association with the pretune frequency Fp indicated by the pretune frequency signal S7 input from the outside (step ST12), and reads the read data as D / The value is set in the A value register 26 (step ST13). Next, the processing unit 24 outputs the load signal S24 and causes the D / A converter 16 of the PLL unit 10 to capture the data (pretune signal S26) set in the D / A value register 26 (step ST14). The D / A converter 16 converts the fetched data into an analog signal and outputs it as a signal S13.

  When the signal S13 from the D / A converter 16 is input, the capacitor 34 (see FIG. 2) provided in the frequency control signal generation circuit 14 is charged. Thereby, the frequency adjustment signal S12 corresponding to the set amplification factor is output from the frequency control signal generation circuit 14 (step ST15). The control oscillator 15 outputs a signal S1 having a frequency corresponding to the frequency adjustment signal S12 (step ST16).

  Next, the counter enable signal S3 input from the outside is enabled (step ST17). Accordingly, the counter 21 starts counting the signal S1 output from the control oscillator 15 using the signal S11 output from the frequency divider circuit 11 as a gate signal (step ST18). Here, as shown in FIG. 4, the signal S11 output from the frequency divider circuit 11 has a longer cycle than the signal S1 output from the controlled oscillator 15, and the counter 21 uses the signal S11 as a gate signal to generate the signal S1. Count. Referring to FIG. 4, while the signal S11 is in the H (high) state, the counter value S21 of the counter 21 increases every time the signal S1 is input, and while the signal S11 is in the L (low) state. It can be seen that the counter value S21 of the counter 21 is maintained.

  When the signal S11 falls during the counting of the signal S1, the counter 21 outputs the count end signal S22 to the counter value register 22 and the error determination unit 23. Each time the count end signal S22 from the counter 21 is input, the counter value register 22 takes in the counter value S21 of the counter 21 and temporarily holds it (step ST19). Next, the error determination unit 23 determines whether or not the count end signal S22 output from the counter 21 has been received twice or more after the error calculation signal S4 is input (step ST20). The error calculation signal S4 is input to the error determination unit 23 at the same time when the counter enable signal S3 is enabled or after a predetermined time has elapsed since the counter enable signal S3 was enabled. If the determination result in step ST20 is “NO”, the process returns to step ST18.

  On the other hand, when the determination result in step ST20 is “YES”, the error determination unit 23 obtains (detects) the frequency Fo of the signal S1 output from the controlled oscillator 15 (step ST21). Specifically, first, the error determination unit 23 takes in the counter value S23 held in the counter value register 22 when the count end signal S22 from the counter 21 is input twice or more. Next, the counter value taken in using the conversion coefficient K indicated by the conversion coefficient signal S5 is converted into a frequency, and this frequency is multiplied by the reciprocal of the frequency division ratio specified by the frequency division setting signal S2, so that the PLL unit 10 The frequency Fo of the signal S1 output from is obtained.

  Next, the error determination unit 23 calculates the difference between the frequency Fo obtained in step ST21 and the pretune frequency Fp indicated by the pretune frequency signal S7 input from the outside to obtain an error value ΔF = | Fo−Fp |. Obtained (step ST22). Then, it is determined whether or not the obtained error value ΔF is equal to or greater than a threshold value ΔFt indicated by a threshold signal S6 input from the outside (step ST23).

  If the determination result in step ST23 is “YES”, the error determination unit 23 uses the conversion coefficient K indicated by the conversion coefficient signal S5 input from the outside to counter the error value ΔF obtained in step ST22. The data is converted into a value and the data held in the D / A value register 26 is read out. Then, the converted counter value is subtracted from the read data (step ST24).

  Next, the error determination unit 23 passes the value obtained in step ST24 to the processing unit 24 (step ST25), and the processing unit 24 sets the value passed from the error determination unit 23 in the D / A value register 26. (Step ST26). When the above processing is completed, the processing unit 24 outputs the load signal S24 and causes the D / A converter 16 of the PLL unit 10 to capture the data (pretune signal S26) set in the D / A value register 26. (Step ST14). The D / A converter 16 converts the captured data into an analog signal and outputs it as a signal S13, and a frequency adjustment signal S12 corresponding to the signal S13 is output from the frequency control signal generation circuit 14 (step ST15). The control oscillator 15 outputs a signal S1 having a frequency corresponding to the frequency adjustment signal S12 (step ST16).

  In step ST14, when the processing unit 24 outputs the load signal S24, the data (new pretune signal S26) newly set in the D / A value register 26 is input to the PLL unit 10, thereby As shown in FIG. 4, the frequency Fo of the signal S1 output from the controlled oscillator 15 approaches the pretune frequency Fp. When the determination result in step ST23 is “NO”, that is, when the error value ΔF is smaller than the threshold value ΔFt, the processing unit 24 stores the data set in the D / A value register 26. Then, it is stored in the memory 25 in association with the pretune frequency Fp indicated by the pretune frequency signal S7 input from the outside (step ST27). Through the above processing, the initial value of the pretune signal S16 to be given to the D / A converter 16 of the PLL unit 10 is obtained.

<Second operation>
FIG. 5 is a flowchart showing a second operation of the phase-locked loop circuit 1, and FIG. 6 is a timing chart showing signal waveforms at various parts during the second operation of the phase-locked loop circuit 1. When the second operation of the phase-locked loop circuit 1 is started, first, processing for determining the frequency Fo of the signal S1 output from the PLL unit 10 is performed (step ST31). In this processing, for example, when the user inputs the frequency Fo of the signal S1 by operating the operation unit (not shown) of the signal generator provided with the phase locked loop circuit 1, the frequency reference input to the PLL unit 10 Processing for determining the frequency of the signal S0 is performed. Here, it is assumed that the frequency of the frequency reference signal S0 is, for example, 1 GHz.

  Next, a process of setting the pretune frequency Fp corresponding to the frequency Fo determined in step ST31 in the processing unit 24 is performed (step ST32). Specifically, a control device (not shown) of the signal generator provided with the phase locked loop circuit 1 obtains a pretune frequency Fp corresponding to the frequency Fo of the input signal S1, and this pretune frequency Fp. Is output to the processing unit 24 of the pretune signal generation unit 20, so that the pretune frequency Fp is set in the processing unit 24. The specific method for obtaining the pretune frequency Fp is, for example, a pretune frequency obtained by subtracting a predetermined frequency from the frequency Fo of the input signal S1 within a range that falls within the tuning frequency band of the PLL unit 10. A method for obtaining Fp is conceivable. The pretune frequency Fp is not limited to this example, and any other method can be used.

  Next, the processing unit 24 of the pretune signal generation unit 20 reads data corresponding to the pretune frequency Fp indicated by the input pretune frequency signal S7 from the memory 25 (step ST33), and reads the read data as D / A. The value is set in the value register 26 (step ST34). Next, the processing unit 24 outputs a load signal S24, causes the D / A converter 16 of the PLL unit 10 to take in the data (pretune signal S26) set in the D / A value register 26, and the PLL unit 10 The timer 17 is started (step ST35).

  Here, as shown in FIG. 6, during the second operation of the phase locked loop circuit 1, the counter 21 of the pretune signal generator 20 is not operating because the counter enable signal S <b> 3 is disabled. The counter value S21 and the count end signal S22 do not change. Further, when the load signal S24 is output from the processing unit 24 of the pretune signal generation unit 20, the timer 17 is started. Therefore, the timer status signal S14 is output until the timer 17 finishes counting the predetermined period T1. . As a result, the pretune switch control signal S27 enters the H (high) state, and the switch 13 provided in the PLL unit 10 enters the open state.

  When the switch 13 is in the open state, the D / A converter 16 converts the fetched data into an analog signal and outputs it as a signal S13. When this signal S13 is input to the frequency control signal generation circuit 14, a capacitor 34 (see FIG. 2) provided in the frequency control signal generation circuit 14 is charged. Thereby, the frequency adjustment signal S12 according to the set amplification factor is output from the frequency control signal generation circuit 14 (step ST36). The control oscillator 15 outputs a signal S1 having a frequency corresponding to the frequency adjustment signal S12.

  Next, the control device (not shown) of the signal generator provided with the phase locked loop circuit 1 sets the frequency division setting signal S2 (step ST37). Here, since the second operation is an operation in which the PLL unit 10 generates a signal S1 having the same frequency and phase as the input frequency reference signal S0, the frequency dividing ratio of the frequency dividing circuit 11 is “1” (that is, , A value that does not divide the frequency reference signal S0).

  When the timer 17 is measuring time, the pretune switch control signal S27 output from the OR circuit of the pretune signal generation unit 20 is in the H (high) state, and the switch 13 is maintained in the open state. Then, the frequency Fo of the signal S1 output from the controlled oscillator 15 approaches the pretune frequency Fp as shown in FIG. 6, and finally becomes equal to the pretune frequency Fp. (Step ST38).

  On the other hand, when the timer 17 finishes counting the predetermined time T1, the timer status signal S14 stops. As a result, the pretune switch control signal S27L (low) state is entered, and the switch 13 of the PLL unit 10 is turned on. Thus, the output terminal of the phase frequency comparator 12 and the output terminal of the frequency control signal generation circuit 14 are electrically connected, and the signal S11 output from the frequency divider circuit 11 and the signal S1 output from the control oscillator 15 A signal indicating the frequency and phase comparison result is input to the frequency control signal generation circuit 14, and the PLL unit 10 operates as a phase locked loop. As a result, the frequency and phase of the signal S1 output from the controlled oscillator 15 are synchronized with the frequency and phase of the frequency reference signal S0, and the frequency of the signal S1 output from the controlled oscillator 15 is as shown in FIG. The frequency Fo set in step ST31 is obtained.

  Here, since the frequency of the signal S1 output from the control type oscillator 15 is equal to the pretune frequency Fp during the period T1 in which the timer 17 is measuring time, it becomes the frequency Fo set in step ST31. The time until is very short. That is, the time until the frequency of the signal S1 output from the controlled oscillator 15 becomes the frequency Fo set in step ST31 is determined by the period T1 and the period T2 shown in FIG. The periods T1 and T2 can be arbitrarily determined depending on the loop band of the phase locked loop. Here, since the period T1 is about 200 μsec and the period T2 is about 100 μsec, the frequency S of the signal S1 output from the controlled oscillator 15 can be set to the frequency Fo set in step ST31 in a very short time.

  Next, a modified example of the phase locked loop circuit according to the embodiment of the present invention will be described. FIG. 7 is a block diagram showing a main configuration of a modified example of the phase-locked loop circuit according to one embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the structure same as the structure of the phase locked loop circuit 1 shown in FIG. The phase locked loop circuit 2 illustrated in FIG. 7 includes a PLL unit 40 and a pretune signal generation unit 20. The pretune signal generator 20 included in the phase locked loop circuit 2 has the same configuration as that shown in FIG. On the other hand, the PLL unit 40 included in the phase-locked loop circuit 2 has a configuration in which a down converter 41 (conversion unit) and a low-pass filter 42 (filter unit) are included in the PLL unit 10 shown in FIG. The difference is that a frequency reference signal S10 is input in addition to the signal S0.

  The frequency of the frequency reference signal S0 input to the PLL unit 40 is, for example, 100 MHz, and the frequency of the frequency reference signal S10 input to the PLL unit 40 is, for example, 1 GHz. The down converter 41 receives the signal S1 output from the controlled oscillator 15 and the frequency reference signal S10, and down-converts the signal S1 based on the frequency reference signal S10. For example, if the frequency of the signal S1 output from the controlled oscillator 15 is 1.01 GHz, a signal having a frequency difference (10 MHz) between the signal S1 and the frequency reference signal S10 is output.

  The low-pass filter 42 is connected to the output terminal of the down converter 41 and one input terminal of the phase frequency comparator 12, and passes only a signal having a necessary frequency among the signals output from the down converter 41. Then, unnecessary components are removed and output to the phase frequency comparator 12. The output of the down converter 41 is also input to the counter 21 of the pretune signal generation unit 20. When the frequency of the signal output from the down converter 41 is 10 MHz, the frequency dividing ratio of the frequency dividing circuit 11 is set to 1/10, for example. As a result, the frequency of the signal S11 output from the frequency divider circuit 11 is 10 MHz, and a signal having a frequency of 10 MHz is input to both input terminals of the phase frequency comparator 12.

  The phase-locked loop circuit 2 configured as described above down-converts the signal S1 output from the controlled oscillator 15 by the down-converter 41 based on the frequency reference signal S10, and passes the down-converted signal through the low-pass filter 42. Output to the phase frequency comparator 12 for feedback. Since the down-converted signal is fed back, the frequency of the signal output from the controlled oscillator 15 can be controlled with higher accuracy. Further, since the signal down-converted by the down-converter 41 is used as the input of the counter 21, even if the frequency of the frequency reference signal S10 is high (for example, 1 GHz), a high speed such as GaAs-MMIC (gallium arsenide-monolithic microwave integrated circuit) is used. It is not necessary to use an expensive IC that operates, and cost and circuit scale can be reduced.

  As described above, in the present embodiment, the frequency of the signal S1 output from the controlled oscillator 15 is made equal to the pretune frequency Fp during the period T1 when the timer 17 measures time, and then the switch 13 is turned on. Moved on and synchronized. For this reason, the frequency of the signal S1 output from the controlled oscillator 15 can be set to the desired frequency Fo in a very short time.

  Further, the signal S11 obtained by dividing the frequency reference signal S0 necessary for the phase-locked loop is used as the gate signal of the counter 21 used when obtaining the initial value of the pretune signal S26. For this reason, it is not necessary to separately incorporate an oscillator or the like in order to generate the gate signal, and the circuit scale and cost can be reduced. Further, in this embodiment, since the pretune signal generation unit 20 is provided with a counter 21 that counts the frequency of the signal S1 output from the controlled oscillator 15, when the initial value of the pretune signal S26 is obtained, There is no need to provide a frequency counter. For this reason, an equipment burden is reduced when manufacturing a signal generator having a phase locked loop circuit, and an initial value of the pretune signal S26 can be obtained without unpacking the signal generator.

  The phase-locked loop circuit and the signal generator according to one embodiment of the present invention have been described above. However, the present invention is not limited to the above-described embodiment, and can be freely modified within the scope of the present invention. For example, the frequency control signal generation circuit 14 is not limited to the circuit shown in FIG. 2, and can be realized by other circuits having the same function. Moreover, in the said embodiment, although the error determination part 23 and the process part 24 were represented by the separate block, it is good also as a block which put these functions together. Furthermore, the signal generator of the present invention is not limited to the PLL frequency synthesizer, and may be any apparatus that includes the phase-locked loop circuit of the present invention and generates a standard signal using a signal output from this circuit.

It is a block diagram which shows the principal part structure of the phase locked loop circuit by one Embodiment of this invention. 2 is a diagram illustrating an example of an internal configuration of a frequency control signal generation circuit 14 provided in a PLL unit 10. FIG. 3 is a flowchart showing a first operation of the phase-locked loop circuit 1. 3 is a timing chart showing signal waveforms at various parts during a first operation of the phase-locked loop circuit 1; 4 is a flowchart showing a second operation of the phase-locked loop circuit 1. FIG. 6 is a timing chart showing signal waveforms at various parts during the second operation of the phase locked loop circuit 1. It is a block diagram which shows the principal part structure of the modification of the phase locked loop circuit by one Embodiment of this invention. It is a block diagram which shows the structure of the conventional phase-locked loop circuit. It is a block diagram which shows the structure of the pretune circuit 106 in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Phase-locked loop circuit 11 Divider circuit 12 Phase frequency comparator 13 Switch part 14 Frequency control signal generation circuit 15 Control type oscillator 17 Timer 21 Counter 22 Counter value register 23 Error judgment part 24 Processing part 25 Memory 41 Down converter 42 Low-pass filter Fp Pretune frequency S0 Frequency reference signal S1 signal S12 Frequency adjustment signal S26 Pretune signal ΔF Error value ΔFt Threshold

Claims (9)

In a phase-locked loop circuit including a control signal generation unit that generates a control signal and an oscillator that outputs a signal having a frequency according to the control signal output from the control signal generation unit,
A detection unit for detecting a frequency of a signal output from the oscillator;
The control signal generation so that an error value indicating a difference between a frequency detected by the detection unit and a preset frequency that defines an initial value of a frequency of a signal output from the oscillator is smaller than a predetermined value. A processing unit that provides the control signal generation unit with a control value that varies the control signal generated by the unit;
And a storage unit that stores the control value given to the control signal generation unit when the error value is smaller than the predetermined value. A comparison unit that compares a frequency reference signal having a predetermined frequency with a signal output from the oscillator;
The phase-locked loop circuit according to claim 1, further comprising: a switch unit provided between the comparison unit and the control signal generation unit.   The phase-locked loop circuit according to claim 2, wherein the processing unit opens the switch unit when generating the control value to be stored in the storage unit. A frequency dividing circuit that divides the frequency reference signal by a predetermined frequency dividing ratio;
4. The phase-locked loop according to claim 2, wherein the detection unit includes a counter that counts a frequency of a signal output from the oscillator using a signal output from the frequency dividing circuit as a gate signal. 5. circuit.   3. The phase locked loop circuit according to claim 2, wherein, when starting the operation as the phase locked loop, the processing unit gives the control value stored in the storage to the control signal generating unit. 4.   6. The phase-locked loop circuit according to claim 5, further comprising a timer unit that closes the switch unit after a predetermined time has elapsed since the control value stored in the storage unit is supplied to the control signal generation unit. .   The phase-locked loop circuit according to claim 5, wherein the control signal generation unit operates as a loop filter during the operation as the phase-locked loop. A converter that converts the signal output from the oscillator into a signal having a lower frequency;
8. The filter unit according to claim 2, further comprising: a filter unit that passes only a signal having a necessary frequency from the signal converted by the conversion unit and outputs the signal to the comparison unit. Phase-locked loop circuit. A phase-locked loop circuit according to claim 1 is provided, and a standard signal having a predetermined frequency is generated using a signal output from the phase-locked loop circuit. Signal generator.

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