CN111817715B - Phase locking method and related phase-locked loop, chip and electronic device - Google Patents
Phase locking method and related phase-locked loop, chip and electronic device Download PDFInfo
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- CN111817715B CN111817715B CN202010934902.8A CN202010934902A CN111817715B CN 111817715 B CN111817715 B CN 111817715B CN 202010934902 A CN202010934902 A CN 202010934902A CN 111817715 B CN111817715 B CN 111817715B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
Abstract
The application discloses a phase locking method and relevant phase-locked loop, chip and electronic device, the phase locking process includes frequency locking phase and phase locking phase, the phase locking phase includes loading cycle, the method includes: generating a reference phase from a reference clock in the frequency locking phase or the phase locking phase, the reference phase representing phase information of the reference clock; generating a variable phase according to a variable clock in the frequency locking stage or the phase locking stage outside the loading period, wherein the variable phase represents phase information of the variable clock; generating the variable phase from the variable clock and the phase error during the loading period; generating a phase error according to the reference phase and the variable phase; filtering the phase error to generate a frequency control word; and generating the variable clock according to the frequency control word.
Description
Technical Field
The present disclosure relates to phase locking methods, and particularly to a phase locking method capable of increasing a locking speed of a phase-locked loop, and a related phase-locked loop, a chip and an electronic device.
Background
As semiconductor manufacturing processes move to smaller dimensions, the advantages of digital phase locked loops are exploited. Under the nanometer level process, compared with the traditional charge pump phase-locked loop, the digital phase-locked loop has the advantages of smaller area, lower power consumption, lower voltage working voltage, insensitivity to the process and the like. And because the loop filter (hereinafter referred to as the filter) adopts a full digital design, the control of the filter becomes more convenient. However, how to accelerate the locking speed of the digital pll is still one of the important items to be improved in the art.
Disclosure of Invention
An objective of the present invention is to provide a phase-locking method capable of increasing the locking speed of a phase-locked loop, and a related phase-locked loop, a chip and an electronic device, so as to solve the above-mentioned problems.
An embodiment of the present application discloses a phase locking method, wherein a phase locking process includes a frequency locking phase and a phase locking phase, the phase locking phase follows the frequency locking phase, and the phase locking phase includes a loading cycle, the method includes: generating a reference phase from a reference clock in the frequency locking phase or the phase locking phase, the reference phase representing phase information of the reference clock; generating a variable phase according to a variable clock in the frequency locking stage or the phase locking stage outside the loading period, wherein the variable phase represents phase information of the variable clock; generating the variable phase from the variable clock and the phase error during the loading period; generating a phase error according to the reference phase and the variable phase; filtering the phase error to generate a frequency control word, comprising: in the frequency locking stage, generating a proportional output according to the reference clock and the phase error, and generating the frequency control word according to the proportional output only; resetting the proportional output in the loading period, taking the frequency control word generated last before entering the loading period as an integral output of the loading period, and generating the frequency control word according to the proportional output and the integral output; and generating the proportional output and the integral output according to the reference clock and the phase error at the phase locking stage outside the loading period, and generating the frequency control word according to the proportional output and the integral output; and generating the variable clock according to the frequency control word.
An embodiment of the present application discloses a phase-locked loop, the phase-locked process includes a frequency locking phase and a phase locking phase, the phase locking phase is after the frequency locking phase, and the phase locking phase includes a loading period, the phase-locked loop includes: a reference phase generator for generating a reference phase according to a reference clock in the frequency locking phase or the phase locking phase, wherein the reference phase represents phase information of the reference clock; a variable phase generator for generating a variable phase from a variable clock in the frequency locking phase or the phase locking phase other than the loading period, the variable phase representing phase information of the variable clock, and for generating the variable phase from the variable clock and the phase error in the loading period; a phase detector for generating a phase error according to the reference phase and the variable phase; a filter, comprising: a scaling unit to generate a scaled output from the reference clock and the phase error during the frequency lock phase or the phase lock phase other than the loading period, and to reset the scaled output during the loading period; an integration unit that is not enabled during the frequency lock phase, that takes a last generated frequency control word before entering the load period as an integrated output of the load period during the load period, and that generates an integrated output depending on the reference clock and the phase error during the phase lock phase outside the load period; the filter generates the frequency control word according to the proportional output and the integral output; and a numerically controlled oscillator for generating the variable clock according to the frequency control word.
An embodiment of the present application discloses a chip, which includes the phase-locked loop described above.
An embodiment of the present application discloses an electronic device, including the above-mentioned phase-locked loop.
The clock generation method can be used for compensating the phase difference between the reference phase generator and the variable phase generator by additionally adding a phase error value to the variable phase generator when a loading signal enters a loading period when the frequency locking stage enters the phase locking stage, meanwhile, a proportion unit in the filter is reset, and the last frequency control word before the loading signal comes is loaded into an integration unit in the filter to be used as an initial value of the next moment, so that the time for adjusting the phase error in the phase locking stage is saved, and the convergence time of the phase locking stage is reduced.
Drawings
Fig. 1 is a circuit block diagram of an embodiment of a digital phase locked loop of the present application.
Fig. 2 is a circuit block diagram of an embodiment of a reference phase generator of the present application.
Fig. 3 is a circuit block diagram of an embodiment of a variable phase generator of the present application.
FIG. 4 is a circuit block diagram of an embodiment of a proportional cell of the present application.
Fig. 5 is a circuit block diagram of an embodiment of an integration unit of the present application.
Fig. 6 is a timing diagram of the digital phase locked loop locking process of the present application.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
In order to realize the quick start of the digital phase-locked loop, namely, to accelerate the locking speed and shorten the clock generation process, the digital phase-locked loop can be locked in stages, specifically, the locking process of the digital phase-locked loop can be divided into a frequency locking stage and a phase locking stage, the frequency locking stage locks aiming at the locking frequency, and the phase locking stage is added with the phase locking besides the frequency continuous locking. After the digital phase-locked loop is switched from the frequency locking stage to the phase locking stage, the initial value setting is carried out on part of hardware of the digital phase-locked loop, so that the phase locking stage is accelerated, and the details are described later.
Referring to fig. 1, fig. 1 is a circuit block diagram of an embodiment of a digital phase locked loop 100 of the present application. The digital phase locked loop 100 is capable of being clocked by a reference clock CLKRAnd a frequency division ratio N to generate a variable clock CLKVSo that when the lock is completed, the variable clock CLKVFrequency of and reference clock CLKRIs a division ratio N, wherein the reference clock CLK is theRMay be provided by a crystal oscillator external to the wafer on which the digital phase locked loop 100 is located,or by other circuitry in the wafer; the dividing ratio N is determined according to the application of the system in which the digital phase-locked loop 100 is located, and is preset in the chip.
The digital phase locked loop 100 includes a reference phase generator 102, a variable phase generator 104, a phase detector 106, a filter 107, and a digitally controlled oscillator 114, wherein the reference phase generator 102, the variable phase generator 104, the phase detector 106, and the filter 107 are all digital circuits. In this embodiment, the digital phase locked loop 100 is generating a variable clock CLKVThe process of (1) includes a frequency locking phase and a phase locking phase, wherein the frequency locking is performed at the beginning, and then the phase locking phase is switched to the phase locking phase until the locking state converges, that is, the locking is generally completed and the phase locking phase is continuously maintained. The variable phase generator 104 and the filter 107 in the digital phase-locked loop 100 are configured accordingly for both phases, while the reference phase generator 102, the phase detector 106 and the dco 114 are identical for both phases.
The reference phase generator 102 is used for generating a reference clock CLK according to a reference clockRGenerating a reference phase ϕRReference phase ϕRRepresenting a reference clock CLKRThe phase information of (1). Referring to fig. 2, fig. 2 is a block diagram of a reference phase generator 102 according to an embodiment of the present application, wherein the reference phase generator 102 is based on a reference clock CLK in either the frequency locked phase or the phase locked phaseRA first preset value is accumulated, for example, in this embodiment, the first preset value is a frequency dividing ratio N. Specifically, the reference phase generator 102 includes a flip-flop 202 and an adder 204, in the embodiment, the flip-flop 202 is configured to be based on a reference clock CLKRTo cause the Q output to data-switch in accordance with the input signal at the D input, i.e. each time at the reference clock CLKROn the rising edge of the clock signal, the flip-flop 202 will output the reference phase ϕ of the previous timeRThe sum division ratio N is output as the reference phase ϕ by the adder 204RThat is, the reference phase generator 102 substantially uses the reference clock CLKRThe frequency of the division ratio N is accumulated.
Referring to fig. 6, fig. 6 is a timing diagram illustrating a locking process of the digital phase locked loop 100 according to the present application. The division ratio N in the embodiment of fig. 6 is 16, and the reference phase ϕ can be seenRWith reference clock CLK R16, i.e. reference phase ϕ in fig. 6RAt the reference clock CLKRThe rising edge of (c) changes from 17 to 33 and then to 49.
Returning to FIG. 1, the variable phase generator 104 is configured to generate the variable clock CLK according to the variable clock CLKVProducing a variable phase ϕVVariable phase ϕVRepresenting a variable clock CLKVThe phase information of (1). Referring to fig. 3, fig. 3 is a circuit block diagram of an embodiment of the variable phase generator 104 of the present application. The variable phase generator 104 is based on the variable clock CLK during the frequency-locked phase and the phase-locked phase except for the loading period (the period when the loading signal SL is 1)VAccumulating the second preset value to produce a variable phase ϕV. Due to the variable clock CLKVIs the reference clock CLK in the frequency locked stateRThat is, the frequency of accumulation performed by the variable phase generator 104 is N times the frequency of accumulation performed by the reference phase generator 102, so that the second preset value is 1/N of the first preset value, for example, in this embodiment, the first preset value is N, and the second preset value is 1. Specifically, variable phase generator 104 includes flip-flop 302, adder 304, adder 308, and multiplexer 306. The flip-flop 302 is used for being dependent on the variable clock CLK during a period (the period when the loading signal SL is 0) other than the loading periodVTo cause data switching at the Q output in response to the input signal at the D input, i.e. at the variable clock CLKVOn the rising edge of (c), flip-flop 302 outputs variable phase ϕVAnd variable phase ϕVThe sum of the second preset value and the second preset value is added by the adder 304 and is added at the variable clock CLKVIs output as a variable phase ϕ when the next rising edge of (c) comesVThat is, the variable phase generator 104 of FIG. 3 essentially uses the variable clock CLKVThe frequency of (c) is accumulated for 1.
The phase detector 106 of fig. 1 is configured to detect the reference phase ϕ according to the reference phaseRAnd variable phase ϕVProducing a phase error ϕEFor example, the phase detector 106 may be implemented as a subtractor for obtaining the reference phase ϕRAnd variable phase ϕVThe difference of (a). Since the digital phase-locked loop 100 can only lock the frequency during the frequency locking phase, the phase error ϕ cannot be clearedEThe principle is explained later, so that the digital phase-locked loop 100 still has a non-zero phase error ϕ after the frequency locking phase is completedE. Specifically, as shown in fig. 6, before switching from the frequency locking phase to the phase locking phase, even when the enable signal E is 0, the reference clock CLK is set to be zeroRVariable phase ϕ within the period of (c)VIs equal to the division ratio N (16), representing the variable clock CLK (25-9 = 16)VFrequency of and reference clock CLKRIs a division ratio N, i.e. frequency locked, but now the phase error ϕEStill non-zero.
Phase error ϕEThe frequency control word for the variable frequency is determined by the process, and thus the phase error ϕ for different processes, and the overall loop gain of the digital phase-locked loop 100EAre not identical. Digital phase-locked loop 100 also requires a time-to-phase error ϕ after digital phase-locked loop 100 switches from the frequency-locked phase to the phase-locked phaseEThe convergence time of the phase locking phase is greatly lengthened, especially in the case of a small bandwidth of the filter 107, and the locking time is affected by the process, increasing the uncertainty of the locking time.
Referring to fig. 3 and fig. 6, in order to reduce the convergence time of the digital pll 100 in the phase-locked phase, when the variable phase generator 104 switches from the frequency-locked phase to the phase-locked phase, i.e. when the enable signal E changes from 0 to 1, the loading signal SL is set to 1 immediately after switching to the phase-locked phase, and keeps a variable clock CLKVIs returned to 0, called the loading period, in other words, the loading period occurs from the time of the loading periodThe first variable clock CLK after the frequency locked phase has entered the phase locked phaseVThe period of (c). During the loading period, the variable phase generator 104 adds the phase error ϕ generated by the phase detector 106 through the adder 308 in addition to the first preset valueETo produce a variable phase ϕVThereby causing the phase error ϕ generated by the phase detector 106ECan be quickly compensated for, as shown in fig. 6, a variable phase ϕ during the loading cycleVIs 31, but in the variable clock CLKVThe next period, variable phase ϕVAdding said first preset value (1) to 31 plus a phase error ϕE(7) 39 so that the next reference clock CLK after the digital phase-locked loop 100 is switched to the phase-locked phaseRPeriod of (2), variable phase ϕVAnd a reference phase ϕRSame, all are 49, resulting in a phase error ϕEFrom 7 to 0.
However, the reference phase generator 102 and the variable phase generator 104 are not limited to the embodiments shown in fig. 2 and 3. For example, for variable phase generator 104, a digital divider may also be used to divide the variable clock CLKVDividing by N times to generate a divided variable clock CLKDV(wherein the variable clock CLK is dividedDVIs a variable clock CLK V1/N) of the frequency of the clock signal, so that the variable clock CLK is dividedDVFrequency of and reference clock CLKRIs the same (when the lock is complete). Therefore, if a digital divider is used, the reference phase generator 102 and the variable phase generator 104 should accumulate the same value, for example, the reference phase generator 102 is based on the reference clock CLKRAccumulate the second preset value to generate a reference phase ϕR(ii) a Variable phase generator 104 divides variable clock CLKDVThe second preset value is also accumulated to produce a variable phase ϕV. During the loading period, the digital frequency divider in the variable phase generator 104 is dependent on the variable clock CLKVAnd phase error ϕETo generate a divided variable clock CLKDVI.e. to the variable clock CLKVWhen dividing by N times, addingPhase error ϕ generated by the phase detector 106ETo generate a divided variable clock CLKDVMake the correspondingly generated variable phase ϕVCan pass through phase error ϕEIs compensated for quickly.
In addition, the loading period in fig. 6 occurs as soon as the frequency locking phase is switched to enter the phase locking phase, so as to maximally accelerate the phase locking time in the phase locking phase, but the present application is not limited thereto, and in some embodiments, the loading period may also occur at an interval after the phase locking phase is entered.
The filter 107 of FIG. 1 is used to correct the phase error ϕEFiltering to generate a frequency control word SC, which is used to control the numerically controlled oscillator 114 to generate the variable clock CLKVTo the variable phase generator 104 and forms a loop. In some embodiments, the output of the filter 107 may be further normalized to be used as the frequency control word SC, so as to obtain better locking performance.
Specifically, the filter 107 includes a proportional unit 108, an integral unit 110, and an adder 112, wherein the outputs of the proportional unit 108 and the integral unit 110 are added by the adder 112 to generate the frequency control word SC. The proportional unit 108 and the integral unit 110 are shown in fig. 4 and 5, respectively. The scaling unit 108 includes a flip-flop 402, a multiplier 404, multiplexers 406 and 410, and an inverter 408, wherein the multiplier 404 is used for multiplying the phase error ϕEThe product of the first gain α and the first gain α is output to a first input terminal (0) of the multiplexer 406, wherein the first gain α is related to the transfer function of the scaling unit 108, and specifically the first gain α determines the zeroth order characteristic of the transfer function of the filter 107; while the input of the second input terminal (1) of the multiplexer 406 is a third preset value, which is 0 in this embodiment. The first input terminal (0) of the multiplexer 410 is inputted with the reference clock CLKR(ii) a Variable clock CLKVThrough inverter 408 to a second input (1) of multiplexer 410. The multiplexer 406 selectively couples the first input terminal (0) or the second input terminal (1) of the multiplexer 406 to the multiplexer 406 according to the loading signal SLThe output of multiplexer 406 is coupled to the D input of flip-flop 402. The multiplexer 410 selectively couples the first input (0) or the second input (1) of the multiplexer 410 to the output of the multiplexer 410 according to the loading signal SL, and the output of the multiplexer 410 is coupled to the clock input of the flip-flop 402. Under the control of the loading signal SL, the flip-flop 402 is controlled by the ratio unit 108 according to the reference clock CLK during the frequency-locked phase and the phase-locked phase except for the loading periodRWill phase error ϕEThe product of the first gain α is output as the proportional output S0. During the load cycle, flip-flop 402 is clocked by a variable clock CLKVOutputs 0.
When the digital phase-locked loop 100 is in the frequency locking phase, the integration unit 110 is not enabled, and when the digital phase-locked loop 100 is in the phase locking phase, the integration unit 110 comprises a flip-flop 502, a multiplier 504, an adder 506, multiplexers 508 and 514, a multiplier 504, an and gate 512 and an inverter 510, wherein the multiplier 504 is used for converting the phase error ϕEThe product of the second gain p, which determines the first order characteristic of the transfer function of the filter 107, is output to the adder 506 and the integral output S1, and is output to the first input (0) of the multiplexer 508; while the input of the second input (1) of the multiplexer 508 is the frequency control word SC, the output of the multiplexer 508 is coupled to the D input of the flip-flop 502. And gate 512 is used for comparing enable signal E with reference clock CLKRAn AND operation and outputs the result to a first input (0) of the multiplexer 514; variable clock CLKVThe output of the multiplexer 514 is coupled to the clock input of the flip-flop 502 via the inverter 510 to the second input (1) of the multiplexer 514. The reference clock CLK is controlled by the load signal SL and the enable signal E, and by the AND gate 512RThe enable signal E is 0, and cannot be transmitted to the flip-flop 502, so that the integration unit 110 loses the triggering of the clock input in the frequency locking phase, and the integration unit 110 is not enabled. Integrating during the phase-locked phase except for the loading periodThe unit 110 is dependent on the reference clock CLK via multiplexers 508, 514, multiplier 504 and adder 506RWill phase error ϕEAnd the sum of the product of the second gain ρ and the integrated output S1 is the integrated output S1.
In other words, in the frequency locking phase, the filter 107 is set to be a zero order filter with only the proportional unit 108, and the open loop transfer function of the digital phase locked loop 100 is:
ϕV=ϕRαKndcoin which K isndcoThe gain of the oscillator 114 is digitally controlled.
The closed loop transfer function of the digital phase locked loop 100 is:
ϕE=ϕR/(1+ϕRαKndco)
it can be seen that in the frequency lock phase, phase error ϕEIs a value other than zero. But due to phase error ϕEConstant and thus may indicate that the frequency may still be locked in the frequency locking phase.
After the frequency locking, the phase locking stage is entered, and the integrating unit 110 is enabled to become a first-order filter, where the open-loop transfer function of the digital phase-locked loop 100 is:
ϕV=ϕR（α+ρ/s）Kndco
the closed loop transfer function of the digital phase locked loop 100 is:
ϕE=(sϕR)/(s+ϕR（αs+ρ）Kndco)
it can be seen that in the phase lock phase, phase error ϕEZero at very low frequencies, and thus accounts for the converged phase error ϕEIs zero.
As mentioned above, to speed up the phase convergence in the phase lock phase, the phase error ϕ is additionally added to the output of the variable phase generator 104 during the loading periodESo that the phase ϕ is variableVAnd a reference phase ϕRAnd (6) synchronizing. For the filter 107, during the loading period, the integration unit 110 will output the filter 107By actively configuring variable phase generator 104, proportional unit 108, and integral unit 110 during the loading period, the time for phase convergence of digital phase-locked loop 100 during the phase-locked phase can be reduced compared to conventional approaches by loading frequency control word SC into integral unit 110 and resetting the output of proportional unit 108. The concrete description is as follows.
Referring to fig. 4 and 6, when the scaling unit 108 switches from the frequency locking phase to the phase locking phase, the third preset value is loaded through the multiplexers 406 and 410 and the inverter 408 during the loading period, and the third preset value is loaded according to the inverted variable clock CLKVThe output is a proportional output S0, and the third preset value is zero in the embodiment, which is equivalent to the phase error ϕEA 0 condition produces proportional output S0, which causes proportional output S0 to reset to 0. As can be seen from fig. 6, the first inverted variable clock CLK of the proportional unit 108 after switching from the frequency locked phase to the phase locked phaseVWhen the period of (c) occurs, i.e. the variable clock CLK corresponding to the dotted line in fig. 6VThe falling edge of (c), resets the integrated output S1 to 0.
Referring to fig. 5 and fig. 6, in the loading period after the integration unit 110 switches from the frequency locking phase to the phase locking phase, the multiplexer 508, 514 and the inverter 510 are used to load the frequency control word SC and the frequency control word SC is loaded according to the inverted variable clock CLKVThe output is the integrated output S1, so the loaded clock control word SC will be the last generated clock control word SC before entering the loading period, i.e. the variable clock CLK before entering the loading periodVThe frequency control word SC of the generation of the cycle. As can be seen from fig. 6, the integration unit 110 switches the first inverted variable clock CLK after the frequency locking phase is switched to the phase locking phaseVWhen the period of (c) occurs, i.e. the variable clock CLK corresponding to the dotted line in fig. 6VThe falling edge of (c), the frequency control word SC (28) is loaded and output.
It should be noted that, when the loading signal SL comes, the reference clock CLKRDoes not necessarily come in time, in order to complete the frequencyLoading of the rate control word SC, whereby the loading period uses a variable clock CLKVAs a clock; in some embodiments, a two-cycle variable clock CLK may also be usedVTo complete the loading of the frequency control word SC.
The present application further provides a chip, which includes the digital pll 100, and the chip can be disposed in an electronic device, for example, any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, or a tablet computer.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (17)
1. A phase locking method, wherein a phase locking process comprises a frequency locking phase and a phase locking phase, wherein the phase locking phase follows the frequency locking phase, and wherein the phase locking phase comprises a loading cycle, the method comprising:
generating a reference phase from a reference clock in the frequency locking phase or the phase locking phase, the reference phase representing phase information of the reference clock;
generating a variable phase according to a variable clock in the frequency locking stage or the phase locking stage outside the loading period, wherein the variable phase represents phase information of the variable clock;
generating the variable phase from the variable clock and phase error during the loading period;
generating the phase error according to the reference phase and the variable phase;
filtering the phase error to generate a frequency control word, comprising:
in the frequency locking stage, generating a proportional output according to the reference clock and the phase error, and generating the frequency control word according to the proportional output only;
resetting the proportional output in the loading period, taking the frequency control word generated last before entering the loading period as an integral output of the loading period, and generating the frequency control word according to the proportional output and the integral output; and
generating the proportional output and the integral output according to the reference clock and the phase error at the phase locking stage outside the loading period, and generating the frequency control word according to the proportional output and the integral output; and
generating the variable clock in dependence on the frequency control word.
2. The phase locking method of claim 1, wherein generating the reference phase from the reference clock comprises:
accumulating a first preset value according to the reference clock to generate a reference phase.
3. The phase locking method of claim 2, wherein generating the variable phase from the variable clock comprises:
accumulating a second preset value according to the variable clock to generate a variable phase, wherein the ratio of the first preset value to the second preset value is a frequency dividing ratio, and the frequency dividing ratio is the ratio of the frequency of the variable clock generated at the end of the phase locking stage to the frequency of the reference clock; and
generating the variable phase as a function of the variable clock and the phase error comprises:
accumulating a second preset value according to the variable clock, and additionally adding the phase error to generate the variable phase.
4. The phase locking method of claim 1, wherein generating the proportional output as a function of the reference clock and the phase error comprises:
and outputting the product of the phase error and a first gain as a proportional output according to the reference clock, wherein the first gain is related to the zeroth order characteristic of the transfer function of the filtering processing.
5. The phase locking method of claim 1, wherein generating the integrated output as a function of the reference clock and the phase error comprises:
adding a product of the phase error and a second gain related to a first order characteristic of a transfer function of the filtering process to the integrated output in accordance with the reference clock, and taking the resultant sum as the integrated output.
6. The phase locking method according to any one of claims 1 to 5, wherein generating the frequency control word based only on the proportional output comprises:
and outputting the proportion as the frequency control word.
7. The phase-locking method according to any one of claims 1 to 5, wherein generating the frequency control word according to the proportional output and the integral output comprises:
adding the proportional output and the integral output to produce the frequency control word.
8. The phase locking method according to any one of claims 1 to 5, wherein the loading period occurs at a first period of the variable clock after entering the phase-locked phase from the frequency-locked phase.
9. A phase-locked loop, wherein a phase-locking process includes a frequency-locking phase and a phase-locking phase, wherein the phase-locking phase follows the frequency-locking phase, and wherein the phase-locking phase includes a loading period, the phase-locked loop comprising:
a reference phase generator for generating a reference phase according to a reference clock in the frequency locking phase or the phase locking phase, wherein the reference phase represents phase information of the reference clock;
a variable phase generator for generating a variable phase from a variable clock in the frequency locking phase or the phase locking phase other than the loading period, the variable phase representing phase information of the variable clock, and for generating the variable phase from the variable clock and a phase error in the loading period;
a phase detector for generating the phase error according to the reference phase and the variable phase;
a filter, comprising:
a scaling unit to generate a scaled output from the reference clock and the phase error during the frequency-locked phase or the phase-locked phase outside the loading period, and to reset the scaled output during the loading period;
an integration unit that is not enabled during the frequency lock phase, that takes a last generated frequency control word before entering the load period as an integrated output of the load period during the load period, and that generates an integrated output depending on the reference clock and the phase error during the phase lock phase outside the load period;
the filter generates the frequency control word according to the proportional output and the integral output; and
a numerically controlled oscillator for generating the variable clock according to the frequency control word.
10. The phase locked loop of claim 9 wherein the reference phase generator accumulates a first predetermined value according to the reference clock to generate the reference phase during either the frequency locking phase or the phase locking phase.
11. The phase-locked loop of claim 10, wherein the variable phase generator accumulates a second predetermined value according to the variable clock to generate the variable phase during the phase-locked phase or the phase-locked phase outside the loading period, wherein a ratio of the first predetermined value to the second predetermined value is a frequency division ratio, and the frequency division ratio is a ratio of a frequency of the variable clock generated at the end of the phase-locked phase to a frequency of a reference clock; and the variable phase generator accumulates a second preset value according to the variable clock during the loading period and additionally adds the phase error to generate the variable phase.
12. The phase locked loop of claim 9 wherein the scaling unit is configured to output a product of the phase error and a first gain as a scaled output according to the reference clock during the frequency locking phase or the phase locking phase outside the loading period, wherein the first gain is related to a zeroth order characteristic of a transfer function of the filter.
13. The phase locked loop of claim 9 wherein the integration unit is configured to output a product of the phase error and a second gain and a sum of the integrated output as the integrated output according to the reference clock during the phase lock phase outside the loading period, wherein the second gain is related to a first order characteristic of a transfer function of the filter.
14. A phase locked loop as claimed in any one of claims 9 to 13, wherein said filter further comprises an adder for adding said proportional output and an integrated output generated by said integrating unit to generate said frequency control word.
15. A phase locked loop as claimed in any one of claims 9 to 13, wherein said loading period occurs the first period of said variable clock after said frequency lock phase enters said phase lock phase.
16. A chip, comprising:
a phase locked loop as claimed in any one of claims 9 to 15.
17. An electronic device, comprising:
the chip of claim 16.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174634A (en) * | 1994-11-28 | 1998-02-25 | 柯廷技术大学 | Steered frequency phase locked loop |
| WO2000077936A1 (en) * | 1999-06-11 | 2000-12-21 | Telefonaktiebolaget Lm Ericsson (Publ) | An arrangement in an electronics system |
| CN1667956A (en) * | 2003-11-19 | 2005-09-14 | 国际商业机器公司 | Modular DLL architecture for generating multiple timings |
| JP2006262489A (en) * | 2005-03-18 | 2006-09-28 | Avago Technologies General Ip (Singapore) Private Ltd | Linear phase-locked loop having double tuning element |
| CN101640533A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Rapid locking method for full digital phase-locked loop |
| CN103297041A (en) * | 2012-02-28 | 2013-09-11 | 株式会社巨晶片 | Phase-locked loop |
| CN110855289A (en) * | 2019-11-14 | 2020-02-28 | 芯原微电子(上海)股份有限公司 | All-digital phase-locked loop locking method and all-digital phase-locked loop circuit |
-
2020
- 2020-09-08 CN CN202010934902.8A patent/CN111817715B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174634A (en) * | 1994-11-28 | 1998-02-25 | 柯廷技术大学 | Steered frequency phase locked loop |
| WO2000077936A1 (en) * | 1999-06-11 | 2000-12-21 | Telefonaktiebolaget Lm Ericsson (Publ) | An arrangement in an electronics system |
| CN1667956A (en) * | 2003-11-19 | 2005-09-14 | 国际商业机器公司 | Modular DLL architecture for generating multiple timings |
| JP2006262489A (en) * | 2005-03-18 | 2006-09-28 | Avago Technologies General Ip (Singapore) Private Ltd | Linear phase-locked loop having double tuning element |
| CN101640533A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Rapid locking method for full digital phase-locked loop |
| CN103297041A (en) * | 2012-02-28 | 2013-09-11 | 株式会社巨晶片 | Phase-locked loop |
| CN110855289A (en) * | 2019-11-14 | 2020-02-28 | 芯原微电子(上海)股份有限公司 | All-digital phase-locked loop locking method and all-digital phase-locked loop circuit |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的改进型全数字锁相环的设计;彭咏龙等;《电源技术》;20150228(第02期);第410-412页 * |
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