JPH02288673A - Frequency adjustment circuit for signal processing filter - Google Patents

Abstract

PURPOSE:To attain accurate signal processing by correcting a center frequency of a signal processing filter equal to the frequency of a reference clock. CONSTITUTION:An input signal is fed to a phase comparator circuit 29 via a switch 25, a signal processing filter 26 and a switch 27 and the phase is compared with that of a reference clock. Then an output voltage corresponding to a phase difference component is generated from a loop filter 30 and fed to the signal processing filter 26 via an S/H(sample-and-hold) circuit 31 and the center frequency fO of the signal processing filter 26 is controlled to be equal to a frequency fS of the reference clock. Since the center frequency fO is subject to negative feedback control so as to be equal to the reference clock frequency fS, accurate signal processing is applied.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a signal processing filter such as an active filter built into an IC (integrated circuit), and particularly relates to a signal processing filter such as an active filter built in an IC (integrated circuit). This invention relates to improvements in automatic frequency adjustment circuits.

(Prior Art) As is well known, an automatic frequency adjustment circuit using a PLL (phase locked loop) circuit is used as a means for automatically adjusting the center frequency of a signal processing filter such as an active filter built into an IC. be.

Also, among automatic frequency adjustment circuits using PLL circuits, there are two types: one using a VCO (voltage controlled oscillator), and the other using a VCO (voltage controlled oscillator).
Instead of CO, vcF<rti pressureff,! There is a type that uses a control filter).

The time constants of the VCO and VCF are both configured by the same circuit as the signal processing filter. For this reason, the VCO
Alternatively, by applying a voltage that controls the frequency response of the VCF to the signal processing filter, the frequency response of the signal processing filter is controlled to have desired characteristics.

FIG. 4 shows a conventional automatic frequency adjustment circuit using a VCO. That is, the reference clock supplied to the input terminal 11 is input to the phase comparison circuit 12. The signal is supplied to a PLL circuit 15 consisting of a loop filter 13 and a VCO 14.

At this time, if the PLL circuit 15 is in a phase synchronization (locked) state, closed loop control is performed so that the oscillation frequency fVCO of the VCO 14 becomes equal to the frequency fS of the reference clock.

Then, the output voltage of the loop filter 13 at this time is
By supplying it to the time constant circuit of the signal processing filter 16, the center frequency fO of the signal processing filter 16 is set to V
The oscillation frequency f of C014 can be made equal to the VCO.

Further, FIG. 5 shows a conventional automatic frequency adjustment circuit using a VCF. That is, by supplying the reference clock supplied to the input terminal 17 to the PLL circuit 21 consisting of the phase comparison circuit 18° loop filter 19 and the VCF 20, the cutoff frequency fVCP of the VCF 20 is adjusted to the frequency fS of the reference clock. It is controlled in a closed loop to be equal.

++ Te, VCF20 is, for example, 2nd order (7) LPF (o-
pass filter), the input/output phase difference is 90° at the cutoff frequency fVCP of the VCF 20. Also,
If a multiplication circuit is used as the phase comparison circuit 18, the PLL circuit 21 will be in a synchronized state when the phase 2 of the two inputs is 90''.

Then, the output voltage of the loop filter 19 at this time is
By supplying the time constant circuit of the signal processing filter 22, the center frequency fO of the signal processing filter 1B is set to V
The cutoff frequency f of CF 20 can be made equal to VCP.

However, in the conventional automatic frequency adjustment circuit as described above, the oscillation frequency f of VCO14, VCO and VC
F 20 (7) Cutoff frequency f VCP C, both P
While the frequency is controlled to be equal to the reference clock frequency fS by closed loop control using the LL1 path 15.21,
The center frequency fO of the signal processing filter l[i, 22 is open-loop controlled by simply adding the output voltage of the loop filter 13.19.

Even if the time constant circuit of V CO14 or vCF20 and the specific number circuit of the signal processing filter 18.22 are configured with the same circuit, the oscillation of V CO14 will occur due to the relative error of a few percent of the elements. Frequency f VCO
and V CF 20 (7) Cutoff frequency fVcP, knob, reference clock frequency fS, and signal processing filter 1
A problem arises in that the center frequencies fO of 6.22 are not equal.

(Problem to be solved by the invention) As described above, in the conventional frequency adjustment circuit, VCO and V
Since it is open-loop control that only supplies the control voltage supplied to the CF to the signal processing filter, there is a problem that the center frequency of the signal processing filter is not equal to the frequency of the reference clock due to variations in the circuit elements. There is.

Therefore, the present invention was made in consideration of the above circumstances, and provides an extremely good frequency adjustment circuit for a signal processing filter that can extract the center frequency of the signal processing filter to be equal to the frequency of the reference clock. The purpose is to provide.

[Means of the Invention] (Means for Solving the Problems) The frequency and 22 rectifying circuit of the signal processing filter according to the present invention guides an input signal to the signal processing filter, and
A switching means is provided for guiding a first reference clock of a constant frequency to the signal processing filter during a blanking period when there is no signal to be processed by the signal processing filter of the input signal, and the switching means leads the first reference clock to the signal processing filter. The output of the signal processing filter is compared with the first reference clock in a state where the signal is guided to the processing filter, and the center frequency of the signal processing filter is controlled so that the phase difference component becomes a predetermined value. and to hold the first control signal and supply it to the signal processing filter while the switching means is switched to guide the input signal to the signal processing filter. It is composed of

(Function) According to the above configuration, the signal processing filter is used as the VCF of the PLL circuit with the switching means guiding the first reference clock to the signal processing filter. Through closed loop control, negative feedback control can be performed to make the center frequency of the signal processing filter equal to the first reference clock.

In addition, when the switching means is switched so as to lead the input signal to the signal processing filter, the first control signal is held and supplied to the signal processing filter, and the signal processing filter is used for signal processing of the input signal. Since it is used as the center frequency, the input signal can be processed at the correct center frequency.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, an input terminal 23 is supplied with an input signal such as a television signal in which signal periods and blanking periods alternate. Further, reference numeral 24 in FIG. 1 is a clock input terminal to which a reference clock having a constant frequency fS is supplied.

Then, the input signal and 2! The quasi-clock is switch 25.
0 (0) is selectively supplied to the signal processing filter 20 by the switch 27.
is selectively supplied to the output terminal 28 and one input terminal of the phase comparator circuit 29. Further, the other input terminal of the phase comparator circuit 29 is supplied with a reference clock.

Furthermore, the output of the phase comparator circuit 29 is output from the loop filter 3
0 and an S/H (sample/hold) circuit 31, the signal is supplied to a time constant circuit that sets the center frequency fO of the signal processing filter 2B.

Here, the switches 25 and 27 and the S/H circuit 31
is supplied with the gate pulse supplied to the pulse input terminal 32. This gate pulse is a signal that discriminates between a signal period and a blanking period of an input signal.

The switches 25, 27 are switched to the positions shown in FIG. 1 during the blanking period, and are switched to the positions opposite to those shown in the figure during the signal period. Furthermore, the S/H circuit 31 is controlled so as not to perform the sample/hold operation during the blanking period, but to perform the sample/hold operation during the signal period.

The operation of the configuration as in the above embodiment will be described below. First, during the input signal blanking period, the switches 25 and 27 are switched to the positions shown in FIG.
The HIiD path 31 is configured not to perform sample/hold operations.

Therefore, the reference clock is set to switch 25. Phase comparison circuit 29 via signal processing filter 26 and switch 27
The clock is supplied to the reference clock and its phase is compared with the reference clock. and,
An output voltage corresponding to the phase difference component is generated from the loop filter 30 and supplied to the signal processing filter 26 via the S/H circuit 31.
is controlled so that the center frequency fo is equal to the frequency fs of the base clock.

In other words, during the input signal blanking period, the signal processing filter 26 is used as the V CF 20 of the PLL circuit 21 shown in FIG.
Closed loop control by the L circuit 21 enables negative feedback control to make the center frequency of the signal processing filter 2G equal to the frequency fO of the reference clock.

Next, in the signal period of the input signal, the switch angle is 25°27
is switched to a position opposite to that shown in FIG. 1, so that the S/H circuit 31 performs a sample/hold operation.

Therefore, the S/H circuit 31 holds the output voltage of the loop filter 30 at the time of switching from the blanking period to the signal period, and the center frequency fO of the signal processing filter 2G is fixed by this hold voltage.

Further, the input signal is processed by the signal processing filter 2G via the switch 25 and then taken out from the output terminal 28 via the switch 27. That is, during the signal period of the input signal, the signal processing filter 2G processes the input signal with the center frequency fO fixed based on the hold voltage of the S/H circuit 31.

Therefore, according to the configuration of the above embodiment, the signal processing filter 26 is switched to the PL during the blanking period of the input signal.
Since it is used as the VCF of the L circuit, negative feedback control can be performed so that the center frequency fo becomes equal to the frequency fS of the reference clock, and accurate signal processing can be performed.

FIG. 2 shows another embodiment of the invention, in which the same parts as in FIG. 1 are given the same symbols. In this embodiment, a reference clock with a frequency equal to the center frequency fO of the signal processing filter 26 cannot be obtained from the outside, and the Q of the signal processing filter 26 is high and the capture range cannot be expanded sufficiently. It is designed to be particularly effective in both cases.

That is, numeral 33 in FIG. 2 is a clock input terminal, to which a clock is supplied with a frequency fsI which is not equal to the center frequency fo of the signal processing filter 26.

This clock has a white division ratio of I/n and l/n+.

Frequency divider circuit 34.35. Phase comparison circuit 36. A PLL circuit 39 including a loop filter 37 and a VCO 38 converts the signal into a reference clock having a frequency equal to the center frequency fO of the signal processing filter 26.

In this conversion, since the oscillation frequency fVCO of the VCO 38 of the PLL circuit 39 can be expressed as fVco - (n/m) fsl, the values of n and m, which are the frequency division ratios of the frequency divider circuit 34.35, are controlled. By doing so, fVL'0-
It is sufficient to set it so that fO.

In addition, by supplying the control voltage supplied to VC03g, that is, the output voltage of the loop filter 37, to the signal processing filter 26 via the adder circuit 40, the signal processing Rough adjustment is performed to bring the center frequency fO of the filter 26 approximately close to the oscillation frequency fVCO of the VCO38.

Furthermore, by adding the control voltage for controlling the signal processing filter 26 as a VCF during the blanking period of the input signal, that is, the output voltage of the loop filter 30 via the adding circuit 40, the signal processing filter The center frequency fo of VCO 38 is the oscillation frequency f V of VCO 38.
Fine adjustments are made to equalize CO.

For this reason, the signal processing filter 2 that operates as a VCF
Even if the Q of B is high and the capture range is narrow, fluctuations in the center frequency fo can be suppressed within the capture range by rough adjustment by the PLL circuit 39 using the output voltage of the loop filter 37.

Further, the oscillation output of the VC038, that is, the reference clock, is supplied to the phase comparator circuit 29 via the phase shift circuit 41. If the phase difference between the input and output at the center frequency fO of the signal processing filter 26 is not 90@, this phase shift circuit 41 corrects the phase difference between the two input signals of the phase comparison circuit 29 to become 90''. It's no good.

FIG. 3 shows a partially modified version of the embodiment shown in FIG. That is, the switch 27 is removed, the output of the signal processing filter 2G is supplied to the output terminal 28 and the phase comparison circuit 29, and the phase comparison circuit 29 is provided with a sample/hold function, and the gate pulse The structure is simplified by controlling the hold operation.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, extremely good frequency adjustment of a signal processing filter can be achieved in which the center frequency of the signal processing filter can be corrected so as to be similar to the frequency of the reference clock. It is possible to create a circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a frequency adjustment circuit for a signal processing filter according to the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, and FIG. FIGS. 4 and 5 are block diagrams showing a modification of the embodiment, and FIGS. 4 and 5 are block diagrams showing conventional automatic frequency adjustment circuits, respectively. 11... Input terminal, 12... Phase comparison circuit, 13.
...Loop filter, 14...VCo, 15...P
LL circuit, 16...signal processing filter, I7...
Input terminal, 18...phase comparison circuit,! 9...Loop filter, 2o...VCF, 21...PLL circuit,
22...Signal processing filter, 23...Manual terminal,
24... Clock input terminal, 25... Switch, 2
G...Signal processing filter, 27...Switch, 2
8... Output terminal, 29... Phase comparison circuit, 3o...
・Loop filter, 31...S/H circuit, 32...
Pulse input terminal, 33... Input terminal, 34.35...
- Frequency divider circuit, 36... Phase comparison circuit, 37... Loop filter, 38... VCo, 39... PLL circuit, 40... Addition circuit, 4I... Phase shift circuit.

Claims (2)

[Claims] (1) While guiding the input signal to the signal processing filter,
switching means for guiding a first reference clock of a constant frequency to the signal processing filter during a blanking period when there is no signal to be processed by the signal processing filter of the input signal; While the clock is being led to the signal processing filter, the output of the signal processing filter and the first reference clock are compared in phase, and the center of the signal processing filter is adjusted so that the phase difference component becomes a predetermined value. a control means for generating a first control signal for controlling a frequency; and a first control signal outputted from the control means in a state where the switching means is switched to guide the input signal to the signal processing filter. 1. A frequency adjustment circuit for a signal processing filter, comprising a holding means for holding a control signal and supplying the control signal to the signal processing filter. (2) From a second reference clock having a frequency different from that of the first reference clock, the first reference clock is
A second control signal supplied to a voltage controlled oscillator of the phase-locked loop means, and a first control signal outputted from the control means are added together to generate the reference clock of the phase-locked loop means. addition means leading to the signal processing filter; and the first reference clock generated by the phase-locked loop means are phase-shifted so as to have a predetermined phase difference with respect to the output of the signal processing filter. and a phase shift means for supplying the control means.
A frequency adjustment circuit for the signal processing filter described above.