TWI517540B - Charge pump - Google Patents

Description

Charge pump

The present invention is a charge pump, and in particular, a charge pump that changes the output current in response to a voltage level change of a control node.

Please refer to the first figure, which is a schematic diagram of a phase-locked loop provided by the prior art. The phase locked loop 10 mainly includes a phase detector 101, a charge pump (CP) 103, a low pass filter (LF) 105, and a Voltage Control Oscillator (VCO) 107. In addition, it can also be selectively used with the frequency divider 109. The basic principle of the phase-locked loop 10 is to compare the phase difference between the frequency-divided signal V _div outputted by the frequency divider 109 and the input signal V _in , and adjust the output signal of the voltage-controlled oscillator 107 according to the comparison result of the phase difference. The frequency of V _out is f _out . Ideally, the frequency-divided output signal V _out (ie, the frequency-divided signal V _div ) should coincide with the input signal V _in .

Further exploring the respective components in the phase-locked loop 10, and the relationship between the corresponding generated signals, it can be known that the phase and output frequency of the output signal (V _out ) output by the voltage controlled oscillator 107 are θ _out , f , respectively. _Out . In the feedback path of the phase-locked loop 10, the output signal V _out can be divided by the frequency divider 109, and the frequency and phase of the frequency-divided signal V _div obtained by the frequency division are f _div and θ _{div , respectively} . Further, the phase corresponding to the input signal V _in input from the external phase of the phase-locked loop 10 is θ _in .

Furthermore, the phase detector 101 is used to compare the phase θ _{div of the} frequency-divided signal with the phase θ _{in of the} input signal to obtain a phase difference (θ _in -θ _div ) between the two, and use the phase difference to obtain a phase difference The group outputs a phase comparison signal ( _Vup , _Vdown ) to the charge pump 103. After the phase comparison signal (V _up, V _down) and then through the charge pump 103, low pass filter 105 and converted into a voltage in the form of a control signal, voltage control is used to adjust the output signal V _out of the output of the oscillator 107.

Please refer to the second figure (a), which is a schematic diagram of a charge pump composed of a first current source group and a second current source group. The first current source group 103a of the charge pump 103 includes a first current source 1031 and a first switch 1033, and the second current source group 103b is composed of a second current source 1032 and a second switch 1034.

The charge pump 103 provides the first switching current I _P and the second switching current I _N by using the first current source 1031 and the second current source 1032, respectively, but whether the switching currents are actually turned on, and the low-pass is passed through the control node S _cont . The filter 105 is charged and discharged, and it still depends on the switch used. The first changeover switch 1033 and the second changeover switch 1034 are correspondingly turned on according to the first phase comparison signal V _up and the second phase comparison signal V _down output by the phase detector 101.

Please refer to the second figure (b), which illustrates the phase comparison signal output by the phase detector, corresponding to the clock map of the current output by the charge pump at its control node. In this figure, the horizontal axis represents time t, and the vertical axis represents voltage changes of the phase comparison signals ( _Vup , _Vdown ), respectively, and the switching current output by the charge pump 103.

When the phase detector 101 outputs a first phase comparison signal V _up the first switch 1033 is turned on, charge pump 103 outputs the first switching current I _P, and the switching current I _P using the first low-pass filter 105 to charge. That is, during a first phase comparison signal corresponding to V _up generated during a first switching output current I _P, the period is also equivalent to the charge pump 103 pairs of the low pass filter 105 during charging.

Similarly, when the output of the phase detector 101 of the second phase comparison signal V _down the second switch 1034 is turned on, charge pump 103 outputs the second switching current I _N, and using a second low switching current I _N The pass filter 105 performs discharge. That is, the period during which the second phase comparison signal _{Vdown is} generated corresponds to the period during which the second switching current I _{N is} output, and this period is also equivalent to the period during which the charge pump 103 discharges the low-pass filter 105.

As described above, the output combination I _{CP of the} first switching current I _P and the second switching current I _N forms a phase comparison signal for charging or discharging the low-pass filter at the rear end. Generally, when the charge pump 103 is implemented, the first current source group 103a is realized by a combination of a p-channel metal-oxide-semiconductor (PMOS), and the N-type metal oxide half-electricity is realized. A combination of n-channel metal-oxide-semiconductors (abbreviated as NMOS) implements the second current source group 103b.

Ideally, the effects of the first current source group 103a and the second current source group 103b on the charge and discharge of the low-pass filter 105 should be symmetrical with each other, but offset, but the characteristics of the two types of transistors are not completely symmetrical. There is a difference that may cause the current value of the charge and discharge current to be not completely equal, that is, at the control node S _cont of the charge pump 103, the first switching current I _P and the current of the second switching current I _N are output. The values are not consistent.

In the case where the characteristics of the PMOS and the NMOS are not the same, the first switching current I _P actually generated by the PMOS in the first current source group 103a and the second switching current I generated by the NMOS in the second current source group 103b _N does not necessarily match, which will also make the phase-locked loop 10 less than ideal when used. Therefore, the present invention proposes an improved design of the charge pump.

The present invention is a charge pump that outputs a current at a control node according to a phase comparison signal. The charge pump includes: a first current source group disposed between a first voltage terminal and the control node. The first current switching source outputs a first switching current according to the phase comparison signal; and a second current source group is disposed between the control node and a second voltage terminal group, the second current source group includes: a first sub-switching current generating circuit electrically connected to the control node and the second voltage end point, which generates a first sub-switching current due to the phase comparison signal; and a second sub-switching current generating circuit electrically connected The control node and the second voltage end point generate a second sub-switching current due to the phase comparison signal; and a selection circuit electrically connected to the first sub-switching current generating circuit and the second sub-switching current And generating a circuit, wherein the control node outputs the first sub-switching current or the second sub-switching current according to a voltage level of the control node.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Due to system parameters such as bandwidth (K), phase margin, and damping factor, the jitter and stability of the entire system of the phase-locked loop are determined. Therefore, these parameters are often used to evaluate the advantages and disadvantages of the phase-locked loop.

When designing a phase-locked loop, the bandwidth K of the low-pass filter is typically designed to be less than or equal to one tenth of the frequency of the input signal V _in . Further, the output signal V _out may utilize different input signal V _in, and to complete the frequency dividing ratio M of the other compositions. For example, if the phase-locked loop is expected to generate an output signal V _out with a frequency of 1 GHz, the frequency of the input signal with the frequency division coefficient M=100 may be selected to be 10 MHz, or the frequency division coefficient M=50 may be selected. The frequency of the input signal is provided in a manner of 20 MHz.

In other words, the output signal V _out may be affected by the input signal V _in and the frequency division coefficient M, and the input signal V _in is proportional to the bandwidth K of the low pass filter.

In addition, since the bandwidth K of the low-pass filter is proportional to the charge and discharge current I _CP generated by the charge pump on the control node S _cont , when the current value of the charge and discharge current I _CP is higher, the low-pass filter The bandwidth K also increases. On the other hand, since the bandwidth K of the low-pass filter is inversely proportional to the frequency division coefficient M of the frequency divider, the relationship of the bandwidth K of the low-pass filter proportional to I _CP /M can be summarized.

Considering the stability of the phase-locked loop, the bandwidth K of the low-pass filter needs to be maintained when actually operating the phase-locked loop. However, the frequency of the output signal V _out needs to be adjusted frequently, representing the frequency division of the frequency divider. The coefficient M also needs to be adjusted accordingly to maintain the bandwidth K of the low pass filter. It can be known from the relationship between the bandwidth K of the low-pass filter and the I _CP /M that once the frequency division coefficient M of the frequency divider is adjusted, it represents that the charge pump generates the charge and discharge current I _CP of the control node S _cont . The size also needs to be adjusted to maintain the bandwidth K of the low-pass filter.

That is, when designing the phase-locked loop, the charge and discharge current I _CP generated by the charge pump can be utilized to compensate for the influence on the bandwidth K due to the adjustment of the frequency-dividing coefficient M. For example, if the frequency coefficient M is higher and the charge and discharge current I _CP provided by the charge pump is higher, the bandwidth K can be kept fixed; if the frequency coefficient M is smaller, the charge and discharge current of the charge pump I _CP The smaller the interval, the wider the K of the low pass filter can also be maintained.

For example, if the range of the frequency division coefficient M is between 0 and 100, the design must select a parameter that allows the corresponding bandwidth K to be 10. Since the value of the frequency division coefficient M is adjusted when the phase-locked loop is operated dynamically, in order to prevent the bandwidth K from being changed by the change of the frequency-dividing coefficient M, the charge-discharge current I _CP generated by the charge pump is used to divide the frequency coefficient. The change in M is compensated accordingly.

As described above, since the frequency of the output signal V _out of the phase-locked loop is adjusted, the frequency-dividing coefficient M needs to be adjusted. In order to maintain the bandwidth K without fluctuation, it is necessary to dynamically adjust the charge pump. Charge and discharge current I _CP . Therefore, when the adjustable range of the charge/discharge current I _CP is larger, it corresponds to the frequency division coefficient M, and the elasticity of the value of the bandwidth K can be adjusted to be larger.

Since the charge and discharge current I _CP of the charge pump needs to be used to adjust the bandwidth K under the influence of the frequency division coefficient, it is important that the charge and discharge current I _CP flowing through the charge pump can be stably changed. issue.

Referring to the second graph (a) can be known, for a PMOS, a first voltage level of the voltage at terminal S _cont of V ₁ voltage level control node and a first quasi-differential pressure △ V ₁ corresponds to the voltage of the PMOS source The voltage across the pole and the drain is v _DS,P . Similarly, for the NMOS, the voltage level of the second voltage terminal V _{2 and} the voltage level of the control node S _{cont are} the second voltage difference ΔV ₂ corresponds to the voltage across the source and the drain of the NMOS, v _DS,N .

Due to the voltage level of the first voltage terminal V ₁ (assumed to be the voltage source V _dd ), the voltage level of the second voltage terminal V ₂ (assumed to be ground V _GND ) is fixed, so the voltage of the control node S _cont If the level changes, it will affect the value of the first voltage drop ΔV ₁ , the second voltage drop ΔV ₂ , and the voltage and NMOS between the source and the drain of the corresponding PMOS. The cross-pressure between the source and the bungee.

As described above, when the voltage level of the charge pump on the control node S _cont changes, it will affect the cross-voltage between the source and the drain of the PMOS, and the cross between the source and the drain of the NMOS. Pressure.

Please refer to the third figure (a), which is the characteristic curve of the on-current of the NMOS corresponding to the change of the source and the gate across the voltage. For the NMOS, when the gate and drain voltage difference is less than the threshold voltage (ie, v _GD-N <V _tN ), the NMOS operates in a cutoff region.

On the other hand, when the voltage difference between the gate and the drain of the NMOS is greater than the threshold voltage (ie, v _GD-N >V _tN ), it _depends on the voltage across the source and the drain, and the gate and source. The relationship between the pressure difference and the threshold voltage may enter the triode region or the saturation region. The correspondence between the on-current and the voltage across the electrodes when the on-current is generated in the two regions of the NMOS will be described below.

First, if the voltage across the source and the drain of the NMOS, v _DS-N , and the voltage difference between the gate and the source, v _GS-N , and the threshold voltage V _tN , satisfy v _DS-N < ( v _In the relation of _GS-N -V _tN ), the NMOS is in the three-pole region. In this state, the current that the NMOS turns on can be expressed by the following equation: i _DN = k [2( v _GS-N - V _tN ) v _DS-N - v _DS-N ² ].

Secondly, if the voltage across the source and the drain of the NMOS, v _DS-N , and the voltage difference between the gate and the source, v _GS-N , and the threshold voltage V _tN , satisfy v _DS-N ≧ ( v ) _In the relationship of _GS-N - V _tN ), the operation mode of the NMOS is in a saturation region. In this state, the current that the NMOS turns on can be expressed by the following equation: i _DN = k ( v _GS-N - V _-Nt ) ² (1+ λ _DS-N ).

Based on the foregoing description, when the NMOS source, cross voltage v _DS-N is small between the drain current i _D and v _DS-N is proportional to the NMOS conduction, and also (v _GS-N -V _tN) It is proportional to the linear relationship of the third-order region (a) in the third-order region; when v _{DS-N is} gradually increased to a certain extent, the change of v _DS-N does not affect the NMOS-on current i _D , so The current conducted at the NMOS presents i _D as a horizontal line of the saturation region in the third graph (a).

That is to say, for the NMOS, the voltage across the source and the drain will affect the current value of i _D . Similarly, for PMOS, the voltage across the source and drain also affects the current value of i _D and affects its operating region, which is similar to NMOS and will not be described here.

According to the foregoing description of the voltage level of the control node S _cont of the charge pump, and the current relationship of the NMOS and PMOS when conducting, the following phenomenon can be seen: the voltage level on the control node S _cont of the charge pump When the gradual increase is gradually increased, the first voltage difference ΔV _{1 is} gradually decreased, and the second voltage difference ΔV _{1 is} gradually increased. That is, the voltage across the source and the drain of the PMOS is gradually reduced, and the voltage across the source and the drain of the NMOS is gradually increased.

For the PMOS, once the voltage across the source and the drain V _DS becomes smaller and becomes smaller to a certain extent, the representative PMOS will enter the triode from the saturation region. Once the PMOS mode of operation enters the tripolar region from the saturation region, the current value of the current I _P flowing through the PMOS will also decrease, and thus the PMOS (turns off the state) is turned off; for the NMOS, once When the voltage across the source and the drain (V _DS ) is gradually increased to a certain extent, the operating region representing the NMOS may enter the saturation region from the three-pole region, so that the current value of the current I _N flowing through the NMOS follows increase.

Please refer to the third diagram (b), which is a relationship diagram of the switching current provided by the PMOS and NMOS in the charge pump with respect to the voltage level change of the control signal. As can be seen from the figure, when the voltage level of the control node S _cont is gradually increased from 0 volts, the first switching current I _P and the second switching current I _N are accompanied by the voltage level of the control node S _cont . Increase and increase.

Once the voltage level V _{cont of the} control node S _cont continues to increase and reaches a certain level (eg, 0.9 volts), the first switching current I _P generated by the PMOS may reverse downward as the voltage becomes higher. However, for the NMOS, when the voltage level V _{cont of the} control node S _cont increases, the V _ds representing the NMOS increases across the voltage, so the NMOS remains continuously turned on, so the second switching current I _N when it is turned on remains Continued to increase.

Therefore, if the first switching current I _P and the second switching current I _N are summed, it can be seen that the net current flowing out of the charge pump is as shown in the third diagram (b) at the control node S _cont When the voltage level is less than 0.9 volts, the current value approaches zero. On the contrary, once the voltage level of the control node S _cont is greater than 0.9 volts, the current value of the first switching current I _P is insufficient to offset the current value of the second switching current I _N , resulting in the first switching current I _P and the second The net charge and discharge current I _CP formed by the sum of the switching currents I _N will increase rapidly.

It should be noted that the sum of the currents of the switching currents here needs to consider the directivity of the current. Since the flow direction of the first switching current I _p is opposite to the flow direction of the second switching current I _N , the sum of the two (ie, The current value that the charge pump actually outputs to the control node S _cont is equivalent to the difference between the absolute values of the current values.

In summary, it can be found that the higher the voltage level V _cont of the control node S _cont , the higher the frequency f _{out of the} output signal; the higher the frequency coefficient M, the higher the frequency f _{out of} the output signal. Therefore, it can be inferred that the higher the frequency coefficient M is, the higher the voltage level V _{cont of the} control node S _cont is.

In addition, since the voltage level V _{cont of the} control node S _cont also affects the charge and discharge current, theoretically, the larger the frequency coefficient M, the higher the current value of the charge and discharge current I _CP . However, when the voltage level V _{cont of the} control node S _cont is greater than a certain degree, the sum of the charge and discharge currents I _{CP may} not be zero due to the mismatch of the PMOS and the NMOS, resulting in the phase locked loop at the control node S _cont . When the voltage level V _{cont is} greater than a certain level, it cannot operate normally, which also limits the adjustable range of the frequency division coefficient M. To this end, the present invention provides a method of allowing the charge and discharge current I _CP generated by the charge pump to remain stable without being affected by voltage level changes.

In short, the idea of the present invention is to increase the operating range of the charge pump in response to the voltage level V _{cont of the} control node S _cont , and let the voltage of the net charge and discharge current I _{CP of the} output node S _{cont be} at the control node S _cont . When the level V _{cont is} large, it can maintain the state of 0, and it will not be affected by the PMOS being turned off, so that the adjustment of the charge and discharge current I _CP can be more flexible, and the phase-locked loop can be adjusted and removed. When the coefficient is M, the tolerance of the bandwidth variation is improved.

Please refer to the fourth figure (a), which is a functional block diagram of a preferred embodiment of the charge pump proposed by the present invention. The charge pump 30 for outputting current at the control node S _cont according to the phase comparison signal includes: setting a first current source group 31 between the first voltage endpoint V ₁ and the control node S _cont , and setting the control node S _cont and the two terminal voltage V ₂ of the second current source 32 is set. Selectively utilizing one of the first current source group 31 or the second current source group 32 by the phase comparison signal from the phase detector 101 to generate a charge and discharge current I _CP to the low pass filter at the control node S _cont .

First, the structure of the first current source group 31 is similar to the upper portion of the charge pump of the second figure (a), and is composed of a first current source (not shown) and a first switching unit (not shown). The first current source is electrically connected to the first voltage terminal V ₁ and is used to provide a fixed current (ie, the first switching current I _P ); and the first switching unit is electrically connected to the first current source and the control node S Between _cont , it is determined whether to output the first switching current I _P from the first current source group 31 according to the first phase comparison signal V _up . The first current source group 31 outputs the first switching current I _P at the control node S _cont according to the first phase comparison signal V _up .

In the preferred embodiment, the second current source group 32 has more components than the first current source group 31. Taking the fourth diagram (a) and (b) as an example, the second current source group 32 includes two. The sub-switching current generating circuits 321, 322, and a selection circuit 323. The internal structure of the second current source group 32 will be described below. First, the first sub-switching current generating circuit 321 and the second sub-switching current generating circuit 322 are electrically connected between the control node S _cont and the second voltage terminal V2. The voltage level of the control node S _cont is generated to generate a first sub-switching current I _NO , which in turn generates a second sub-switching current I _{NN in} response to the voltage level of the control node S _cont . That is to say, the change of the voltage level of the control node S _cont will affect the generation of the first sub-switching current I _NO and the second sub-switching current I _NN .

Further, the selection circuit 323 is electrically connected to the first sub-current generating circuit 321 is switched to the second switching sub-current generating circuit 322, the function selecting circuit 323 is the voltage level of the control node S _cont selected output to the control node S _cont The first sub-switching current I _NO or the second sub-switching current I _NN .

The selection circuit 323 uses the voltage level of the control node S _cont to select the basis for outputting the first sub-switching current I _NO or the second sub-switching current I _NN , which may vary due to application considerations, for example: using the control node S _cont the voltage level of the second voltage V _cont and the terminal voltage V ₂ a pressure difference, the pressure difference between the voltage level of the voltage V _cont S _cont of the control node to a voltage level of the comparison to select an output control node S _cont Current and other ways. The following description is taken as an example of the voltage difference between the voltage level V _{cont of the} control node S _cont and the second voltage terminal V ₂ .

In short, the purpose of the selection circuit 323 is to select a circuit below the charge pump 30 that should be output by the first sub-switching current generating circuit 321 or by the second sub-switching current generating circuit 322 to the control node S _cont . The selection of the reference bias voltage V _dc can be obtained by analog or the like. Generally, the value of the reference bias voltage V _dc can be a range, for example, the voltage level of the voltage source V _dd and the voltage across the source and the drain V. _sd difference (V _dd -V _sd) as a reference bias voltage V _dc, where V _{sd sd} V may be the minimum possible.

Referring to FIG. 4(b), which is a schematic diagram of a second current source group of charge pumps implemented by a comparator in a preferred embodiment of the present invention. This figure further illustrates the internal configuration of the first sub-current switching generating circuit 321, the second sub-current switching generating circuit 322, and the selecting circuit 323.

The first sub-switching current generating circuit 321 includes a first sub-switching unit 321a and a first sub-current source 321b. The first sub-switching unit 321a is electrically connected to the control node S _cont and is turned on when the voltage level V _{cont of the} control node S _cont is less than the reference bias voltage V _dc ; and the first sub-current source 321 b is electrically connected to the second voltage The terminal V ₂ and the first sub-switch unit 321a are provided to provide the first sub-switching current I _NO to the control node S _cont when the first sub-switch unit 321a is turned on.

The purpose of providing the first sub-switching current generating circuit 321 is to select the output first when the voltage voltage difference between the voltage level V _{cont of the} control node S _cont and the second voltage terminal V2 is less than the reference bias voltage V _dc . sub-switching current I _NO.

The second sub-switching current generating circuit 322 includes a second sub-switching unit 322a and a second sub-current source 322b. The second sub-switching unit 322a is electrically connected to the control node S _cont and is turned on when the voltage level V _{cont of the} control node S _cont is greater than the reference bias voltage V _dc ; and the second sub-current source 322 b is electrically connected to the second voltage The second sub-switching current I _{NN is} provided between the terminal V ₂ and the second sub-switch unit 322a, and when the second sub-switch unit 322a is turned on, the control node S _{cont is provided} .

The purpose of providing the second sub-switching current generating circuit 322 is to select the control node 323 when the voltage difference between the voltage level V _{cont of the} control node S _cont and the second voltage terminal V2 is greater than the reference bias voltage V _dc . S _cont outputs a second sub-switching current I _NN .

The selection circuit 323 mainly includes a comparison unit 323a electrically connected to the control node S _cont , and a control unit 323 b electrically connected to the first sub-switch unit 321 a and the second sub-switch unit 322 a. The two input terminals of the comparing unit 323a are respectively connected to the control node S _cont and the reference bias voltage V _dc , and the voltage comparison signal V _{cmp is} output according to the comparison result of the two. After receiving the voltage comparison signal _Vcmp , the control unit 323b may select to provide the first sub-switching current I _NO by the first sub-switching current generating circuit 321 or provide the second sub-switching current generating circuit 322 by the second sub-switching current generating circuit 322. Switch current I _NN .

Referring to Figure 5(a), a schematic diagram of a selection circuit is implemented in accordance with the teachings of the present invention. In addition to the comparing unit 323a and the control unit 323b, the selecting circuit 323 may further include an inverter 323c electrically connected between the comparing unit 323a and the control unit 323b, and the inverter 323c is used to invert the voltage comparison signal _Vcmp . V _cmp ' is obtained and output to the control unit 323b.

The present invention in response to a control voltage V _cont level variation on the node S _cont, comparing the voltage signal V _cmp its complement V _cmp 'respectively corresponding to different sub-promoter switching current generating circuit. For example, when the voltage level V _{cont of the} control node S _cont is less than the reference bias voltage V _dc , the voltage level of the voltage comparison signal V _cmp is 0 volt, which represents that the voltage comparison signal V _cmp is logic 0 and its complement is logic 1 In this state, the charge pump 30 generates the first sub-switching current I _NO .

Conversely, when the voltage level V _{cont of the} control node S _cont is greater than the reference bias voltage V _dc , the voltage level of the voltage comparison signal V _cmp is equivalent to V _dd , which represents that the voltage comparison signal V _cmp is logic 1 and its complement is logic In the state of 0, the charge pump 30 generates a second sub-switching current I _NN .

The control unit 323b may be further divided into: a first control block 3231 electrically connected to the comparison unit 323a and the first sub-switching current generating circuit 321, and electrically connected to the comparing unit 323a, depending on the controlled sub-switching current generating circuit. And a second control block 3232 of the second sub-switching current generating circuit 322, wherein the former is used to select to generate a first sub-switching current I _NO for selecting to generate a second sub-switching current I _NN .

That is, after receiving the voltage comparison signal _Vcmp and the inverted voltage comparison signal _Vcmp' , the control unit 323b selects the first sub-switching current generating circuit 321 to provide the first sub-switching current I. _NO , or a second sub-switching current I _{NN is} provided by the second sub-switching current generating circuit 322.

The first control block 3231 outputs a first control signal according to the voltage comparison signal _Vcmp , thereby turning on the first sub-switching unit 321a in the first sub-switching current generating circuit 321, and outputting the first sub-switching current _INO ; The second control block 3232 outputs a second control signal according to the reversed voltage comparison signal V _cmp ', thereby turning on the second sub-switch unit 322a in the second sub-switching current generating circuit 322, and outputting the second sub-switching Current I _NN .

The first control block 3231 includes a first semiconductor switching element 3201 and a second semiconductor switching element 3202, and the gates of the two are respectively connected to the inverted voltage comparison signal V _cmp ' and the voltage comparison signal V _cmp .

Wherein the first gate bipolar semiconductor switching element 3201 are electrically connected to the second phase comparison signal V _down switching unit 321a of the first sub-pole, when the first semiconductor switching element is turned on and 3201, put the second phase comparison signal The voltage level is turned on to the gate of the first sub-switch unit 321a, thereby providing the first sub-switching current I _NO on the control node S _cont ; and the two poles of the second semiconductor switching element 3202 are electrically connected to the first sub-switch respectively The gate of the cell 321a and the second voltage terminal V ₂ , when the second semiconductor switching element is turned on and turned on, turns on the voltage level (V _GND ) of the second voltage terminal V ₂ to the first sub-switch unit 321a The gate further stops providing the first sub-switching current I _NO on the control node S _cont .

The internal configuration of the second control block 3232 is quite similar to the internal configuration of the first control block 3231, and the second control block 3232 is composed of a third semiconductor switching element 3203 and a fourth semiconductor switching element 3204, the two semiconductor switches The gates of the components are respectively connected to the voltage comparison signal _Vcmp and the inverted voltage comparison signal _Vcmp '.

Wherein the third gate bipolar semiconductor switching element 3203 are electrically connected to the second phase comparison signal V _down switching unit and the second sub electrode 322a is, when the third semiconductor switching element is turned on and 3203, a second phase comparison signal put The voltage level of V _down is conducted to the gate of the second sub-switch unit 322a, thereby providing the second sub-switching current I _NN to the control node; and the two poles of the fourth semiconductor switching element 3204 are electrically connected to the second sub-switch unit, respectively. The gate of 322a, and the second voltage terminal V ₂ , when the fourth semiconductor switching element 3204 is turned on and turned on, turns on the voltage level (V _GND ) of the second voltage terminal to the second sub-switch unit 322a. The gate, in turn, stops providing the second sub-switching current I _NN on the control node S _cont .

A voltage comparison signal V _cmp manner connected point of view, the comparison voltage signal V _cmp is electrically connected to the second semiconductor switching element 3202 and the third semiconductor switching element 3203, and the voltage comparison signal V _cmp after reverse 'were electrically connected To the first semiconductor switching element 3201 and the fourth semiconductor switching element 3204.

It should be noted that the manner in which the voltage comparison signal V _cmp or the voltage comparison signal V _cmp ' inverted by the inverter 323c is connected to the first control block 3231 or the second control block 3232 is not limited, which is because the comparison unit 323a having positive, two negative input terminal, the input terminal connected to the control nodes based on these S _cont sequence differs from the reference bias voltage V _dc, the comparison unit 323a output by the voltage comparator signal V _cmp may change.

Please refer to the fifth figure (b), which uses the selection circuit design of the connection of the fifth figure (a), in response to the relationship between the voltage level of the control node and the reference bias voltage, and the node inside the control unit. Voltage level, and a list of open states of the semiconductor switching elements. It is assumed here that the voltage level of the second voltage terminal V2 is 0 volts, and the comparison unit 323a is a comparator whose forward input terminal is connected to the control node S _cont and the negative input terminal is connected to the reference bias voltage. V _dc . In practical applications, the way the comparator's forward input endpoint is connected to the negative input endpoint is not limited to this.

When the voltage level V _{cont of the} control node S _cont is lower than the reference bias voltage V _dc (ie, V _cont <V _dc ), the voltage level of the voltage comparison signal V _cmp output by the comparison unit 323a is 0, and its logic The state is 0, and its reversed logic state (ie its complement) is 1.

For the first control block 3231, since the gate of the first semiconductor switching element 3201 is electrically connected to the inverted voltage comparison signal _Vcmp ', it is in an on state; due to the gate connection of the second semiconductor switching element 3202 The voltage comparison signal V _{cmp is} thus presented in a closed state. That is, the voltage level of the second phase comparison signal _Vdown will be conducted through the first semiconductor switching element 3201, and the voltage level of the first node S1 is equivalent to the voltage level of the second phase comparison signal _Vdown . .

For the second control block 3232, since the gate of the third semiconductor switching element 3203 is connected to the voltage comparison signal _Vcmp , it is in a closed state; since the gate of the fourth semiconductor switching element 3204 is connected to the voltage comparison signal _Vcmp The complement is therefore rendered open. That is, the voltage level of the second phase comparison signal _Vdown will be transmitted through the fourth semiconductor switching element 3204, and the voltage level of the second node S2 is the voltage of the second voltage terminal V2, that is, 0. volt.

In summary, when the voltage level of the control node S _cont is lower than the reference bias voltage V _dc , the voltage level of the first node S1 is equivalent to the second phase comparison signal V _down , and the voltage level of the second node S2 is 0 volts, so that the first sub-switch unit 321a electrically connected to the first node S1 is thus turned on, and the second sub-switch unit 322a electrically connected to the second node S2 is thus turned off. This also means that in this state, the second current source group 32 provides only the first sub-switching current I _NO and does not provide the second sub-switching current I _NN .

When the voltage level of the control node S _cont is higher than the reference bias voltage V _dc (ie, V _cont >V _dc ), the voltage level of the voltage comparison signal V _cmp output by the comparison unit is V _dd , and the logic state thereof is 1, and the logic state of the reverse voltage comparison signal V _cmp ' is 0.

For the first control block 3231, since the gate of the first semiconductor switching element 3201 is connected to the reverse voltage comparison signal V _cmp ' with a logic state of 0, a closed state is exhibited; due to the gate of the second semiconductor switching element 3202 The pole is connected to a voltage comparison signal V _cmp with a logic state of 1, thus exhibiting an on state. That is, the voltage level (V _GND ) of the second voltage terminal V2 will pass through the conduction of the second semiconductor switching element 3202 such that the voltage level of the first node S1 is 0 volts.

For the second control block 3232, since the gate of the third semiconductor switching element 3203 is connected to the voltage comparison signal _{Vcmp having a} logic state of 1, it is in an on state; due to the gate of the fourth semiconductor switching element 3204, Connected to the reversed voltage comparison signal V _cmp ' with a logic state of 0, thus presenting a closed state. That is, the voltage level of the second phase comparison signal _Vdown will be transmitted through the third semiconductor switching element 3203, and the voltage level of the second node S2 is equivalent to the voltage level of the second phase comparison signal _Vdown . quasi.

In summary, when the voltage level V _{cont of the} control node S _cont is higher than the reference bias voltage V _dc , the voltage level of the first node S1 is 0 volts, and the voltage level of the second node is V _down , thus The first sub-switch unit electrically connected to the first node S1 is thus turned off, and the second sub-switch unit electrically connected to the second node S2 is thus turned on. This also means that in this state, the second current source group 32 provides only the second sub-switching current I _NN without providing the first sub-switching current I _NO .

Please refer to a sixth diagram, which is a schematic diagram of a second sub-switching current generating circuit in accordance with a preferred embodiment employed in accordance with the teachings of the present invention. In this figure, the second sub-switching current generating circuit 322 includes a current mirror composed of four semiconductor switching elements 3205 to 3208, and the reflected reference current is conducted to the control node S _cont through the second sub-switching unit 322a.

Through the negative feedback amplifier 3221, the voltage level V _{cont of the} control node S _cont will be conducted to the gate of the fifth semiconductor switching element 3205, and the conduction current will be reflected by the current mirror as the second sub-switching current I _NN use.

Hereinafter, when the voltage level V _{cont of the} control node S _cont is smaller than the reference bias voltage V _dc and the voltage level V _{cont of the} control node S _cont is greater than the reference bias voltage V _dc , respectively, using the seventh diagram (a) and (b), The on and off states of the semiconductor switching elements in the second current source group 32, and the changes in the internal node voltages of the second current source group 32.

Due to the state of the semiconductor switching elements in the second current source group 32, the corresponding changes with the nodes have been described in the fifth diagram (a) and (b), and only the present invention will be briefly described herein how the second current source group 32 is different. In the state, different currents are output at the control node S _cont .

Referring to FIG. 7( a ), the control node on the charge pump according to the preferred embodiment of the present invention selects the output of the first sub-switching current generating circuit when the voltage level thereof is less than the reference bias voltage. A schematic diagram of a sub-switching current.

When the voltage level V _{cont of the} control node S _cont is less than the reference bias voltage V _dc , the voltage comparison signal V _{cmp is} outputted as 0 volts, and the second semiconductor switching element 3202 and the third semiconductor switching element 3203 electrically connected thereto are thus turned off. . On the other hand, the voltage level of the inverted voltage comparison signal V _cmp ' is V _dd , and the first semiconductor switching element 3201 and the fourth semiconductor switching element 3204 electrically connected thereto are thus turned on.

As described above, since both the first semiconductor switching element 3201 and the fourth semiconductor switching element 3204 are turned on and turned on, the former turns on the second phase comparison signal V _down to the first sub-switching current generating circuit 321, which turns on V _GND . The second sub-switching current generating circuit 322 is connected. That is, the first sub-switching current I _NO generated by the first sub-current source 321b will be output to the control node S _cont , and the second sub-switching current I _NN will not be output to the control node S _cont . Therefore, in the seventh diagram (a), the second sub-switching current generating circuit 322 is indicated by a broken line, indicating that in this state, the second sub-switching current generating circuit 322 does not supply current to the control node S _cont .

Referring to FIG. 7(b), the control node of the preferred embodiment of the present invention is configured to control the output of the second sub-switching current generating circuit when the voltage level thereof is greater than the reference bias voltage. Schematic diagram of the two sub-switching currents.

When the voltage level V _{cont of the} control node S _cont is greater than the reference bias voltage V _dc , the voltage comparison signal is outputted as V _dd , and the second semiconductor switching element 3202 and the third semiconductor switching element 3203 electrically connected thereto are both turned on. On the other hand, since the reverse voltage comparison signal V _cmp ' is 0 volt, the gates of the first semiconductor switching element 3201 and the fourth semiconductor switching element 3204 electrically connected thereto are both turned off and not turned on.

As described above, since both the second semiconductor switching element 3202 and the third semiconductor switching element 3203 are turned on, the former turns on V _GND to the first sub-switching current generating circuit 321, and the latter turns on the second phase comparison signal V _down to The second sub-switches the current generating circuit 322. Therefore, the first sub-switching current I _NO generated by the first sub-current source 321b is not outputted to the control node S _cont , and the second sub-switching current I _NN is output to the control node S _cont . Therefore, in the seventh diagram (b), the first sub-switching current generating circuit 321 is indicated by a broken line, indicating that the first sub-switching current generating circuit 321 does not supply current in this state.

Depending PMOS innate characteristics the NMOS, resulting in the phenomenon of the charge pump output in net charge and discharge current does not match, the present invention proposes a charge pump design, the voltage level V _cont S _cont of dynamically according to the control node, Selectively adjusting the source of the discharge current can improve the PMOS on-current caused by the voltage level V _{cont of the} control node S _cont being high.

In other words, when the voltage level V _{cont of the} control node S _cont becomes large, the source of the discharge current actually supplied by the second current source group 32 also changes correspondingly, which is output from the first sub-switching current generating circuit 321 a sub-switching current I _NO, be changed from the second sub-case of the second sub-current generating circuit 322 switches the output of the switching current I _NN, can be improved when the output voltage is too high, the current of the PMOS and the NMOS not match.

Please refer to the eighth figure, which is a diagram showing the relationship between the current value of the first sub-switching current and the second sub-switching current and the output voltage after the second sub-switching current generating circuit is implemented in the preferred embodiment of the present invention.

The first part of the eighth figure illustrates that the current values of the first switching current I _P , the first sub-switching current I _NO and the second sub-switching current I _NN correspond to the voltage level change relationship of the control node S _cont .

As for the first switching current I _P , similar to the third figure ( b ), that is, when the voltage level of the control node S _cont is greater than the reference bias voltage V _dc , the current value of the first switching current I _P A reversed down situation occurs.

The first sub-switching current I _NO provided by the first sub-switching current generating circuit 321 is similar to the second switching current I _{N of the} third graph (b), when the voltage level V _{cont of the} control node S _cont is greater than the reference bias voltage At V _dc , the current value of the first sub-switching current I _NO will continue to increase.

The second sub-switching current I _NN provided by the second sub-switching current generating circuit 322 is a characteristic curve which is gradually increased and continues to slide in a process in which the voltage level of the control node S _cont gradually becomes larger. Briefly, the present invention utilizes the second sub-switching current I _NN to compensate the current value of the first sub-switching current I _NO , whereby the PMOS is used when the voltage level of the control node S _cont is greater than the reference bias voltage V _dc . The effect of mismatch with NMOS.

On the other hand, the second part of the eighth figure illustrates the net current after summing the currents of the first switching current I _P , the first sub-switching current I _NO and the second sub-switching current I _NN , corresponding to the control The voltage level of the node S _cont is V _cont . Since the first sub-switching current I _NO and the second sub-switching current I _NN having different characteristics are provided at the NMOS terminal, the voltages at the control node S _cont are respectively smaller than the reference bias voltage V _dc and greater than the reference bias voltage V _{dc .} Provides output current.

In other words, when the voltage level of the control node S _cont is less than the reference bias voltage V _dc , the first sub-switching current generating circuit 321 is used in conjunction with the first current group 31 , so the net charge generated by the charge pump 30 is used. The discharge current I _CP corresponds to the sum of the first switching current I _P and the first sub-switching current I _NO , that is, I _CP =I _P +I _NO .

When the voltage level of the control node S _cont is greater than the reference bias voltage V _dc , the second sub-switching current generating circuit 322 is used in conjunction with the first current group 31 , so the net charge and discharge current I _CP generated by the charge pump 30 That is equivalent to the sum of the first switching current I _P and the second sub-switching current I _NN , that is, I _CP =I _P +I _NN .

When the frequency of the output signal outputted by the phase-locked loop is higher, the charge and discharge current value of the charge pump outputted at the control node S _cont is also higher, and the control voltage of the voltage controlled oscillator is higher. Corresponding to the magnitude change of the voltage level of the second phase comparison signal _Vdown , the bias voltage input to the voltage controlled oscillator is changed.

The idea is to reduce the second switching current I _N of the NMOS, that is, when the voltage V _{cont of the} control node S _cont is greater than the reference bias voltage V _dc , the path of the current travel is another, when the two are combined, The phase-locked loop can be operated in a relatively wide range of frequencies.

Ideally, the output voltage of the phase locked loop can be locked at one frequency, but the lock (tacking) of the process, the control node S _cont voltage level V _cont still may change, once the control node of the voltage level S _cont When V _cont exceeds the reference bias voltage V _dc , the circuit behavior of the phase locked loop may become divergent.

In other words, the present invention provides a design for maintaining a net charge and discharge current in the case where the voltage level variation of the control node S _cont is large, thereby reducing the mismatch between the PMOS and the NMOS, possibly resulting in an output signal V _out and division. The influence of the frequency coefficient M.

According to the concept of the present invention, the current formed by the PMOS of the upper half of the charge pump and the current of the current of the NMOS of the lower half of the charge pump can be made uniform, so that the net charge and discharge current I _{CP is} even under control. When the voltage level of the node S _cont becomes large, it still approaches 0, that is, the operating range of the net charge and discharge current I _CP is more flexible. Once the operating range of the net charge and discharge current I _CP increases, in addition to improving the phase-locked loop when the voltage level of the control node S _cont becomes large, the divergence is lost because it cannot be locked, and the adjustment of the frequency-dividing coefficient M is not affected. The width K makes the phase-locked loop work better.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims.

The components included in the diagram of this case are listed as follows:

101‧‧‧ phase detector

103, 30‧‧‧ Charge pump

105‧‧‧Low-pass filter

107‧‧‧Voltage Controlled Oscillator

109‧‧‧Delephone

10‧‧‧ phase-locked loop

103a, 31‧‧‧First current source group

1031‧‧‧First current source

1033‧‧‧First switch

103b, 32‧‧‧second current source group

1032‧‧‧second current source

1034‧‧‧Second switch

321‧‧‧ first sub-switching current generating circuit

322‧‧‧Second sub-switching current generating circuit

323‧‧‧Selection circuit

321a‧‧‧First sub-switch unit

321b‧‧‧ first sub current source

322a‧‧‧Second sub-switch unit

322b‧‧‧Second sub-current source

323a‧‧‧Comparative unit

323b‧‧‧Control unit

323c‧‧‧ reverser

3231‧‧‧First Control Block

3232‧‧‧Second control block

3201‧‧‧First semiconductor switching element

3202‧‧‧Second semiconductor switching element

3203‧‧‧ Third semiconductor switching element

3204‧‧‧fourth semiconductor switching element

3221‧‧‧Amplifier

3205‧‧‧ Fifth semiconductor switching element

3206‧‧‧ sixth semiconductor switching element

3207‧‧‧ seventh semiconductor switching element

3208‧‧‧ eighth semiconductor switching element

The case can be further understood by the following figures and descriptions: The first figure is a schematic diagram of the phase-locked loop provided by the conventional technology.

The second figure (a) is a schematic diagram of a charge pump composed of a first current source group and a second current source group.

The second figure (b) shows the judgment signal output by the phase detector, corresponding to the clock map of the current output by the charge pump at its control node.

The third graph (a) is a characteristic curve in which the on-current of the NMOS corresponds to the change in the voltage across the source and the drain.

The third graph (b) is a graph showing the relationship between the switching current supplied by the PMOS and the NMOS in the charge pump with respect to the voltage level change of the control signal.

Figure 4 (a) is a functional block diagram of a preferred embodiment of the charge pump of the present invention.

Figure 4 (b) is a schematic diagram of a second current source set of charge pumps implemented by a comparator in a preferred embodiment of the present invention.

Figure 5 (a) is a schematic diagram of a selection circuit implemented in accordance with the teachings of the present invention.

Figure 5 (b), which uses the selection circuit design of the connection of the fifth diagram (a), in response to the magnitude relationship between the voltage level of the control node and the reference bias voltage, and the voltage level of the node inside the control unit A list of open states of the semiconductor switching elements.

Figure 6 is a schematic illustration of a second sub-switching current generating circuit in accordance with a preferred embodiment employed in accordance with the teachings of the present invention.

Figure 7 (a), which is a control of the preferred embodiment of the present invention on a charge pump The node selects a schematic diagram of outputting the first sub-switching current by the first sub-switching current generating circuit when the voltage level thereof is less than the reference bias voltage.

Figure 7 (b) is a control node of the preferred embodiment of the present invention. When the voltage level is greater than the reference bias, the second sub-switching current generating circuit outputs the second sub-subject. Schematic diagram of switching current.

Figure 8 is a diagram showing the relationship between the current value of the first sub-switching current and the second sub-switching current and the output voltage after the second sub-switching current generating circuit is implemented in the preferred embodiment of the present invention.

32‧‧‧Second current source group

321‧‧‧ first sub-switching current generating circuit

322‧‧‧Second sub-switching current generating circuit

323‧‧‧Selection circuit

321a‧‧‧First sub-switch unit

321b‧‧‧ first sub current source

322a‧‧‧Second sub-switch unit

322b‧‧‧Second sub-current source

323a‧‧‧Comparative unit

323b‧‧‧Control unit

Claims (10)

A charge pump outputs a current at a control node according to a phase comparison signal, the charge pump comprising: a first current source group disposed between a first voltage end point and the control node, a phase comparison signal outputs a first switching current at the control node; and a second current source group disposed between the control node and a second voltage terminal group, the second current source group comprising: a first sub-switch a current generating circuit electrically connected to the control node and the second voltage end point, wherein the first sub-switching current is generated due to the phase comparison signal; and a second sub-switching current generating circuit electrically connected to the control node The second voltage end point generates a second sub-switching current due to the phase comparison signal; and a selection circuit electrically connected to the first sub-switching current generating circuit and the second sub-switching current generating circuit, And selecting, according to a voltage level of the control node, the first sub-switching current or the second sub-switching current to be output by the control node. The charge pump according to claim 1, wherein the first current source group comprises: a first switch unit electrically connected to the control node, which is turned on according to the phase comparison signal; and a first The current source is electrically connected to the first voltage end point and the first switching unit, and the first switching current is provided on the control node due to the opening of the first switching unit. The charge pump according to claim 1, wherein the first sub-switching current generating circuit comprises: a first sub-switching unit electrically connected to the control node, wherein a voltage level of the control node is less than Turning on a reference bias voltage; and a first sub current source electrically connected between the second voltage terminal and the first sub-switch unit, the first sub-switch unit being provided to provide the first sub-switch unit Switching current to the control node. The charge pump according to claim 1, wherein the second sub-switching current generating circuit comprises: a second sub-switching unit electrically connected to the control node, wherein a voltage level of the control node is greater than Turning on a reference bias voltage; and a second sub current source electrically connected between the second voltage terminal and the second sub-switch unit, the second sub-switch unit being provided to provide the second sub-switch unit Switching current to the control node. The charge pump according to claim 1, wherein the current is output to the control node by the first current source group or the second current source group due to the phase comparison signal. The charge pump of claim 1, wherein the selection circuit initiates the first sub-switch when the voltage level of the control node and the voltage difference of the second voltage terminal are less than a reference bias voltage. A current generating circuit outputs the first sub-switching current at the control node. The charge pump of claim 1, wherein the selection circuit selects and outputs the second sub-voltage when a voltage difference between the voltage level of the control node and the second voltage end point is greater than a reference bias voltage. Switch the current. The charge pump according to claim 1, wherein the selection circuit comprises: a comparison unit electrically connected to the control node, which is output according to a comparison between a voltage level of the control node and a reference bias voltage. a voltage comparison signal; and a control unit electrically connected to the comparison unit, the first sub-switching current generating circuit and the second sub-switching current generating circuit, and selecting to switch by the first sub-subject according to the voltage comparison signal The current is generated by the current generating circuit or by the second sub-switching current generating circuit. The charge pump of claim 8, wherein the selection circuit further comprises an inverter electrically connected between the comparison unit and the control unit, and the reversed voltage comparison signal is output to The control unit. The charge pump according to claim 8 , wherein the control unit comprises: a first control block electrically connected to the comparison unit and the first sub-switching current generating circuit, and comparing signals according to the voltage And outputting a first control signal, thereby turning on a first sub-switching unit in the first sub-switching current generating circuit to output the first sub-switching current; and a second control block electrically connected to the comparison And a second sub-switching current generating circuit that outputs a second control signal according to the voltage comparison signal, thereby turning on a second sub-switching unit in the second sub-switching current generating circuit to output the first The second sub-switches the current.