JP4539555B2 - Charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit used in a PLL circuit used as a frequency synthesizer, a clock generation circuit, or the like in the field of communication or the like.

  The PLL is a feedback circuit that is widely used as a frequency synthesizer or a clock generation circuit in the field of communication or the like and compares the phases of an input signal and an output signal. A block diagram of the charge pump type PLL circuit is shown in FIG. The PLL in this block performs an operation of locking the output of the VCO to a frequency N / A times the reference signal.

  The operation of the PLL shown in FIG. 9 is as follows. First, the output signal of the VCO input to the PLL is divided by N by the main counter, and the reference signal is divided by A by the reference counter. The phase frequency comparator compares the outputs of the two counters and outputs a charge control signal (up signal) or a discharge control signal (down signal) according to the phase difference between the two signals. The charge pump circuit to which this control signal is input outputs a charging current to the next-stage loop filter when the up signal is ON and a discharging current when the down signal is ON. The loop filter smoothes the pulsed output current and performs current-voltage conversion, and applies the output voltage to the control voltage terminal of the VCO. Here, which phase difference is advanced by the phase frequency comparator depends on the polarity of the VCO. By continuously performing the above operation, the frequency of the VCO can be converged to N / A times the frequency of the reference signal.

  As described above, the charge pump circuit included in the PLL circuit is a circuit that generates a charging current or a discharging current in accordance with the control signal output from the phase frequency comparator and supplies it to the load (loop filter). This is a circuit that outputs the current that is the source of the control voltage supplied to the VCO. If this output current is not generated accurately following the control signal from the phase frequency comparator, the phase noise and spurious of the VCO output signal will increase. Leads to.

  FIG. 7 shows a configuration of a conventional charge pump circuit. Sup is a charging control signal (up signal), Sdw is a discharging control signal (down signal), MP1 is a charging current source transistor, MN1 is a discharging current source transistor, SW1 is a SPST switch for controlling charging current, and SW2 is An SPST switch for controlling discharge current, Tout is an output terminal, and VDD is a power source. Also, an appropriate bias voltage corresponding to the current output from the current source transistor is applied to Vgp and Vgn.

  When the up signal Sup is turned ON, the switch SW1 is closed and the source of the charging current source transistor MP1 is pulled up to the power supply potential. At this time, a current corresponding to the potential between the gate and the source of the transistor is discharged from the drain of MP1 and output from the output terminal. Conversely, when the up signal Sup is turned off, the switch SW1 is opened and the charging current is cut off. Similarly to this, when the down signal Sdw is turned ON, the SW2 is closed and the charging current is pulled out from the output terminal, and when the down signal Sdw is turned OFF, the SW2 is opened to cut off the charging current. .

JP 2000-151398 A

  However, in the conventional circuit of FIG. 7, when SW1 changes from an open state to a closed state, the source potential of the current source transistor MP1 changes abruptly, so that the gate-source capacitance of the current source transistor MP1 is sufficient. If the battery cannot be charged at a high speed, there arises a problem that the gate potential follows the change in the source potential and is not constant. That is, the process follows that the gate potential of the current source transistor changes from a certain initial value Vgp0 to near the power supply potential and then returns to Vgp0. At this time, since the gate-source voltage of the current source transistor changes slowly, a delay occurs in the rise of the output current from this transistor. FIG. 8 is a voltage / current waveform diagram of each part for explaining this operation. Although the operation at the time of charging is shown here, the operation at the time of discharging is the same, and the rise of the discharge current when SW2 changes from the open state to the closed state is delayed due to the gate-source capacitance of MN1. appear.

  When the rise of the charge / discharge current is delayed, if the up signal and down signal input to the charge pump circuit are short pulses, SW1 or SW2 is turned off before the current completely rises, and is proportional to the pulse width. Thus, it becomes impossible to charge and discharge the accurate charge to the output, and a dead zone occurs. This means that if the phase difference between the input and output signals of the PLL is smaller than a certain value, no output from the charge pump circuit is generated, so that the VCO cannot be controlled, leading to an increase in phase noise. .

  The present invention has been made to solve the above problems, and prevents fluctuations in the gate potential of the current source transistor even when the up signal and down signal input to the charge pump circuit are short pulses. An object of the present invention is to provide a charge pump circuit in which the rise time of the output current is reduced, the device operates at high speed, and the dead zone is reduced.

The charge pump circuit according to the present invention includes a charging current source transistor and a charging dummy transistor biased to each gate terminal in common from the first bias voltage terminal, and a bias to each gate terminal in common from the second bias voltage terminal. has been discharging current source transistor and the discharging dummy transistors, are connected to the source terminal of the charging dummy transistor and the charging current source transistor, to vary based on the potential of each source terminal to the charging control signal First switching means and second switching means are connected to the source terminals of the discharge current source transistor and the discharge dummy transistor, respectively, and change the potential of each source terminal based on the discharge control signal. 3 switching means and 4th switching means, the charging current source transistor And an output terminal connected to each drain terminal of the discharging current source transistor and outputting a charging current or a discharging current from each drain terminal, the first switching means and the second switching means the charging current source transistor and the potential of each source terminal of said charging dummy transistors, one of the amount of increase in the potential at the source terminal and the other for charging to equal properly the decrease in the potential at the source terminal Switching is performed based on a control signal, and the third switching unit and the fourth switching unit increase the potential of each source terminal of the discharge current source transistor and the discharge dummy transistor, and increase the potential at one source terminal. in which switching based on the discharging control signal to equal properly the decrease in the potential of an amount and the other of the source terminal.

  In the present invention, the first switching means and the second switching means use the potentials of the source terminals of the charging current source transistor and the charging dummy transistor as the potential increase amount at one source terminal and the other source terminal, respectively. The third switching means and the fourth switching means switch the potentials of the source terminals of the discharge current source transistor and the discharge dummy transistor to one side, so that the amount of decrease in the potential is substantially equal. Because the switching is performed based on the discharge control signal so that the amount of increase in potential at the source terminal and the amount of decrease in potential at the other source terminal are substantially equal, the up signal and down signal input to the charge pump circuit are short. Even when it is a pulse, it prevents fluctuations in the gate potential of the current source transistor, shortens the rise time of the output current, and operates at high speed The effect obtained by the charge pump circuit dead zone is reduced.

Embodiment 1 FIG.
1 is a circuit configuration explanatory diagram showing a charge pump circuit according to Embodiment 1 of the present invention. Here, Sup is a charging control signal (up signal), Sdw is a discharging control signal (down signal), MP1 is a charging current source transistor, MN1 is a discharging current source transistor, and Vgp and Vgn are current sources. An appropriate bias voltage corresponding to the current output from the transistor is applied. Tout is an output terminal, and VDD is a power supply. SWC1 is a charge current control switch circuit, and SWC2 is a discharge current control switch circuit, which controls ON / OFF of currents output from the drains of the current source transistors MP1 and MN1. MP2 is a charging dummy transistor having the same size as MP1, and its gate terminal is connected to the gate terminal of MP1. Similarly, MN2 is a discharge dummy transistor having the same size as MN1, and its gate terminal is connected to the gate terminal of MN1. SW3 is an SPDT switch for switching and connecting the source terminal of MP2 to constant potential Vp1 or constant potential Vp2, and SW4 is an SPDT switch for switching and connecting the source terminal of MN2 to constant potential Vn1 or constant potential Vn2. is there.

  Here, by making the charging current source transistor MP1 and the discharging current source transistor MP2 the same size, the charge charge of the gate-source capacitance of MP1 and the gate-source of MP2 when Sup is switched. Capacitance discharge charges can be made equal. Similarly, by setting the charging dummy transistor MN1 and the discharging dummy transistor MN2 to have the same size, the charging charge of the gate-source capacitance of MN1 and the discharging charge of the gate-source capacitance of MN2 can be made equal. In addition, since the rise of the charging current is delayed due to the difference in size of these transistors, each transistor is selected within an allowable range.

  Here, the operation during charging will be described. FIG. 2 is a voltage / current waveform diagram of each part for explaining the operation. When the up signal Sup changes from OFF to ON, the state of the switch circuit SWC1 changes, and the current flows to MP1. At this time, the source potential of MP1 changes from a certain constant potential Vsp1A to Vsp1B. At the same time, the state of SW3 is changed by the up signal Sup, and the source potential of MP2 is switched from Vp2 to Vp1. However, the potentials of Vp1 and Vp2 are set so that the potential difference is equal to the potential difference between Vsp1A and Vsp1B.

  Note that the requirement of matching accuracy between the potential difference between Vp1 and Vp2 and the potential difference between Vsp1A and Vsp1B relates to how far the rising delay of the charging current is allowed. Further, in this embodiment, the case where both the transistor size and the potential difference are equal has been described as an example, but theoretically, the product of the transistor size and the potential difference may be selected to be equal, and the rising of the charging current Select within the allowable range of delay.

  As described above, when the up signal changes from OFF to ON, the source potentials of MP1 and MP2 change in the opposite direction by the same potential. Also, here, MP1 and MP2 are illustrated using the same size transistors, and the gate-source capacitances are also equal. For this reason, the fluctuation of the gate potential Vgp which has occurred in the conventional circuit described with reference to FIG. 7 is canceled out by the two transistors and does not occur here. That is, the output drain current value (Ip) from MP1 can rise at high speed without causing a delay from the Sup input.

  The operation during discharging is the same as during charging. By setting the potentials of Vn1 and Vn2 so that the same amount of change as the source potential change of MN1 due to the operation of the switch circuit SWC2 occurs in the reverse direction when the down signal changes from OFF to ON, The influence of the source-to-source capacitance can be offset by the gate-source capacitance of MN2, and the gate potential Vgn can be kept constant. That is, the output current of MN1 can be raised at high speed.

Next, in the operation at the time of charging and discharging, the gate potential of the charging current source transistor MP1 or the discharging current source transistor MN1 is set to the initial value without injecting / releasing charges from the bias circuit for applying Vgp and Vgn. Explain why you can keep it.
First, paying attention to only the charging current source transistor MP1, when Sup changes from OFF to ON, in order to keep the gate voltage of MP1 at the initial value Vgp0, the charge of (Vsp1B−Vsp1A) × Cgsmp1 Must be injected into the gate electrode. (However, Cgsmp1 is the capacitance between the source and gate of MP1.) However, in general, a bias circuit that provides Vgp suppresses current consumption and has a low charge supply capability, so it takes time to inject charges from the bias circuit. , The time until the gate voltage of MP1 returns to Vgp0 again increases. That is, when there is no charging dummy transistor MP2, the rise of the drain current is delayed.
Next, consider the operation of the charging dummy transistor MP2. When Sup changes from OFF to ON, the source voltage of MP2 changes from Vp2 to Vp1. Therefore, in order to keep the gate voltage of MP2 at the initial value Vgp0, the charge of (Vp2−Vp1) × Cgsmp2 is discharged from the gate electrode. There is a need to. (However, Cgsmp2 is the source-gate capacitance of MP2.)
Here, in the circuit of FIG. 1, (Vsp1B−Vsp1A) and (Vp2−Vp1) are set equal, and the transistor sizes of MP1 and MP2 are equal, so Cgsmp1 = Cgsmp2. That is, the amount of charge injected into MP1 is equal to the amount of charge released from MP2. That is, since the gate potential of MP1 can be maintained at the initial value Vgp0 without injecting / releasing charges from the bias circuit that applies Vgp, the drain current can be rapidly raised from MP1 after Sup is turned ON. Can do.
The operation during discharging is the same as during charging. When the down signal changes from OFF to ON, the potentials of Vn1 and Vn2 are such that a change amount having the same value as the source potential change amount of MN1 due to the operation of the switch circuit SWC2 and having the opposite sign occurs in the source potential of MN2. It is set. Here, since the transistor sizes of MN1 and MN2 are the same, the gate-source capacitance is also the same, and it is the same as the operation principle at the time of charging. The charge exchange is canceled by the charge injection and the charge discharge from the gate electrode of MN2, and Vgn is held at a constant value. That is, the drain current from MN1 after Sdw changes to ON can be raised at high speed.

  Therefore, according to the charge pump circuit according to the first embodiment of the present invention, the fluctuation of the gate potential of the charging current source transistor is reduced, the rise time of the output current is short, and the charge pump circuit can operate at high speed. Even when the up signal and the down signal input to the circuit are short pulses, there is an effect that a charge pump circuit with a reduced dead zone can be obtained.

Embodiment 2. FIG.
FIG. 3 is a circuit configuration explanatory view showing a charge pump circuit according to Embodiment 2 of the present invention. Here, the switch circuit SWC1 shown in FIG. 1 is an SPST switch inserted between the power supply VDD and the source of the charging current source transistor MP1, and the switch circuit SWC2 is connected to the ground and the source of the discharging current source transistor MN1. A charge pump circuit in the case of an SPST switch inserted between the two is illustrated. Here, SW3 is an SPDT switch that switches and connects the source of the charging dummy transistor MP2 to either the power source or the output terminal Tout of the charge pump circuit. SW4 is the source of the discharging dummy transistor MN2 connected to the ground. It is an SPDT switch that is connected to one of the output terminals Tout of the charge pump circuit.

  When the up signal Sup is OFF, since SW1 is open, Vsp1 is equal to the output terminal voltage Vout. Here, when the up signal changes to ON, SW1 is closed and Vsp1 becomes equal to VDD. As for SW3, the operation of connecting the source of the dummy transistor MP2 to VDD when the up signal Sup is OFF and connecting it to the output terminal Tout when the up signal is ON is performed. That is, when the up signal Sup changes from OFF to ON, the source potential of the charging current source transistor MP1 changes by (VDD−Vout), and the source potential of the charging dummy transistor MP2 changes by (Vout−VDD). .

  From the above operation, similarly to the description in the first embodiment, the sizes of MP1 and MP2 are the same and the gate-source capacitance is also the same, so that the charge injected into the gate of MP1 and the gate of MP2 are released. The charge is canceled and the gate potential Vg1 of MP1 and MP2 is kept at a constant potential. That is, the drain current from MP1 can be raised at high speed.

  The same applies to the operation on the discharge side. When the down signal Sdw changes from OFF to ON, the source potential of the discharge current source transistor MN1 changes by (−Vout), and the source potential of the discharge dummy transistor MN2 changes by (Vout). Since the gate-source capacitances of MN1 and MN2 are equal, the charge injected into the gate of MN1 and the charge released from the gate of MN2 are canceled, and the gate potential Vg2 is kept constant. Therefore, a fast rise of the discharge current is realized.

  Therefore, according to the charge pump circuit according to the second embodiment of the present invention, the fluctuation of the gate potential of the charging current source transistor is reduced, the rise time of the output current is short, and the charge pump circuit can operate at high speed. Even when the up signal and the down signal input to the circuit are short pulses, there is an effect that a charge pump circuit with a reduced dead zone can be obtained.

Embodiment 3 FIG.
FIG. 4 is a circuit configuration explanatory diagram showing a charge pump circuit according to Embodiment 3 of the present invention. FIG. 4 is a modification of FIG. 3 illustrated in the second embodiment, and an operational amplifier OP1 used as a buffer is inserted in a path connecting the output terminals Tout and SW3 and SW4 of the charge pump circuit. OP1 connects Tout to the positive phase input terminal and directly connects the output of OP1 to the negative phase input terminal to apply negative feedback. As a result, when the SW3 and SW4 sides are viewed from Tout, the parasitic capacitance on the switch side is not visible, and the potential change of Tout is suppressed when SW3 and SW4 operate. Since a potential change not caused by the charging / discharging current of Tout leads to an increase in the VCO output spurious, the insertion of OP1 realizes a reduction in the VCO output spurious.

Embodiment 4 FIG.
FIG. 5 is a circuit configuration explanatory view showing a charge pump circuit according to Embodiment 4 of the present invention. 1 is an example of a charge pump circuit in which the switch circuit SWC1 and the switch circuit SWC2 in the charge pump circuit of FIG. 1 illustrated in Embodiment 1 are SPDT switches. The source terminal of the current source transistor MP1 is switched and connected to either the constant potential Vp4 or the constant potential Vp3 by SW1, and the source terminal of the current source transistor MN1 is connected to either the constant potential Vn3 or the constant potential Vn4 by SW2. . Here, Vp4 is higher than (Vg1 + MP1 threshold voltage), Vp3 is lower than (Vg1 + MP1 threshold voltage), Vn4 is lower than (Vg2-MN1 threshold voltage), and Vn3 is (Vg2-MN1 threshold voltage). ) It is set to a higher potential.

  The switches SW1 and SW3 connect the source of MP1 to Vp4 and the source of MP2 to Vp1 when the up signal Sup is ON, and connect the source of MP1 to Vp3 and the source of MP2 to Vp2 when Sup is OFF To perform the operation. The switches SW2 and SW4 connect the source of MN1 to Vn4 and the source of MN2 to Vn1 when the down signal Sdw is ON, and the source of MN1 to Vn3 and the source of MN2 to Vn2 when Sdw is OFF. The operation to connect to is performed. Here, (Vp4-Vp3) = (Vp2-Vp1) and (Vn3-Vn4) = (Vn1-Vn2) are established.

Therefore, in the case of the circuit of FIG. 5 as well, the same principle as in the first embodiment is established, and the fluctuation of the gate potential of the current source transistor can be prevented at the rise of the charge output current or the discharge output current. Can be reduced.
Here, the difference from the first embodiment is the fall time when the output current is cut off.
For example, in the case of the circuit of FIG. 3, when Sup changes from ON to OFF, SW1 is opened and the charging current output from the drain of MP1 is cut off, but the charge accumulated in MP1 can only be discharged to the output terminal. Therefore, there is a problem that the fall time of the current after SW1 is opened becomes long.
In the case of the configuration shown in FIG. 5, when Sup changes from ON to OFF, the source potential of MP1 is forcibly connected to a low potential (Vp3), so that the charge in MP1 is released to the source side. The fall time of the drain current is reduced. Similarly, when Sdw changes from ON to OFF, the charge in MN1 is released to the source side, and the fall time of the drain current is reduced.

  The dummy transistors MP2 and MN2 not only prevent the gate potential from changing when the up signal Sup and the down signal Sdw change from OFF to ON, but also to the gate electrode of the current source transistor when changing from ON to OFF. Since the charge / discharge charges are supplied, fluctuations in the gate potential can be suppressed.

Embodiment 5 FIG.
FIG. 6 is an explanatory circuit diagram showing a charge pump circuit according to Embodiment 5 of the present invention. FIG. 6 is a modification of FIG. 5 illustrated in the fourth embodiment, in which Vp4, Vp2, Vn3, and Vn1 are set to the ground potential, and Vp3, Vp1, Vn4, and Vn2 are set to the power supply potential. By connecting these terminals to a power supply or ground potential, a stable voltage can be constantly applied to the source potential of each current source transistor and dummy transistor, and bias circuits that generate potentials Vn1 to Vp4 and Vp1 to Vp4 are also provided. It becomes unnecessary. In addition, since the charge / discharge time of the current source transistor is increased by the dummy transistor, the speed reduction can be prevented even when the source potential is applied with a large amplitude from the ground potential to the power supply potential.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration explanatory diagram for describing a configuration of a charge pump circuit according to a first embodiment of the present invention; It is a figure for demonstrating operation | movement of the charge pump circuit concerning Embodiment 1 of this invention. It is a configuration explanatory view for explaining the configuration of a charge pump circuit according to a second embodiment of the present invention. It is a configuration explanatory diagram for explaining the configuration of a charge pump circuit according to a third embodiment of the present invention. It is a configuration explanatory diagram for explaining the configuration of a charge pump circuit according to a fourth embodiment of the present invention. It is a configuration explanatory diagram for explaining the configuration of a charge pump circuit according to a fifth embodiment of the present invention. It is a configuration explanatory diagram for explaining the configuration of a conventional charge pump circuit. It is a figure for demonstrating operation | movement of the conventional charge pump circuit. It is a block diagram which shows the conventional charge pump type PLL circuit.

Claims (6)

A charging current source transistor and a charging dummy transistor biased to each gate terminal in common from the first bias voltage terminal, and a discharging current source transistor and discharge biased to each gate terminal in common from the second bias voltage terminal First switching means connected to each source terminal of the dummy transistor for charging, the charging current source transistor, and the charging dummy transistor, respectively, for changing the potential of each source terminal based on the charging control signal; Switching means, third switching means and fourth switching connected to the source terminals of the discharging current source transistor and the discharging dummy transistor, respectively, for changing the potential of each source terminal based on the discharging control signal Each of the charging current source transistor and the discharging current source transistor Are commonly connected to the drain terminal, an output terminal, for outputting a charging current or discharging current from said respective drain terminals,
The first switching unit and the second switching unit are configured to change the potential of each source terminal of the charging current source transistor and the charging dummy transistor between the amount of increase in potential at one source terminal and the other source terminal. switch based on the charging control signal to equal properly the decrease of the potential, the source terminal of said third switching means and said fourth switching means dummy transistor for discharging the discharging current source transistor potential, the charge pump circuit for switching on the basis of the discharge control signal so as to equal properly the decrease in potential at the increase and the other of the source terminal of the potential at one of the source terminal of the. 2. The charge pump circuit according to claim 1, wherein the first switching means is a first switch circuit connected to a power source, and the potential of the source terminal of the charging current source transistor is based on the power source by the charging control signal. Switching to potential and open, the second switching means is a first SPDT switch for switching to connection to a binary potential, and the potential of the source terminal of the charging dummy transistor is set to the binary value by the charging control signal. The third switching means is a second switch circuit connected to the ground, the potential of the source terminal of the discharging current source transistor is switched to the ground potential and the open by the discharging control signal, The switching means of 4 is a second SPDT switch for switching to connection to a binary potential, and the discharge control signal A charge pump circuit, characterized in that more switches the potential of the source terminal of the discharging dummy transistor to the potential of the 2 values. 2. The charge pump circuit according to claim 1, wherein the first switching means is a first SPST switch connected to a power source, and the potential of the source terminal of the charging current source transistor is based on the power source by the charging control signal. A third SPDT switch that switches between the potential and the open, and the second switching means switches to the connection between the power source and the output terminal, and the potential of the source terminal of the dummy dummy transistor for charging is controlled by the control signal for charging. The third switching means is a second SPST switch that connects to the ground, and the potential of the source terminal of the discharge current source transistor is set to the ground by the discharge control signal. Switch to potential and open, and switch the fourth switching means to the ground and the output terminal. A charge pump circuit, characterized in that the fourth SPDT switch for switching the connection switches the potential of the source terminal of the discharging dummy transistor by the discharge control signal to the potential of the output terminal and the ground potential. 4. The charge pump circuit according to claim 3, wherein a positive phase input terminal is connected to the output terminal, an output is inputted to the negative phase input terminal, negative feedback is applied, and an output terminal is connected to the third SPDT switch and the fourth output terminal. A charge pump circuit comprising: an operational amplifier commonly connected to the SPDT switch; and the third SPDT switch and the fourth SPDT switch connected to the output terminal via the operational amplifier. 2. The charge pump circuit according to claim 1, wherein the first switching means is a fifth SPDT switch for switching to connection to a binary potential, and the potential of the source terminal of the charging current source transistor is determined by the charging control signal. Is switched to the binary potential, and the second switching means is switched to the connection to the binary potential to form a sixth SPDT switch, and the potential of the source terminal of the charging dummy transistor is changed by the charging control signal. A seventh SPDT switch for switching to a binary potential and switching the third switching means to a connection to a binary potential is used, and the potential of the source terminal of the discharge current source transistor is set to the 2 by the discharge control signal. Switch to the potential of the value, and the fourth switching means is the eighth SPDT switch to switch to the connection to the binary potential, A charge pump circuit the potential of the source terminal of the discharging dummy transistor by the discharge control signal and switches the potential of the 2 values. 2. The charge pump circuit according to claim 1, wherein the first switching means is a ninth SPDT switch for switching between connection to a power source and ground, and the potential of the source terminal of the charging current source transistor is set by the charging control signal. A tenth SPDT switch that switches between the potential based on the power source and the ground potential, and the second switching unit switches to the connection between the power source and the ground, and the charge control signal causes the source terminal of the charging dummy transistor to An eleventh SPDT switch for switching the potential between the power source potential and the ground potential and the third switching means for switching to the connection between the power source and the ground, and a source terminal of the discharge current source transistor by the discharge control signal Is switched between the power supply potential and the ground potential. The switching means is a twelfth SPDT switch that switches the connection to the power supply and the ground, and the potential of the source terminal of the discharge dummy transistor is switched between the power supply potential and the ground potential by the discharge control signal. Charge pump circuit.

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