JPS621434U

JPS621434U -

Info

Publication number: JPS621434U
Application number: JP9190685U
Authority: JP
Priority date: 1985-06-18
Filing date: 1985-06-18
Publication date: 1987-01-07

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例の接続図、第２図
はこの考案の一実施例の説明に用いる接続図、第
３図は従来の出力変換回路の一例の接続図、第４
図は従来の出力変換回路の一例の説明に用いる接
続図である。図面における主要な符号の説明、１，２：ＥＣ
Ｌを構成するトランジスタ、８：エミツタフロワ
トランジスタ、１０：ＰＮＰ型トランジスタ、１
１：抵抗、１２：出力端子。 Fig. 1 is a connection diagram of an embodiment of this invention, Fig. 2 is a connection diagram used to explain an embodiment of this invention, Fig. 3 is a connection diagram of an example of a conventional output conversion circuit, and Fig. 4 is a connection diagram of an example of a conventional output conversion circuit.
The figure is a connection diagram used to explain an example of a conventional output conversion circuit. Explanation of main symbols in the drawings, 1, 2: EC
Transistors constituting L, 8: emitter floor transistor, 10: PNP transistor, 1
1: Resistor, 12: Output terminal.

Claims

[Scope of utility model registration request]

The output of the differential circuit is supplied to the base of an NPN transistor whose emitter is grounded via a constant current source and whose collector is connected to a power supply terminal via a resistor.
Connect the emitters of the NPN type transistors and
An output conversion circuit, wherein the base of the PNP transistor is connected to the emitter of the PNP transistor, and a current output terminal is derived from the collector of the PNP transistor.