JPS6381539U

JPS6381539U -

Info

Publication number: JPS6381539U
Application number: JP17622386U
Authority: JP
Priority date: 1986-11-17
Filing date: 1986-11-17
Publication date: 1988-05-28

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示す回路図、及
び第２図は従来のクランプ回路を示す回路図であ
る。８，１１……差動増幅回路、９，１０，１２，
１３……トランジスタ、１４，１５……抵抗、１
６……基準電源、１７，１８……電流源。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional clamp circuit. 8 , 11 ... Differential amplifier circuit, 9, 10, 12,
13...Transistor, 14,15...Resistor, 1
6... Reference power supply, 17, 18... Current source.

Claims

[Scope of utility model registration request]

1 a first differential amplifier circuit including first and second transistors whose emitters are commonly connected; a second differential amplifier circuit including third and fourth transistors whose emitters are commonly connected; a first and second resistor connected in series between the bases of the four transistors, a reference power source that applies a reference voltage to a midpoint between the first and second resistors, and a current that is supplied to the first and second resistors. a first current source that
a second current source for attracting current flowing through the resistor; means for applying an input signal to a common base of the second and third transistors; and an output circuit connected to a common collector of the second and fourth transistors. A clamp circuit consisting of