JPS6387923U - - Google Patents
Info
- Publication number
- JPS6387923U JPS6387923U JP18233986U JP18233986U JPS6387923U JP S6387923 U JPS6387923 U JP S6387923U JP 18233986 U JP18233986 U JP 18233986U JP 18233986 U JP18233986 U JP 18233986U JP S6387923 U JPS6387923 U JP S6387923U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- terminal
- collector
- transistors
- commonly connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
第１図は本考案の一実施例、第２図は従来例お
よび第３図は第１図、第２図の回路動作を説明す
るための状態遷移図を示す。
１００，２００…ＲＳラツチ回路、Ｔｒ１〜Ｔ
ｒ２０…トランジスタ、…セツト信号入力端子
、…リセツト信号入力端子、Ｑ…出力端子、Ｉ
…インジエクシヨン電流供給端子。
FIG. 1 shows an embodiment of the present invention, FIG. 2 shows a conventional example, and FIG. 3 shows a state transition diagram for explaining the circuit operation of FIGS. 1 and 2. 100,200...RS latch circuit, Tr1~T
r20...transistor,...set signal input terminal,...reset signal input terminal, Q...output terminal, I
...Injection current supply terminal.
Claims (1)
タとは異極性の第２のトランジスタ、第３のトラ
ンジスタから成り、 前記第１のトランジスタのエミツタをインジエ
クシヨン電流供給端子とし、該第１のトランジス
タのベースは第２のトランジスタのコレクタと共
通接続してこれを端子とし、前記第１のトラン
ジスタのコレクタは前記第２および第３のトラン
ジスタのベースと共通接続してこれを端子とし
、前記第３のトランジスタのコレクタを出力端子
とし、前記第２および第３のトランジスタのエミ
ツタはコモン電位に接続したことを特徴とするＲ
Ｓラツチ回路。[Claims for Utility Model Registration] Consisting of a first transistor, a second transistor and a third transistor of different polarity from the first transistor, the emitter of the first transistor is used as an injection current supply terminal, The base of the first transistor is commonly connected to the collector of the second transistor to use this as a terminal, and the collector of the first transistor is commonly connected to the bases of the second and third transistors to use this as a terminal. , wherein the collector of the third transistor is an output terminal, and the emitters of the second and third transistors are connected to a common potential.
S latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18233986U JPH046268Y2 (en) | 1986-11-26 | 1986-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18233986U JPH046268Y2 (en) | 1986-11-26 | 1986-11-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6387923U true JPS6387923U (en) | 1988-06-08 |
| JPH046268Y2 JPH046268Y2 (en) | 1992-02-20 |
Family
ID=31128044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18233986U Expired JPH046268Y2 (en) | 1986-11-26 | 1986-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046268Y2 (en) |
-
1986
- 1986-11-26 JP JP18233986U patent/JPH046268Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH046268Y2 (en) | 1992-02-20 |
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