JPS6374828U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a flip-flop circuit according to an embodiment of this invention, Fig. 2 is a waveform diagram showing its operating timing, Fig. 3 is a circuit diagram showing a conventional flip-flop circuit, and Fig. 4 is its operating timing. FIG. In the figure, 1 to 3 are first to third ECL differential pairs, 7 to 9 are voltage drop resistors, and Q ₁ to Q ₆ are first to sixth transistors. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims for Utility Model Registration] Consisting of first and second transistors whose common emitters are connected to the low potential side and whose respective collectors are connected to the high potential side, a first input is connected to the base of the first transistor. The first E for input is given
It consists of a CL differential pair, and third and fourth transistors whose common emitters are connected to the low potential side and whose respective collectors are connected to the high potential side, and a second input is applied to the base of the third transistor. the second E for input,
It consists of a CL differential pair, and fifth and sixth transistors whose common emitters are connected to the low potential side and whose respective collectors are connected to the high potential side through a resistor and further through a common resistor. The bases of the fifth and sixth transistors are connected to the common emitters of the first and second ECL differential pairs, respectively, and the collectors of the fifth and sixth transistors are connected to the common emitters of the fourth and second transistors, respectively. A flip-flop circuit comprising a third ECL differential pair for output connected to a base.