JPS621429U - - Google Patents

Info

Publication number
JPS621429U
JPS621429U JP9191885U JP9191885U JPS621429U JP S621429 U JPS621429 U JP S621429U JP 9191885 U JP9191885 U JP 9191885U JP 9191885 U JP9191885 U JP 9191885U JP S621429 U JPS621429 U JP S621429U
Authority
JP
Japan
Prior art keywords
circuit
logic gate
time constant
output
constant circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9191885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9191885U priority Critical patent/JPS621429U/ja
Publication of JPS621429U publication Critical patent/JPS621429U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の基本構成を示す回路図、第2
図は本考案の第1の実施例の回路図、第3図は第
2実施例の回路図、第4図は第3実施例の回路図
、第5図は第4実施例の回路図第6図はIC論理
ゲートの出力特性を温度をパラメータとして示し
たグラフ、第7図は従来の発振回路の構成を示す
回路図である。
Figure 1 is a circuit diagram showing the basic configuration of the present invention, Figure 2 is a circuit diagram showing the basic configuration of the present invention.
The figure is a circuit diagram of the first embodiment of the present invention, FIG. 3 is a circuit diagram of the second embodiment, FIG. 4 is a circuit diagram of the third embodiment, and FIG. 5 is a circuit diagram of the fourth embodiment. FIG. 6 is a graph showing the output characteristics of an IC logic gate using temperature as a parameter, and FIG. 7 is a circuit diagram showing the configuration of a conventional oscillation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] IC論理ゲート出力端子と発振周波数を決める
時定数回路との間に高入力インピーダンス、低出
力インピーダンス素子又は回路を挿入、IC論理
ゲートの出力を上記時定数回路を介して入力側に
フイードバツクしてなる発振回路。
A high input impedance, low output impedance element or circuit is inserted between the IC logic gate output terminal and a time constant circuit that determines the oscillation frequency, and the output of the IC logic gate is fed back to the input side via the above time constant circuit. Oscillation circuit.
JP9191885U 1985-06-17 1985-06-17 Pending JPS621429U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9191885U JPS621429U (en) 1985-06-17 1985-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9191885U JPS621429U (en) 1985-06-17 1985-06-17

Publications (1)

Publication Number Publication Date
JPS621429U true JPS621429U (en) 1987-01-07

Family

ID=30648239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9191885U Pending JPS621429U (en) 1985-06-17 1985-06-17

Country Status (1)

Country Link
JP (1) JPS621429U (en)

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