JPS628715U - - Google Patents

Info

Publication number
JPS628715U
JPS628715U JP9941185U JP9941185U JPS628715U JP S628715 U JPS628715 U JP S628715U JP 9941185 U JP9941185 U JP 9941185U JP 9941185 U JP9941185 U JP 9941185U JP S628715 U JPS628715 U JP S628715U
Authority
JP
Japan
Prior art keywords
inverter
external terminal
signal
circuit
switch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9941185U
Other languages
Japanese (ja)
Other versions
JPH0435939Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985099411U priority Critical patent/JPH0435939Y2/ja
Publication of JPS628715U publication Critical patent/JPS628715U/ja
Application granted granted Critical
Publication of JPH0435939Y2 publication Critical patent/JPH0435939Y2/ja
Expired legal-status Critical Current

Links

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  • Oscillators With Electromechanical Resonators (AREA)
  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図のスイツチ回路の構成例を示す
図、第３図は従来の回路を示すブロツク図である
。 １はインバータ、２は第１の外部端子、３は第
２の外部端子、４は第１のスイツチ回路、５は第
２のスイツチ回路、６は第２の信号の接続される
端子である。尚、各図中同一符号は同一又は相当
部分を示す。 FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an example of the configuration of the switch circuit shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional circuit. 1 is an inverter, 2 is a first external terminal, 3 is a second external terminal, 4 is a first switch circuit, 5 is a second switch circuit, and 6 is a terminal to which a second signal is connected. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】 インバータと、このインバータの入力端子が接
続される第１の外部端子と、上記インバータの出
力端子が接続される第２の外部端子とを備え、こ
の第２の外部端子と上記第１の外部端子との間に
フイードバツク回路を外部接続したとき上記イン
バータは発振回路を構成し、上記第１の外部端子
と上記第２の外部端子との間の外部接続をしや断
し、上記第１の外部端子から第１の信号を入力し
たとき上記インバータは信号増幅回路として動作
する半導体電子回路において、 上記インバータの出力端子と上記第２の外部端
子との間に第１のスイツチ回路を挿入し、この半
導体電子回路内の第２の信号を第２のスイツチ回
路を介して上記第２の外部端子に接続し、 上記第１のスイツチ回路をオン状態に、上記第
２のスイツチ回路をオフ状態に制御して上記発振
回路の構成を可能にし、上記第１のスイツチ回路
をオフ状態に、上記第２のスイツチ回路をオン状
態に制御して上記第１の信号を上記インバータに
入力し、かつ上記第２の信号を上記第２の外部端
子に出力することを可能にすることを特徴とする
半導体電子回路。[Claims for Utility Model Registration] An inverter, a first external terminal to which an input terminal of the inverter is connected, and a second external terminal to which an output terminal of the inverter is connected; When a feedback circuit is externally connected between the terminal and the first external terminal, the inverter constitutes an oscillation circuit, and the inverter configures an oscillation circuit, and the inverter does not connect externally between the first external terminal and the second external terminal. In a semiconductor electronic circuit in which the inverter operates as a signal amplification circuit when a first signal is input from the first external terminal, a first signal is connected between the output terminal of the inverter and the second external terminal. a switch circuit is inserted, a second signal in the semiconductor electronic circuit is connected to the second external terminal via the second switch circuit, the first switch circuit is turned on, and the second signal is connected to the second external terminal through the second switch circuit. The first switch circuit is controlled to be in the OFF state to enable the configuration of the oscillation circuit, and the first switch circuit is controlled to be in the OFF state, and the second switch circuit is controlled to be in the ON state to cause the first signal to be in the above-mentioned state. A semiconductor electronic circuit that is capable of inputting the second signal to an inverter and outputting the second signal to the second external terminal.
JP1985099411U 1985-06-28 1985-06-28 Expired JPH0435939Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985099411U JPH0435939Y2 (en) 1985-06-28 1985-06-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985099411U JPH0435939Y2 (en) 1985-06-28 1985-06-28

Publications (2)

Publication Number Publication Date
JPS628715U true JPS628715U (en) 1987-01-20
JPH0435939Y2 JPH0435939Y2 (en) 1992-08-25

Family

ID=30968264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985099411U Expired JPH0435939Y2 (en) 1985-06-28 1985-06-28

Country Status (1)

Country Link
JP (1) JPH0435939Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6363204A (en) * 1986-09-03 1988-03-19 Nec Corp Integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155774A (en) * 1984-08-27 1986-03-20 Seiko Epson Corp 1 chip microcomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155774A (en) * 1984-08-27 1986-03-20 Seiko Epson Corp 1 chip microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6363204A (en) * 1986-09-03 1988-03-19 Nec Corp Integrated circuit device

Also Published As

Publication number Publication date
JPH0435939Y2 (en) 1992-08-25

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