JPS6082276U - Phase sequence detection device - Google Patents

Phase sequence detection device

Info

Publication number
JPS6082276U
JPS6082276U JP17366783U JP17366783U JPS6082276U JP S6082276 U JPS6082276 U JP S6082276U JP 17366783 U JP17366783 U JP 17366783U JP 17366783 U JP17366783 U JP 17366783U JP S6082276 U JPS6082276 U JP S6082276U
Authority
JP
Japan
Prior art keywords
sequence detection
phase sequence
phase
gate
detection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17366783U
Other languages
Japanese (ja)
Other versions
JPS6326778Y2 (en
Inventor
山内 聡見
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP17366783U priority Critical patent/JPS6082276U/en
Publication of JPS6082276U publication Critical patent/JPS6082276U/en
Application granted granted Critical
Publication of JPS6326778Y2 publication Critical patent/JPS6326778Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の相順検出回路を示す回路図、第2図は三
相交流波形図、第3図は1正相ヨの場合の相順検出信号
波形図、第4図は1反相ヨの場合の相順検出信号波形図
、第5図はこの考案の一実施例を示す回路図、第6図は
この考案にがかる1正相ヨと1反相ヨの場合の相順検出
信号波形図である。 図において、φ1.φ2.φ3は三相交流、1は三相交
流電源、2は負荷、3は電源線、5は光結合素子、10
はDフリップフロップ、12は相順検出出力、20はエ
クスクル−シブ・オアゲート、22はスイッチである。 なお、図中同一符号は同一または相当部分を示す。 十−1−一一一 丁[
Figure 1 is a circuit diagram showing a conventional phase sequence detection circuit, Figure 2 is a three-phase AC waveform diagram, Figure 3 is a phase sequence detection signal waveform diagram for 1 positive phase, and Figure 4 is 1 negative phase. Fig. 5 is a circuit diagram showing an embodiment of this invention, and Fig. 6 is a phase sequence detection signal waveform diagram in the case of 1 positive phase and 1 reverse phase y according to this invention. FIG. In the figure, φ1. φ2. φ3 is three-phase AC, 1 is three-phase AC power supply, 2 is load, 3 is power line, 5 is optical coupling element, 10
1 is a D flip-flop, 12 is a phase sequence detection output, 20 is an exclusive OR gate, and 22 is a switch. Note that the same reference numerals in the figures indicate the same or corresponding parts. 10-1-111 [

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)三相交流を印加した電源線に接続された複数の光
結合素子により相順検出信号を取り出し、これらの信号
の位相をフリップフロップにより比較することによって
相順検出を行なうようにしたものにおいて、上記光結合
素子の出力側にスイッチによって上記フリップフロップ
の出力の論理レベルを選択的に反転させる操作回路を接
続し、このスイッチに操作により1正相ヨとなる相順を
逆に設定し得るようにしたことを特徴とする相順検出装
置。
(1) Phase sequence detection is performed by extracting phase sequence detection signals using multiple optical coupling elements connected to a power line to which three-phase alternating current is applied, and comparing the phases of these signals using a flip-flop. In this case, an operating circuit for selectively inverting the logic level of the output of the flip-flop is connected to the output side of the optical coupling element using a switch, and the phase order of 1 positive phase is set to be reversed by operating the switch. A phase sequence detection device characterized in that it obtains the following:
(2)操作回路がエクスクル−シブオアゲートを含み、
このオアゲートの一方の入力端に前記複数の光結合素子
のうちのひとつの出力が接続され、上記オアゲートの他
方の入力端に前記スイッチにより“L”“H”ふた2の
論理レベルが選択的に切換えられて与えられ、上記オア
ゲートの出力端が前記フリップフロップの入力端子に接
続されていることを特徴とする実用新案登録請求の範囲
第1項に記載の相順検出装置。
(2) the operation circuit includes an exclusive or gate;
The output of one of the plurality of optical coupling elements is connected to one input terminal of the OR gate, and the logic level of the lid 2 is selectively set to "L" or "H" by the switch to the other input terminal of the OR gate. 2. The phase sequence detection device according to claim 1, wherein the output terminal of the OR gate is connected to the input terminal of the flip-flop.
JP17366783U 1983-11-11 1983-11-11 Phase sequence detection device Granted JPS6082276U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17366783U JPS6082276U (en) 1983-11-11 1983-11-11 Phase sequence detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17366783U JPS6082276U (en) 1983-11-11 1983-11-11 Phase sequence detection device

Publications (2)

Publication Number Publication Date
JPS6082276U true JPS6082276U (en) 1985-06-07
JPS6326778Y2 JPS6326778Y2 (en) 1988-07-20

Family

ID=30378269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17366783U Granted JPS6082276U (en) 1983-11-11 1983-11-11 Phase sequence detection device

Country Status (1)

Country Link
JP (1) JPS6082276U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8882018B2 (en) 2011-12-19 2014-11-11 Sidergas Spa Retainer for welding wire container and welding wire container with retainer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5597576U (en) * 1978-12-27 1980-07-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5597576U (en) * 1978-12-27 1980-07-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8882018B2 (en) 2011-12-19 2014-11-11 Sidergas Spa Retainer for welding wire container and welding wire container with retainer

Also Published As

Publication number Publication date
JPS6326778Y2 (en) 1988-07-20

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