JPS59130131U - Microcomputer reset circuit - Google Patents

Microcomputer reset circuit

Info

Publication number
JPS59130131U
JPS59130131U JP2194283U JP2194283U JPS59130131U JP S59130131 U JPS59130131 U JP S59130131U JP 2194283 U JP2194283 U JP 2194283U JP 2194283 U JP2194283 U JP 2194283U JP S59130131 U JPS59130131 U JP S59130131U
Authority
JP
Japan
Prior art keywords
voltage
microcomputer
reset circuit
power supply
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2194283U
Other languages
Japanese (ja)
Inventor
端山 朗
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP2194283U priority Critical patent/JPS59130131U/en
Publication of JPS59130131U publication Critical patent/JPS59130131U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はリセット回路の従来例を示す回路図、第2図及
び第3図は第1図の回路の動作を示す波形図、第4図は
本考案の実施例を示す回路図、第5図は第4図の回路の
動作を示す波形図である。 主要部分の符号の説明、1・・・マイクロコンピュータ
、4・・・リセット回路、11・・・第1信号発生回路
、12・・・第2信号発生回路。
FIG. 1 is a circuit diagram showing a conventional example of a reset circuit, FIGS. 2 and 3 are waveform diagrams showing the operation of the circuit in FIG. 1, FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. The figure is a waveform diagram showing the operation of the circuit of FIG. 4. Explanation of symbols of main parts: 1...microcomputer, 4...reset circuit, 11...first signal generation circuit, 12...second signal generation circuit.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)  マイクロコンピュータを初期状態にすべくリ
セット信号を発生するリセット回路であって、前記マイ
クロコンピュータへの電源電圧の電圧上昇に応じて前記
リセット信号を発生する第1信号発生回路と、前記電源
電圧が所定電圧以下にあるときに前記リセット信号を発
生する第2信号発生回路とを有することを特徴とするリ
セット回路。
(1) A reset circuit that generates a reset signal to bring the microcomputer into an initial state, the first signal generating circuit generating the reset signal in response to an increase in the power supply voltage to the microcomputer; and the power supply. and a second signal generation circuit that generates the reset signal when the voltage is below a predetermined voltage.
(2)前記所定電圧は前記電源電圧の設定電圧より低く
かつ前記マイクロコンピュータの最低動作電圧より高い
電圧であることを特徴とする実用新案登録請求の範囲第
1項記載のリセット回路。
(2) The reset circuit according to claim 1, wherein the predetermined voltage is lower than the set voltage of the power supply voltage and higher than the minimum operating voltage of the microcomputer.
JP2194283U 1983-02-17 1983-02-17 Microcomputer reset circuit Pending JPS59130131U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2194283U JPS59130131U (en) 1983-02-17 1983-02-17 Microcomputer reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2194283U JPS59130131U (en) 1983-02-17 1983-02-17 Microcomputer reset circuit

Publications (1)

Publication Number Publication Date
JPS59130131U true JPS59130131U (en) 1984-09-01

Family

ID=30153063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2194283U Pending JPS59130131U (en) 1983-02-17 1983-02-17 Microcomputer reset circuit

Country Status (1)

Country Link
JP (1) JPS59130131U (en)

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