JPS60129722U

JPS60129722U - signal generation circuit

Info

Publication number: JPS60129722U
Application number: JP1731284U
Authority: JP
Inventors: 平野　良文
Original assignee: 日本電気アイシ−マイコンシステム株式会社
Priority date: 1984-02-09
Filing date: 1984-02-09
Publication date: 1985-08-30

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図ａは、従来の信号発生面路の一例を示すブロック
図であり、第１図すは、第１図ａを正常に操作させた時
のタイミング図であり、第１図Ｃは、第１図ａを誤まっ
て操作させたときのタイミング図である。第２図ａは、
本考案の信号発生回路の一実施例を示すブロック図であ
り、第２図すは、第２図ａのタイミング図である。なお
、第１　　。図す、　ｃ、第２図すの信号波形は、電圧波形で描１１
．１３，２１・・・・・・スイッチ、１２・・・・・・
フリップ・フロップ、１４・・・・・・電源、２２，２
３・・・・・・遅延回路。FIG. 1A is a block diagram showing an example of a conventional signal generation surface path, FIG. 1S is a timing diagram when FIG. 1A is operated normally, and FIG. FIG. 2 is a timing chart when the operation shown in FIG. 1a is performed by mistake. Figure 2 a is
FIG. 2 is a block diagram showing an embodiment of the signal generating circuit of the present invention, and FIG. 2 is a timing diagram of FIG. 2a. In addition, the first. The signal waveforms in Figure c and Figure 2 are depicted as voltage waveforms.
．． 13, 21...Switch, 12...
Flip-flop, 14...Power supply, 22,2
3...Delay circuit.

Claims

[Scope of utility model registration request]

a flip-flop circuit whose input signal is a voltage generated by an interlocking mechanical switch; and a first flip-flop circuit connected between a common terminal of a first mechanical switch in the interlocking mechanical switches and a reset terminal of the flip-flop circuit. and a signal inserted between a common terminal of a second mechanical switch in the interlocking mechanical switch and a clock terminal of the flip-flop circuit and having a longer signal delay time than the first signal delay circuit. and a second signal delay circuit having a delay time.