JPS58190703U - control system - Google Patents

control system

Info

Publication number
JPS58190703U
JPS58190703U JP8822082U JP8822082U JPS58190703U JP S58190703 U JPS58190703 U JP S58190703U JP 8822082 U JP8822082 U JP 8822082U JP 8822082 U JP8822082 U JP 8822082U JP S58190703 U JPS58190703 U JP S58190703U
Authority
JP
Japan
Prior art keywords
reset signal
control system
time
level
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8822082U
Other languages
Japanese (ja)
Inventor
勉 杉田
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP8822082U priority Critical patent/JPS58190703U/en
Publication of JPS58190703U publication Critical patent/JPS58190703U/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のシステム構成を示すブロック図、第１Ａ
図は第１図におけるリセット信号発生部の詳細を示す回
路図、第１Ｂ図は第１図の動作を説明するためのタイム
チャート、第２図はこの考案の実施例を示す全体構成図
、第２Ａ図は第２図における時間監視部を詳細に示す回
路図、第２Ｂ図は第２図の動作を説明するためのタイム
チャートである。 符号説明、１・・・・・・リセット信号発生部、２・・
・・・・マイクロプロセッサ、３・・・・・・メモリ、
４・・・・・・出力部、５・・・・・・データバス、６
＝−・・・・時間監視部、ＩＣ・・・・・・インバータ
、ＴＲ・・・・・・トランジスタ、ｚＤ・・・・・・ツ
ェナーダイオード、Ｒ□〜Ｒ５・・・・・・抵抗、ＡＤ
Ｃ・・・・・・アナログ／ディジタル変換器、ＣＡ・・
・・・・コンデ　　　　・ンサ、Ｔ・・・・・・端子。Figure 1 is a block diagram showing the conventional system configuration, Figure 1A
1B is a time chart for explaining the operation of FIG. 1. FIG. 2 is an overall configuration diagram showing an embodiment of this invention. 2A is a circuit diagram showing the time monitoring section in FIG. 2 in detail, and FIG. 2B is a time chart for explaining the operation of FIG. 2. Explanation of symbols, 1...Reset signal generation section, 2...
...Microprocessor, 3...Memory,
4...Output section, 5...Data bus, 6
=-...Time monitoring unit, IC...Inverter, TR...Transistor, zD...Zener diode, R□~R5...Resistance, A.D.
C...Analog/digital converter, CA...
...Capacitor, T...Terminal.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）電源電圧を監視し該電圧レベルが所定値以下に低
下したときリセット信号を発生するとともに該レベルが
所定値以上に回復したときリセット信号を解除するリセ
ット信号発生手段と、各種装置等の制御を行ない該リセ
ット信号を受信したときその制御動作を停止しリセット
信号を解除するとともに各種装置等に所定の信号を与え
てイニシャルスタートを行なう制御手段とを有してなる
制御システムにおいて、前記電圧が所定レベル以下に下
がった時点から該所定レベルに回復する迄の時間を計測
する計測手段を設け、該手段にて計測される時間に応じ
てイニシャルスタートの条件を変えるようにしたことを
特徴とする制御システム。(1) Reset signal generating means that monitors the power supply voltage, generates a reset signal when the voltage level falls below a predetermined value, and cancels the reset signal when the level recovers to a predetermined value or higher, and various devices, etc. In the control system, the control system comprises a control means that performs control and when the reset signal is received, stops the control operation, cancels the reset signal, and gives predetermined signals to various devices etc. to perform an initial start. A measuring means is provided for measuring the time from the time when the level drops below a predetermined level until it recovers to the predetermined level, and the initial start conditions are changed according to the time measured by the means. control system. （２）実用新案登録請求の範囲第１項に記載の制御シス
テムにおいて、前記時間計測手段はコンデンサと抵抗と
から構成されてなることを特徴とする制御システム。(2) Utility Model Registration The control system according to claim 1, wherein the time measuring means comprises a capacitor and a resistor.
JP8822082U 1982-06-15 1982-06-15 control system Pending JPS58190703U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8822082U JPS58190703U (en) 1982-06-15 1982-06-15 control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8822082U JPS58190703U (en) 1982-06-15 1982-06-15 control system

Publications (1)

Publication Number Publication Date
JPS58190703U true JPS58190703U (en) 1983-12-19

Family

ID=30096905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8822082U Pending JPS58190703U (en) 1982-06-15 1982-06-15 control system

Country Status (1)

Country Link
JP (1) JPS58190703U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015162169A (en) * 2014-02-28 2015-09-07 京セラドキュメントソリューションズ株式会社 Storage device, image forming apparatus, method of detecting abnormality caused by instantaneous interruption of hard disk, and method of recovering abnormality caused by instantaneous interruption of hard disk

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261688A (en) * 1975-11-17 1977-05-21 Toshiba Corp Process control device
JPS5479376A (en) * 1977-12-05 1979-06-25 Matsushita Electric Ind Co Ltd Controller of apparatus for house

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261688A (en) * 1975-11-17 1977-05-21 Toshiba Corp Process control device
JPS5479376A (en) * 1977-12-05 1979-06-25 Matsushita Electric Ind Co Ltd Controller of apparatus for house

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015162169A (en) * 2014-02-28 2015-09-07 京セラドキュメントソリューションズ株式会社 Storage device, image forming apparatus, method of detecting abnormality caused by instantaneous interruption of hard disk, and method of recovering abnormality caused by instantaneous interruption of hard disk

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