JPS5933543U - Reset device - Google Patents
Reset deviceInfo
- Publication number
- JPS5933543U JPS5933543U JP12663182U JP12663182U JPS5933543U JP S5933543 U JPS5933543 U JP S5933543U JP 12663182 U JP12663182 U JP 12663182U JP 12663182 U JP12663182 U JP 12663182U JP S5933543 U JPS5933543 U JP S5933543U
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- transistors
- reset device
- divider circuit
- resistor divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のリセット装置の一実施例を示す構成図
、第２図は接続点１０の電源投入時の電圧変化を示す波
形図、第３図はリセット端子１１のリセット時間を示す
波形図、第４図はリセット端子１２のリセット時間を示
す波形図である。
２・・・時定数設定用積分回路のコンデンサ、３゜４、
６． ７・・・リセット時間設定用抵抗、５．８・・
・ＮＰＮ）ランジスタ。FIG. 1 is a configuration diagram showing an embodiment of the reset device of the present invention, FIG. 2 is a waveform diagram showing the voltage change at the connection point 10 when the power is turned on, and FIG. 3 is a waveform showing the reset time of the reset terminal 11. 4 are waveform diagrams showing the reset time of the reset terminal 12. 2...Capacitor of integration circuit for time constant setting, 3゜4,
6. 7...Reset time setting resistor, 5.8...
・NPN) transistor.
Claims (1)
ンデンサの他端に接続された抵抗分割回路と、この抵抗
分割回路からの複数出力をそれぞれ制御入力とする複数
のトランジスタを備え、これら複数のトランジスタを備
え、これら複数のトランジスタの出力を、相互に関係す
る複数のマイクロコンピュータのそれぞれのりセット端
子に入力し、電源投入後各トランジスタによるリセット
解除の出力を時間的に異ならせて発生させるように構成
したことを特徴とするリセット装置。It is equipped with an integrating capacitor whose one end is connected to the power supply, a resistor divider circuit connected to the other end of this capacitor, and a plurality of transistors whose control inputs are the plurality of outputs from the resistor divider circuit. It is equipped with transistors, and the outputs of these plurality of transistors are inputted to the respective glue set terminals of a plurality of microcomputers related to each other, and after the power is turned on, the reset release outputs of each transistor are generated at different times. A reset device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12663182U JPS5933543U (en) | 1982-08-20 | 1982-08-20 | Reset device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12663182U JPS5933543U (en) | 1982-08-20 | 1982-08-20 | Reset device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5933543U true JPS5933543U (en) | 1984-03-01 |
Family
ID=30287878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12663182U Pending JPS5933543U (en) | 1982-08-20 | 1982-08-20 | Reset device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933543U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03161206A (en) * | 1989-11-20 | 1991-07-11 | Chiyoda Corp | Inner burr cutting device for friction welding and cutting blade attaching device |
-
1982
- 1982-08-20 JP JP12663182U patent/JPS5933543U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03161206A (en) * | 1989-11-20 | 1991-07-11 | Chiyoda Corp | Inner burr cutting device for friction welding and cutting blade attaching device |
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