JPS6072039U - reset circuit - Google Patents
reset circuitInfo
- Publication number
- JPS6072039U JPS6072039U JP16214183U JP16214183U JPS6072039U JP S6072039 U JPS6072039 U JP S6072039U JP 16214183 U JP16214183 U JP 16214183U JP 16214183 U JP16214183 U JP 16214183U JP S6072039 U JPS6072039 U JP S6072039U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- zener diode
- reset circuit
- transistor
- sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例を示す回路図、第２図は第１図
に示された回路の動作を示す特性図である。
１・・・マイクロコンピュータ、２，３．４・・・抵抗
、５・・・ツェナーダイオード、６・・・トランジスタ
。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a characteristic diagram showing the operation of the circuit shown in FIG. 1... Microcomputer, 2, 3.4... Resistor, 5... Zener diode, 6... Transistor.
Claims (1)
電子回路にリセット信号を印加するリセット回路に於い
て、電源電圧と接地間に抵抗を介して接続されたツェナ
ーダイオードと、該ツェナーダイオードの端子電圧がベ
ースに印加されたトランジスタとを備え、該トランジス
タの立ち上がり電圧と前記ツェナーダイオードの端子電
圧との和が前記電子回路の最低動作電圧より高くなるよ
うに前記ツェナーダイオードのツェナー電圧を選択し、
電源電圧が前記最低動作電圧から前記和の電圧になる期
間に、前記トランジスタによってリセット信号が出力さ
れることを特徴とするリセット回路。In a reset circuit that applies a reset signal to an electronic circuit such as a microcomputer when the power is turned on or momentarily interrupted, a Zener diode is connected between the power supply voltage and ground via a resistor, and the terminal voltage of the Zener diode is a transistor applied to the base thereof, the Zener voltage of the Zener diode is selected such that the sum of the rising voltage of the transistor and the terminal voltage of the Zener diode is higher than the lowest operating voltage of the electronic circuit;
A reset circuit characterized in that a reset signal is outputted by the transistor during a period in which a power supply voltage reaches the sum voltage from the minimum operating voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16214183U JPS6072039U (en) | 1983-10-19 | 1983-10-19 | reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16214183U JPS6072039U (en) | 1983-10-19 | 1983-10-19 | reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6072039U true JPS6072039U (en) | 1985-05-21 |
Family
ID=30356139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16214183U Pending JPS6072039U (en) | 1983-10-19 | 1983-10-19 | reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6072039U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0299420U (en) * | 1989-01-26 | 1990-08-08 |
-
1983
- 1983-10-19 JP JP16214183U patent/JPS6072039U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0299420U (en) * | 1989-01-26 | 1990-08-08 |
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