JPH0299420U - - Google Patents

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Publication number
JPH0299420U
JPH0299420U JP810189U JP810189U JPH0299420U JP H0299420 U JPH0299420 U JP H0299420U JP 810189 U JP810189 U JP 810189U JP 810189 U JP810189 U JP 810189U JP H0299420 U JPH0299420 U JP H0299420U
Authority
JP
Japan
Prior art keywords
cpu
power supply
reference value
supply line
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP810189U
Other languages
Japanese (ja)
Other versions
JP2587705Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989008101U priority Critical patent/JP2587705Y2/en
Publication of JPH0299420U publication Critical patent/JPH0299420U/ja
Application granted granted Critical
Publication of JP2587705Y2 publication Critical patent/JP2587705Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は請求項1に記載の本考案の実施例の回
路図、第2図は請求項2に記載の本考案の実施例
の構成を示すブロツク図、第3図および第4図は
従来のCPUリセツト回路の回路図である。 符号の説明、1……CPU、2……CPUリセ
ツト回路、3……検知回路、4……負荷制御回路
、Q1……第1のトランジスタ、Q2……第2の
トランジスタ、RST……リセツト端子、VDD
……第1の電源ライン、VCC……第2の電源ラ
イン、V1……第1の基準値、V2……第2の基
準値、ZD1……第1のツエナーダイオード、Z
D2……第2のツエナーダイオード。
FIG. 1 is a circuit diagram of an embodiment of the present invention according to claim 1, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention according to claim 2, and FIGS. 3 and 4 are conventional circuit diagrams. FIG. 2 is a circuit diagram of the CPU reset circuit of FIG. Explanation of symbols, 1... CPU, 2... CPU reset circuit, 3... detection circuit, 4... load control circuit, Q1... first transistor, Q2... second transistor, RST... reset terminal , VDD
...First power line, VCC...Second power line, V1...First reference value, V2...Second reference value, ZD1...First Zener diode, Z
D2...Second Zener diode.

Claims (1)

【実用新案登録請求の範囲】 (1) エミツタを接地した第1のトランジスタの
ベースと第1の電源ラインとの間に、ツエナー電
圧を第1の基準値に規定された第1のツエナーダ
イオードをそのカソード側が上記第1の電源ライ
ン側になるように接続し、 エミツタをCPUの供給電源である第2の電源
ラインに接続し、コレクタを抵抗を介して接地し
た第2のトランジスタのベースと、上記第1のト
ランジスタのコレクタとの間に、抵抗とツエナー
電圧を第2の基準値に規定された第2のツエナー
ダイオードとを直列接続したものを、該第2のツ
エナーダイオードのアノード側が上記第1のトラ
ンジスタのコレクタ側になるように接続し、 上記第2のトランジスタのコレクタを上記CP
Uのリセツト端子に接続して構成されたCPUリ
セツト回路であつて、 上記第1の電源ラインおよび上記第2の電源ラ
インの電圧レベルが、各々上記第1の基準値およ
び第2の基準値を越えている期間は、上記CPU
のリセツト端子に信号電圧を出力して、該CPU
ではリセツトを行なつた後に必要な信号処理を行
なう一方、 上記第1の電源ラインの電圧レベルが上記第1
の基準値よりも低下した場合、または上記第2の
電源ラインの電圧レベルが上記第2の基準値より
も低下した場合には、上記CPUのリセツト端子
への信号電圧の出力を停止して、該CPUでは信
号処理動作を停止する構成にしたことを特徴とす
る、CPUリセツト回路。 (2) 人体より放射される熱線を検知する焦電素
子を有した検知回路と、上記検知回路の信号を処
理するリセツト端子を有したCPUと、該CPU
の信号を受けて必要な制御動作を行なう負荷制御
回路と、上記検知回路及び負荷制御回路に電源を
供給する第1の電源ラインと、上記CPUに電源
を供給する第2の電源ラインと、第1および第2
の基準値を有し、上記第1の電源ラインおよび上
記第2の電源ラインの電圧レベルが、各々上記第
1の基準値および第2の基準値を越えている期間
は、上記CPUのリセツト端子に信号電圧を出力
して、該CPUではリセツトを行なつた後に上記
検知回路の信号を信号処理して、上記負荷制御回
路を制御して必要な制御を行なう一方、上記第1
の電源ラインの電圧レベルが上記第1の基準値よ
りも低下した場合、または上記第2の電源ライン
の電圧レベルが上記第2の基準値よりも低下した
場合には、上記CPUのリセツト端子への信号電
圧の出力を停止して、該CPUの信号処理動作を
停止するCPUリセツト回路とを備えたことを特
徴とする、熱線式検知器。
[Claims for Utility Model Registration] (1) A first Zener diode whose Zener voltage is set to a first reference value is connected between the base of the first transistor whose emitter is grounded and the first power supply line. a base of a second transistor whose cathode side is connected to the first power supply line side, whose emitter is connected to a second power supply line that is the power supply of the CPU, and whose collector is grounded via a resistor; A resistor and a second Zener diode whose Zener voltage is defined as a second reference value are connected in series between the collector of the first transistor, and the anode side of the second Zener diode is connected to the collector of the first transistor. The collector of the second transistor is connected to the collector side of the first transistor, and the collector of the second transistor is connected to the collector of the second transistor.
A CPU reset circuit configured to be connected to a reset terminal of U, wherein the voltage levels of the first power line and the second power line exceed the first reference value and the second reference value, respectively. If the period exceeds the above CPU
Outputs a signal voltage to the reset terminal of the CPU.
Then, after performing the reset, necessary signal processing is performed, while the voltage level of the first power supply line is
or when the voltage level of the second power supply line falls below the second reference value, stop outputting the signal voltage to the reset terminal of the CPU, A CPU reset circuit, characterized in that the CPU is configured to stop signal processing operations. (2) a detection circuit having a pyroelectric element that detects heat rays emitted from the human body; a CPU having a reset terminal that processes signals from the detection circuit;
a load control circuit that performs necessary control operations upon receiving the signal; a first power line that supplies power to the detection circuit and the load control circuit; a second power line that supplies power to the CPU; 1st and 2nd
, and during a period in which the voltage levels of the first power supply line and the second power supply line exceed the first reference value and the second reference value, respectively, the reset terminal of the CPU is After performing a reset, the CPU processes the signal from the detection circuit to control the load control circuit to perform necessary control.
If the voltage level of the power supply line falls below the first reference value, or if the voltage level of the second power supply line falls below the second reference value, a signal is sent to the reset terminal of the CPU. 1. A hot wire type detector, comprising: a CPU reset circuit that stops the signal voltage output of the CPU and stops the signal processing operation of the CPU.
JP1989008101U 1989-01-26 1989-01-26 CPU reset circuit and hot-wire detector using the same Expired - Lifetime JP2587705Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989008101U JP2587705Y2 (en) 1989-01-26 1989-01-26 CPU reset circuit and hot-wire detector using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989008101U JP2587705Y2 (en) 1989-01-26 1989-01-26 CPU reset circuit and hot-wire detector using the same

Publications (2)

Publication Number Publication Date
JPH0299420U true JPH0299420U (en) 1990-08-08
JP2587705Y2 JP2587705Y2 (en) 1998-12-24

Family

ID=31213679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989008101U Expired - Lifetime JP2587705Y2 (en) 1989-01-26 1989-01-26 CPU reset circuit and hot-wire detector using the same

Country Status (1)

Country Link
JP (1) JP2587705Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231221A (en) * 2011-04-25 2012-11-22 Funai Electric Co Ltd Reset circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638622A (en) * 1979-09-06 1981-04-13 Omron Tateisi Electronics Co Power source control circuit for electronic device
JPS5972503A (en) * 1982-10-19 1984-04-24 Canon Inc Sequence controller
JPS6072039U (en) * 1983-10-19 1985-05-21 三洋電機株式会社 reset circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638622A (en) * 1979-09-06 1981-04-13 Omron Tateisi Electronics Co Power source control circuit for electronic device
JPS5972503A (en) * 1982-10-19 1984-04-24 Canon Inc Sequence controller
JPS6072039U (en) * 1983-10-19 1985-05-21 三洋電機株式会社 reset circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231221A (en) * 2011-04-25 2012-11-22 Funai Electric Co Ltd Reset circuit

Also Published As

Publication number Publication date
JP2587705Y2 (en) 1998-12-24

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EXPY Cancellation because of completion of term