JPS6380651U - - Google Patents

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Publication number
JPS6380651U
JPS6380651U JP17355086U JP17355086U JPS6380651U JP S6380651 U JPS6380651 U JP S6380651U JP 17355086 U JP17355086 U JP 17355086U JP 17355086 U JP17355086 U JP 17355086U JP S6380651 U JPS6380651 U JP S6380651U
Authority
JP
Japan
Prior art keywords
signal line
signal
transmission circuit
input end
buffer gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17355086U
Other languages
Japanese (ja)
Other versions
JPH0454510Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986173550U priority Critical patent/JPH0454510Y2/ja
Publication of JPS6380651U publication Critical patent/JPS6380651U/ja
Application granted granted Critical
Publication of JPH0454510Y2 publication Critical patent/JPH0454510Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の１実施例を示すブロツク図、
第２図は第１図に示す実施例の動作を説明する波
形図、第３図は従来の信号伝送回路の構成を示す
ブロツク図である。 ＣＰＵ…中央信号処理装置、ＲＯＭ…リードオ
ンリーメモリ、ＲＡＭ…ランダムアクセスメモリ
、ＢＵＳ（ｎ）…データバス、ＶＣ…電源電圧、
ＲＮ（ｎ）…プルアツプ抵抗、Ｇ１〜Ｇｎ…バツ
フアゲート。 FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a waveform diagram explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional signal transmission circuit. CPU...central signal processing unit, ROM...read-only memory, RAM...random access memory, BUS(n)...data bus, VC...power supply voltage,
RN(n)...Pull-up resistance, G1 to Gn...Buffer gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] １本の信号線に複数のトライステート素子で構
成された信号源と受信部とが互いに並列に接続さ
れたバス方式の信号伝送回路において、前記信号
線にバツフアゲートの入力端が接続されその出力
端から抵抗を介して前記信号線に再接続されたこ
とを特徴とする信号伝送回路。 In a bus-type signal transmission circuit in which a signal source composed of a plurality of tri-state elements and a receiving section are connected in parallel to one signal line, the input end of a buffer gate is connected to the signal line, and the output end thereof is connected to the input end of a buffer gate. A signal transmission circuit characterized in that the signal line is reconnected to the signal line via a resistor.
JP1986173550U 1986-11-12 1986-11-12 Expired JPH0454510Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986173550U JPH0454510Y2 (en) 1986-11-12 1986-11-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986173550U JPH0454510Y2 (en) 1986-11-12 1986-11-12

Publications (2)

Publication Number Publication Date
JPS6380651U true JPS6380651U (en) 1988-05-27
JPH0454510Y2 JPH0454510Y2 (en) 1992-12-21

Family

ID=31111114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986173550U Expired JPH0454510Y2 (en) 1986-11-12 1986-11-12

Country Status (1)

Country Link
JP (1) JPH0454510Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61334U (en) * 1984-06-05 1986-01-06 株式会社明電舎 Tri-state gate element chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5350138A (en) * 1976-10-18 1978-05-08 Hisamitsu Pharmaceut Co Inc Novel acrylic acid ester derivatives

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61334U (en) * 1984-06-05 1986-01-06 株式会社明電舎 Tri-state gate element chip

Also Published As

Publication number Publication date
JPH0454510Y2 (en) 1992-12-21

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