JPH0440017A - Pll circuit - Google Patents

Abstract

PURPOSE:To improve a C/N and to easily vary a loop gain by converting spark advance and delay signals to analog voltages by a count clock oscillator, D/A converter and up/down counter. CONSTITUTION:According to the spark advance and delay outputs of a digital phase comparator, an up/down counter 4 counts the clocks of a count clock oscillator 3 and the counted data of the up/down counter 4 is converted to the analog voltage by a D/A converter 5. Therefore, since any output is not supplied from the phase comparator when a PLL is locked, the up/down counter 4 counts nothing and the output of the D/A converter 5 is kept constant. Thus, the PLL circuit with satisfactory C/N is realized and the loop gain can be decided by the oscillation frequency of the count clock oscillator 3 and easily varied.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a PLL circuit.

[Summary of the invention]

The present invention converts the output of a digital phase comparator in a PLL@ path into an analog voltage using a count clock oscillator, a D/A converter, and an up/down counter, thereby making it easy to control the loop gain and improve the C/N ratio. good PLL
It realizes the circuit.

[Conventional technology]

Conventionally, converting the output of a digital phase comparator of a PLL circuit into an analog voltage has been performed using an analog circuit including a charge pump and a low-pass filter.

[Problem to be solved by the invention]

However, in the conventional technology, the voltage generated by charging by the charge pump leaks, and voltage fluctuations occur even when the PLL loop is locked, resulting in a poor C/N ratio and the need to switch the characteristics of the low-pass filter. Therefore, there is a drawback that it is difficult to have multiple loop gains within the same PLL loop.

(Means for Solving the Problems) In order to solve the above-mentioned drawbacks, the present invention counts the clock of the count clock oscillator with an up/down counter using the advance and retard outputs of the digital phase comparator, The down counter data is converted to analog voltage using a D/A converter.

[Effect]

By doing the above, when the PLL loop is locked, there is no output from the phase comparator, so the up/down counter does not count, the output of the D/A converter is kept constant, and the C/A converter output is kept constant. A PLL circuit with a good N ratio can be realized,
Furthermore, since the loop gain can be determined by the oscillation frequency of the count clock generator, it can be easily varied.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is an example of a loop filter circuit that implements the present invention. In FIG. 1, retard signal 1. Advance angle signal 2 is P
LL is a phase comparison signal output from the phase comparator of the loop, and is a negative logic signal. Advance angle signal 2. Retard signal 1
is normally at Hi level, and if the VCO output is ahead of the reference, the lead angle signal 2 will be at the LOW level for a time proportional to the advance angle, and the VCO output will be retarded relative to the reference. If so, the retard signal 1 similarly becomes LOW level. When the advance angle signal 2 and the retard angle signal 1 are at Hi level, the count clock control circuit 6 stops the oscillation of the count clock oscillator 3, and the output 9 of the count clock oscillator 3 is fixed at Low level. Down counter 4 does nothing. Therefore, the output voltage 10 of the D/A converter 5 is fixed to a constant voltage. Here, in the case of the side shown in FIG. 1, the up/down counter 4 works as an addition counter when the up/down switching input is HiO, and as a subtraction counter when it is LOW.
It counts at the rising edge of the clock. now,
When the output of vCO is retarded than the reference, the retard signal 1 becomes Low level for a certain period of time due to the retard angle. This retard signal 1 is sent to the up/down counter 4.
The up/down counter 4 functions as a subtraction counter while the retard signal l is at a low level. In addition, the count clock oscillator 3
oscillates while the retard signal 1 is at the LOW level, so while the retard signal 1 is at the LOW level, the up/down counter 4 is subtracted by the output 9 of the count 2012 oscillator 3, and the D/A converter 5's output voltage IO becomes lower,
The output voltage 0 of the D/A converter 5 is connected to a low-pass filter, which removes digital noise from the output voltage 10 of the D/A converter 5, and is offset and inverted to correspond to the operating voltage of vCO. It is amplified and the voltage at the loop filter output 8 increases. Next, when the output of vCO is in advance of the reference, the lead angle signal 2 becomes LOW level for a certain period of time depending on the advance angle. At this time, slow signal 1 is Hi
Since the level remains unchanged, the up/down counter 4 operates as an addition counter, and the count clock oscillator 3 oscillates the advance angle signal 2 during the low level as in the case of retarding operation, so the up/down counter 4 is added and counted. , the output voltage of the D/A converter 5 becomes low. Also, V C
.

When the phase and frequency of ○ and the reference match, the advance and retard operations explained above are not performed, and the voltage of the loop filter output 8 is kept constant, so a PLL circuit with a good C/N ratio can be used. can be realized. As explained above, the first
In the circuit example shown in the figure, the voltage at the output 8 of the loop filter becomes low when vCO is advanced relative to the reference, and increases when it is retarded, depending on the advance or retard angle of the VCO relative to the reference. It works to control the VCO. Furthermore, since the loop gain of the PLL loop can be determined by the frequency input to the clock of the up/down counter 4, the frequency of the count clock oscillator 3 can be varied or the clock of the count clock oscillator 3 can be divided by two. Therefore, by changing the frequency of the 7-nop/down counter 4, it is possible to easily change the frequency.Also, for applications that do not require precision, the count clock oscillator can be realized with an LC oscillator, CR oscillator, etc. It is also possible to create and use any frequency using a microcomputer or the like.

〔Effect of the invention〕

As explained above, according to the present invention, the C/N ratio is good,
A PLL circuit whose loop gain can be easily varied can be realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the PLL circuit of the present invention. Retard) No. 8 advance signal Count clock oscillator Up/down counter D/A converter Count clock control circuit Low pass filter Loop filter output Count clock oscillator output/D/A converter 5 output voltage

Claims (2)

[Claims] (1) In the loop filter connected to the digital phase comparator of the PLL circuit, the advance and retard signals output from the phase comparator are converted into analog A PLL circuit characterized by converting voltage into voltage. (2) In the above PLL circuit, the frequency applied to the up/down counter of the count clock oscillator can be varied to two or more types.
PLL circuit described in section.