JPH05218856A - Digital charge pump type pll circuit - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of the follower clock frequency despite the fault of a reference clock. CONSTITUTION:When a reference clock has a fault, a fault detector 8 detects this fault and at the same time forcibly sets the output value of an up-down counter 5 at the digital value equivalent to the center frequency of a VCO 7. This digital value is converted into the analog voltage value by a D/A converter 6 and inputted to the VCO 7. The output frequency of the VCO 7 is fixed at the center frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase locked loop) circuit, and more particularly to a digital charge pump type P
Regarding the LL circuit.

[0002]

2. Description of the Related Art Conventional digital charge pump type PL
As shown in FIG. 2, the L circuit includes a first frequency divider 1 that divides a reference clock, a second frequency divider 2 and a third frequency divider that divides the output of a VCO (voltage controlled oscillator) 7. 3 and the output of the first frequency divider 1 and the output of the third frequency divider 3 are compared, and when the former is ahead of the latter, a number (+) proportional to the phase difference is added. If a pulse is output and the former is delayed compared to the latter, a number (-) proportional to the phase difference is output.
Phase frequency comparator 4 which outputs a pulse and its (+),
It has a charge pump 8 that integrates the (-) pulse and converts it into a voltage, a loop filter 9 having a high-frequency cutoff characteristic, and a VCO 7 that outputs a frequency corresponding to the input voltage.

Next, the operation will be described. The reference clock is divided into 1 / N ₁ by the first divider 1 and the VCO 7
Is divided into 1 / N ₂ by the second frequency divider 2
The divider 3 is 1 / N _3-divided, respectively, are input to the phase frequency comparator 4. The signals input to the phase frequency comparator 4 are compared in phase, and if there is a phase difference between the two signals, a (+) or (-) pulse is output, and the charge pump 8 and Loop filter 9
, The phase difference is converted into a voltage, and the output frequency of the VCO 7 is controlled by the input voltage of the VCO 7 so as to cancel the difference. As a result, a dependent clock synchronized with the reference clock is obtained.

[0004]

In this conventional digital charge pump type PLL circuit, since the output from the charge pump 5 is cut off when the reference clock fails, the VC
There is a problem that the voltage input to O7 changes and the frequency of the dependent clock changes.

An object of the present invention is to prevent the frequency of the dependent clock from fluctuating even if the reference clock fails.

[0006]

In order to achieve the above object, the present invention provides a VCO for controlling an output frequency according to an input voltage, a reference clock divided by a first divider and an output of the VCO. Is compared with the signal frequency-divided by the second frequency divider and the third frequency divider, and if there is a phase difference between the signals, the number of (+) pulses or (-) proportional to the difference. A phase frequency comparator that outputs the pulse of
Count the number of (+) or (-) pulses,
An up / down counter that outputs the count result as a digital value, a D / A converter that converts the digital value into an analog value, a reference clock failure is detected, and the output of the up / down counter is the center of the VCO when the reference clock failure occurs. And a fault detection circuit for setting a digital value corresponding to the frequency.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a digital charge pump type PLL circuit according to an embodiment of the present invention. In FIG. 1, when the reference clock is operating normally, the reference clock divided by 1 / N ₁ by the first divider 1 and
1 / (N by the second frequency divider 2 and the third frequency divider 3
The output of the VCO 7 divided into ₂ N ₃ ) is input to the phase frequency comparator 4. If there is a phase difference between the signals input to the phase frequency comparator 4, the number of (+) pulses (reference clock is faster than the output of the VCO 7) or (-) pulses (reference) in proportion to the difference. Clock is VCO
7 is slower than the output of 7) is output. The number of (+) or (-) pulses is counted by the up / down counter 5, and the count result becomes a digital value.
The digital value is converted into an analog voltage by the D / A converter 6, and the voltage controls the output frequency of the VCO 7 so as to cancel the phase difference.

When a failure occurs in the reference clock, the failure detector 8 detects the failure and at the same time, the output value of the up / down counter 5 is forcibly set to a digital value corresponding to the center frequency of the VCO 7. Its digital value is
The D / A converter 6 converts the voltage into an analog voltage, the voltage is input to the VCO 7, and the frequency of the output of the VCO 7 is fixed to the center frequency.

[0010]

As described above, according to the present invention, when a failure occurs in the reference clock, the output of the up / down counter by the failure detector is set to a digital value corresponding to the center frequency of the VCO. , The output of the VCO is fixed to the center frequency, and the effect that a dependent clock without frequency fluctuation can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a digital charge pump type PLL circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional digital charge pump type PLL circuit.

[Explanation of symbols]

 1 1st frequency divider 2 2nd frequency divider 3 3rd frequency divider 4 Phase frequency comparator 5 Up-down counter 6 D / A converter 7 VCO

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Mizuno 1-428 Mita, Minato-ku, Tokyo NEC Transmission Engineering Co., Ltd.

Claims (1)

[Claims] 1. A voltage controlled oscillator (hereinafter referred to as "VCO") that controls an output frequency according to an input voltage.
And the reference clock and VC divided by the first divider
The phase of the output of O is compared with the signal obtained by dividing the frequency by the second frequency divider and the third frequency divider, and if there is a phase difference between the signals,
A phase frequency comparator that outputs a number of (+) or (-) pulses proportional to the difference and the number of (+) or (-) pulses are counted, and the count result is converted to a digital value. An up / down counter that outputs, a D / A converter that converts the digital value into an analog value, a reference clock failure, and when a reference clock failure occurs, the up / down counter output is converted to a digital value corresponding to the center frequency of the VCO. A digital charge pump type PLL circuit provided with a fault detection circuit for setting.