JPH0378827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for detecting a single frequency from a plurality of control signals of a facsimile or the like using an analog communication network.

Conventional configuration and its problems Conventionally, a circuit for detecting a single frequency from a plurality of signals has been configured as shown in FIG.
That is, it is composed of a demultiplexer 12, an OR gate 15, and i frequency detection filters 14 corresponding to a plurality of frequencies (in this description, it is assumed to be i) to be detected. By setting, one filter among the i frequency detection filters 14 is selected,
A detection signal inputted from the detection signal input terminal 11 is outputted to the output terminal 16 via a selected filter and an OR gate. As the frequency detection filter 14, an active filter composed of a CR circuit network and an operational amplifier is generally used in order to keep the circuit small and inexpensive.

In this conventional frequency detection circuit, when the number of frequencies to be detected increases, the number of frequency detection filters has to be increased, resulting in an increase in the circuit size and the inconvenience of increasing the price. Ta.

To solve the above problem, 1 as a detection filter
One way to detect multiple single frequencies with a frequency detection circuit consisting only of circuits is to switch the time constant of the CR network. The problem has arisen that it is difficult to obtain highly accurate frequency characteristics because of the need to add this to the CR circuit network, and the current situation is that a sufficient solution to the above-mentioned problem cannot be obtained.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
It is an object of the present invention to provide a variable single frequency circuit that can select and detect a predetermined frequency without reducing frequency detection accuracy.

Structure of the Invention The present invention provides a switched capacitor with a function in which a reference clock pulse is input, the frequency characteristic is proportional to the frequency of this reference clock pulse, and the unnecessary band of the detection signal frequency is removed by selecting this reference clock pulse frequency. A filter (hereinafter abbreviated as SCF) is provided at the front stage and a phase locked loop (hereinafter abbreviated as PLL) is provided at the rear stage to form a frequency detection circuit in which the output of the SCF is detected and displayed. The gist is that the detection frequency is selected by setting a frequency divider in the loop.

As described above, the above-mentioned purpose is achieved by selecting and specifying the frequency division ratio of the SCF or PLL which is composed of a set of circuits and constitutes this circuit to a predetermined value.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a schematic configuration of a single frequency detection circuit according to an embodiment of the present invention, in which 21 is a detection input terminal, 22 is an SCF configured with a low pass or band pass, Frequency characteristics such as a pass band, an attenuation band, and a cutoff frequency are made proportional to the output frequency of the frequency divider 27, and unnecessary band components are removed in advance. 23 is a phase comparator that constitutes the PLL, 24 is a filter for the PLL, 25 is a frequency detection output terminal, 26 is a voltage controlled oscillator for the PLL (hereinafter abbreviated as VCO), 27 is a VCO 26
The output of the frequency divider 27 is input to the phase comparator 23. The output of the frequency divider 27 is input to the phase comparator 23. 28
is a frequency divider, which divides the output frequency of the VCO 26 in order to determine the frequency characteristics of the SCF 22.
The frequency of this divided clock pulse is output to the SCF. 29 is a frequency division ratio setting input terminal for specifying the frequency division ratio of each of the frequency divider 27 and the frequency divider 28. Note that the frequency division ratios M and N of the frequency dividers 27 and 28 may be set to the same value, or may be set by a switch (not shown) so that N>M.

Next, the operation will be explained. SCF22 is VCO26
The clock pulse output frequency is divided by 1/
It exhibits a frequency characteristic determined by the clock pulse frequency divided by N, and removes unnecessary band components from the detection signal input to prevent false detection, and its output serves as the reference input of the phase comparator 23. on the other hand,
The input clock pulse frequency compared by the phase comparator 23 is the clock pulse frequency obtained by dividing the output of the VCO 26 by 1/M by the frequency divider 27. The output based on the phase difference of the frequencies compared by the phase comparator 23 is integrated by the filter 24,
It is applied to the VCO 26 and serves as a control signal input to keep the frequency and/or phase constant. Therefore, when the detected signal output from the SCF 22 and the output signal from the frequency divider 27 match in frequency and phase, a predetermined single frequency is detected at the output terminal.

Effects of the Invention According to the present invention, noise is removed in the SCF, malfunctions in the digital PLL circuit can be prevented, and a single frequency can be reliably detected. Furthermore, components other than the SCF can be digitized, making it easy to convert into an LIS, and when the LIS is implemented, it has the effect of further miniaturization.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional variable single frequency detection circuit, and FIG. 2 is a block diagram of a variable single frequency detection circuit according to an embodiment of the present invention. 22...Switched capacitor filter,
23... Phase comparator, 24... Filter, 26...
...Voltage controlled oscillator, 27, 28... Frequency divider.

Claims (1)

[Claims] 1. A switched capacitor filter that removes unnecessary band frequencies from the input signal to be detected, a first frequency divider that determines the frequency characteristics of the switched capacitor filter, and a single frequency divider that determines the frequency characteristics of the switched capacitor filter. A digital PLL circuit that detects the frequency of
a second frequency divider that divides the clock pulse generated from the voltage controlled oscillator provided in the PLL circuit and sets a detection frequency; the first frequency divider operates the switched capacitor filter using a clock pulse generated from the voltage controlled oscillator as a control input, and the PLL circuit operates the switched capacitor filter using a clock pulse generated from the voltage controlled oscillator as a control input.
A variable single frequency detection circuit, characterized in that a single frequency output is obtained by performing a phase comparison between a capacitor filter output and the second frequency divider output.