JPS5964928A - Oscillating device - Google Patents

Abstract

PURPOSE:To prevent the generation of jitters for a phase comparator of a PLL oscillating device, by avoiding the coincidence between an effective edge of an input pulse of a standard frequency and the working timing of another digital circuit. CONSTITUTION:A PLL circuit is incorporated to a semiconductor substrate with a reference frequency of 30kHz obtained by dividing the original oscillation of 120kHz of an original oscillator 51 into 4 parts by a 4-frequency divider 53 together with a digital circuit having a working clock fop of 40kHz obtained by dividing the original oscillation into 3 parts by a 3-frequency divider 56. In such constitution, the output fOSC of the oscillator 51 is fed to the divider 53 via an inverter 52. Thus the change of the reference frequency is equal to the fall timing of the original oscillation. This device avoids the overlap between the edge of the working clock and the edge of the reference frequency and therefore prevents the jitters generated by the working clock of another digital circuit for the reference frequency pulse which is supplied to a phase comparator.

Description

[Detailed description of the invention] The present invention HPLL (Phase 1ocked 1oop
) type oscillator using an integrated circuit.

The PLL type oscillator uses a stable frequency generated by a crystal oscillator etc. as its reference frequency generator, so it is possible to obtain any CV extremely stable frequency, and there are almost no adjustment points. Nowadays, communication devices are widely used not only in communication but also in consumer radios and the like.

Furthermore, with recent advances in semiconductor technology, integrated circuits that incorporate PLL circuits on the same substrate as F microcomputers have come into wide use.

However, when a PLL circuit and other peripheral digital circuits such as a microcomputer are installed on the same board, noise generated from the other digital circuits causes QP
There is a problem in that the spurious is superimposed on the LL portion.The present invention aims to significantly reduce the occurrence of unnecessary spurious as described above.

A PLL oscillator according to the present invention includes at least one variable frequency input, one reference frequency input, a complete phase comparator, and other digital circuits other than the original oscillator for obtaining the reference frequency on the same semiconductor substrate. The integrated circuit has a feature that the effective processing in the phase comparator of the reference frequency manual pulse does not coincide with the timing at which the other digital circuits operate. A detailed description of the present invention will be provided with reference to the following.

FIG. 1 is a block diagram of a general PLL circuit. Output 2 of reference frequency generator 1 and variable frequency divider 3
The phase of output 4 is compared by phase comparator 5, and the phase of output 40 is delayed from output 2.
c) Exit the high level and exit the low level while progressing. If the phases of output 2 and output 4 are exactly the same, then V? -High impedance occurs at the H output cuff. L
A P F (low-pass filter) 8 integrates the entire signal on the output cuff, and supplies a DC voltage according to the waveform of the output cuff to a CO (voltage controlled oscillator) 9. The image is fired at a frequency corresponding to the output voltage of the VC09μLPF8, and the way it is raised is input to the variable frequency divider 3.

Since it is important to understand the operation of the phase comparator in understanding the present invention, only one phase comparator will be explained in more detail. Figure 2 shows the output 4 of the variable frequency divider 3 shown in Figure 1, the output 2 of the reference frequency generator 1, and the phase comparator 5.
FIG. 3 is a timing diagram showing the relationship between the cuff and the cuff. As is clear from FIG. 2, when the phase of output 4 is delayed compared to output 2, the interval level between the rising edge of output 4 and the rising edge of output 2 is output. Conversely, when the output 40 phase is ahead, a low level is output from the output cuff from the rising edge of VCiJ and output 4 to the rising edge of output 2. In cases other than these two, the output cuff μ is in a high impedance state.

As is clear from this explanation, in the phase comparator described here, phase comparison is performed at the rising edge of the input signal. That is, in this case, the effective edge in this phase comparison is the rising edge.

Theoretically, when the PLL is locked, that is, when the rising edges of output 2 and output 4 in Fig. 1 are completely overlapped, the output cuff is in a high impedance state. If the timing of the rising edge of output 2 and output 4 is even slightly different, the level corresponding to the phase difference should be output to the output cuff.

However, in an actual PLL, even in the locked state, the phases of the two inputs of the phase comparator are not fixed in a completely matched state, and as shown in Fig. 3, the phase of VC is shifted to some extent. It is generally fixed. In this case, a pulse is output from the output of the phase comparator 5 at a period of the reference frequency, and therefore the low-pass filter 8 may be designed to pass components below the reference frequency.

Next, consider the case where other digital circuits such as a microcomputer are incorporated into the same semiconductor substrate as the phase comparator.The original oscillation of 120 KHz is divided by 4 and Tc 30.
The same source oscillation as the PLL circuit with KHz as the reference frequency is
Assuming that a digital circuit having a divided fc 40 KHz operating clock is built on the same semiconductor substrate, the edges of the reference frequency pulse are the edges of the operating clocks of other digital circuits (!) as shown in FIG.
: Overlap at a period of 100 μ5 ec (= 10 KHz). Generally, in a digital circuit that operates in synchronization with a clock, the maximum power is consumed at the point where the clock changes, so the potential of the semiconductor substrate and the potential of the power supply etc. fluctuate in synchronization with the clock. do. Therefore, the reference frequency of the PLL section fluctuates in its rising edge every 100 μsec, which is observed as so-called jitter. Since jitter at the input of the phase comparator can be detected as a phase variation, in an integrated circuit configured like this, the 30 kHz component of the reference frequency is superimposed as the frequency component of the output waveform of the two-phase comparator. . Therefore, in a PLLN path that uses all the integrated circuits in this configuration, the cut-off frequency of the low-pass filter i'rlOKHz is subject to limitations, which increases the lock-up time of the PLL. There was a drawback.

FIG. 5 μ shows a reference frequency fref and operation clock fop generation circuit according to an embodiment of the present invention. The basic configuration of this circuit is the same as the circuit that generates the timing shown in FIG. 4, but the output fosc of the original oscillator 51
The difference is that is input to the 4-frequency divider 53 via the inverter 52.

FIG. 6 shows the circuit of FIG. 5, VC, C, 6 original oscillation fosc,
FIG. 3 is a typing diagram showing the timing of a reference frequency f ref and an operation clock fop. As is clear from FIG. 6, in this embodiment, since the inverter 52 is used, the change in the level of the reference frequency occurs at the falling timing of the original oscillation, the edge of the lv operation clock, and the edge of the reference frequency, which do not overlap. No jitter occurs. From this, the circuit in Figure 5? In the fcPLLc used, the frequency component of the output of the phase comparator is 30KH2, so compared to the case of Fig. 4, it is necessary to raise the cut-off frequency &t'r of the PLL.・Improve your time.

In addition, in Fig. 5, the change in the reference frequency was made at the falling timing of the all-nuclear photo shoot, so that the edge of the reference frequency and the edge of the operation clock did not match from Vc.
It goes without saying that the object of the present invention can also be achieved by changing the reference frequency at the rising edge and changing the operating clock at the falling edge of the original oscillation.

The 71st block diagram is a block diagram of another embodiment of the present invention. In addition, in the block of Fig. 7,
Blocks common to those in FIG. 5 are given the same numbers. In this embodiment, the output signal 72 of the 4-frequency divider 74 is converted into D-
A type 7 rig flop 75 is used to digitally delay the operation clock 55 so that the edge of the operating clock 55 and the edge of the reference frequency fref do not overlap.

FIG. 8 is a typing diagram showing the tying of these signals. In this embodiment, the etching of the reference frequency fref is digitally delayed.

This may be delayed using an analog method such as gate transmission delay. Further, in the embodiment shown in FIG. 7, the reference frequency fref is delayed, but the same effect can be obtained even if the operating clock fop is delayed.

FIG. 9 is a block diagram of an application of the embodiment shown in FIG. In this example, the operating clock in FIG. The reference frequency signal 73 is delayed by the reference frequency signal 73. In this way, in the present invention, 1
When there are multiple types of reference frequencies to be input into phase comparison, it is also possible to eliminate the influence of jitter caused by unused reference frequencies on the used reference frequencies.

As explained above, according to the present invention, in an integrated circuit including a three-phase comparator and other digital circuits, the reference frequency pulse input to the phase comparator is caused by the operating clock of the other digital circuits. The occurrence of jitter is eliminated, and the characteristics of the PLL are dramatically improved.

[Brief explanation of the drawing]

Fig. 1 shows a block diagram showing the operating principle of the PLL, Fig. 2 shows a timing diagram showing the operation of the phase comparator 5 in Fig. 1, and Fig. 3 shows the phase comparator of an actual PLL circuit.
Timing diagram showing till I'll', Figure 4 μ,
A block diagram showing how jitter is generated at the edge of a reference frequency pulse similarly generated due to the influence of an operation clock generated from a nuclear power plant (limb). FIG. 5 is a block diagram of an embodiment of the present invention. 6th quotient is a timing diagram showing the operation of the embodiment of FIG. 5, FIG. 7 is another embodiment of the present invention, and FIG. 8 rl is a timing diagram showing the operation of the embodiment of FIG. 7. Figure 9 μ is a block diagram showing an application example of the present invention. l Two single frequency generators, 3: variable frequency divider 7--U
--Kazuyoshi-UU----3rd Closing No. 4 Koku 53 r-----1

Claims (1)

[Claims] In an integrated circuit having a phase comparator having at least one variable frequency input and one reference frequency input and one peripheral digital circuit on the same semiconductor substrate, the reference valid in the phase comparator. An oscillation device characterized by the fact that the edge of the frequency human pulse does not coincide with the timing at which the peripheral digital circuit operates.