JPS62233953A - Jitter adding device - Google Patents

Abstract

PURPOSE:To extract a clock even to an input data signal with various different signal speeds by providing a modulation oscillator phaselocked with an IF signal by a phase locked loop circuit and receiving jitter by a modulation signal, the 2nd mixer and a snynchronizing circuit. CONSTITUTION:An IF signal f outputted from a mixer 2 and given to a band pass filter 4 is inputted to a phase comparator 5. The signal f1 and the output signal of a VCO 7 being a component of a PLL are inputted to the other input of the phase comparator 5. A modulation signal fM is added to the output signal of the phase comaprator 5 to be a control signal of the VCO 7 and the output signal f2 of the VCO 7 is subject to phase modulation and the result is sent to a mixer 8. A local signal fL is fed to the other input of the mixer 8. The outputted signal is a clock signal subjected to phase modulation in the same frequency as the basic frequency of the input data signal fR. The signal f3 is synchronized with the input data signal fR by a syhchroniziag circuit 10 to obtain a signal f4 being the addition of jitter to the input data signal fR.

Description

Detailed Description of the Invention "Industrial Application Field" This invention is intended to intentionally add jitter to a digital input data signal such as PCM within a communication line in order to evaluate the noise resistance characteristics of the communication line network. This relates to a device that attaches data and outputs data to a communication line.

"Prior Art" A conventional jitter adding device has a block configuration as shown in FIG. 3, for example.

The operation of the conventional device will be explained below based on FIG. The input data signal fR having harmonic components that has passed through the banfa amplifier 12 is sent to the synchronization circuit 19, and
The signal is guided to a clock extractor 14a corresponding to the signal speed, and a clock signal fc is extracted. This clock extractor generates a signal (clock) with the basic period of the input data. For example, a voltage controlled oscillator (VCO) with a period almost the same as the basic period of the input data is configured to be phase-locked by the input data. It has become. The frequency band of the PLL in this clock extractor is narrow and is set so that it does not respond to changes in the data of the input data signal "6" and is phase synchronized only to the fundamental frequency.

The clock signal rc extracted here is sent to the phase comparator 15.
The other input of this phase comparator 15a receives the clock signal fc and the VCO that constitutes the PLL.
The output signal of 17a is input. Note that the frequency band of this PLL is set wide so that modulation signals of various frequencies can be added. The modulation signal fM is added to the output signal of the phase comparator 15a to become a control signal for the VCO 17a. As a result, the output signal of the VCO 17a becomes a signal obtained by adding jitter to the clock signal fc of the basic cycle of the input data signal. The output signal of this VCO 17a is used as a clock signal, and the input data signal f is used in the synchronization circuit 19.
, l, it is possible to obtain a signal [6 with jitter added to the input data signal fR. The synchronous circuit 19 is configured by, for example, a delay type flip-flop. FIG. 4 shows this in the form of a timing chart.

To explain the operation of the conventional jitter adding device using a timing chart, the input data signal fR (FIG. 4A) that has passed through the buffer amplifier 12 has this basic circle! I.J.
IT is extracted by the clock extractor 14a, becomes a clock signal (FIG. 4B), and is input to the phase comparator 15a. In this phase comparator 15a, the clock signal and the VCO
The phase of the signal of 17a is compared and the phase difference output signal is
It is added to the modulation signal fH (FIG. 4C) in the amplifier 16a to become a control signal for the VCO 17a. For this reason, VCO1
The waveform of the output signal f5 of 7a is as shown in the fourth diagram. This output signal f has the same period as the clock signal output from the clock extractor 14a, and the modulated signal f
It is phase modulated by H. That is, it has phase jitter. By synchronizing the input data signal fR with this signal f, a signal fb (FIG. 4E) can be obtained. This signal f6 is the same data as the input data signal f11, with parentheses jitter added thereto.

"Problems to be Solved by the Invention" In the conventional jitter adding device configured as described above, the clock extractor and modulation circuit (the part within the broken line in Figure 3) only required. That is, it is necessary to prepare a separate clock extractor and modulation circuit each time the basic cycle of data on a communication line to which jitter is to be added differs. Furthermore, since the circuit characteristics of PLLs configured to correspond to different clock signals are also different from each other, even if the modulation signal has the same magnitude, the PLL input to the modulation signal is
There are disadvantages such as the value of the modulation degree differing depending on the difference.

"Means for Solving the Problem" A first mixer for mixing an input data signal and a local signal to obtain an IF multiplied signal of a constant frequency, and a local signal having a frequency corresponding to the frequency of the input data signal to the first mixer. a local oscillator for supplying
A modulation oscillator which synchronizes the phase of the IF multiplied signal by a phase locked loop (PLL) and adds jitter by a modulation signal, and mixes the signal output from this modulation oscillator with the local signal to generate the original input. By providing a second mixer that outputs a signal having the same period as the basic period of the data signal, and a synchronization circuit for synchronizing the output signal of the second mixer and the input data signal,
For input data signals of various different signal speeds,
Clock extraction can be performed by changing the frequency of the local signal.

“Embodiments of the invention” FIG. 1 shows a block diagram of the present invention.

The input data signal fR having harmonic components that has passed through the buffer amplifier 1 is sent to the synchronization circuit 10, mixed with the local signal fL, and sent to the mixer 2 to obtain a constant frequency IF multiplied signal. A local oscillator 3 is connected to the other input of the mixer 2 in order to supply a local signal fL of a frequency corresponding to the frequency of the input data signal r. This local signal fL can be used to switch multiple crystal oscillators or
It can be obtained using a synthesizer. That is, this local oscillator 3 is adjusted so that the IF multiplied signal frequency obtained by the mixer 2 is always constant even when the fundamental frequency of the input data signal fR differs.

In this example, the mixer 2 mixes the fundamental wave and harmonics of the input data signal fR with the local signal rL to extract an IF of a constant frequency. Therefore, even if the instantaneous input data is 1/N of the fundamental frequency, the mixer 2 can mix N times higher harmonics with the local signal fL to obtain IF, so the input data signals f and I can be Continuous IF multiplication signal even if it is discontinuous.

can be obtained.

Output from mixer 2 and hand bathtub) Lt lid
The IF multiplied signal that has passed is input to the phase comparator 5. The other input of the phase comparator 5 receives the signal f and the output signal of the VCO 7 forming the PLL. A modulation signal f is added to the output signal of this phase comparator 5. is added to become the control signal of VCO7, and the output signal f2 of VCO7 is:
It will undergo phase modulation. The output signal f2 of the VCO 7 having the same frequency and phase jitter as this signal rl is sent to the mixer 8. The other input of this mixer 8 is supplied with the same local signal fL as the signal sent to the mixer 2 by the local oscillator 3. No. 13 outputted from the mixer 8 illuminates the low-pass filter 9 and becomes a signal f.

This signal r, is a clock signal that is phase modulated at the same frequency as the fundamental frequency of the original input data signal fR. In the synchronous circuit 10, the input data signal r,
By synchronizing the input data signals f and I, a signal f4 with jitter added is obtained.

The above operation will be explained using the timing chart shown in FIG. 2. After passing through the buffer amplifier 1, the input data signal fR (FIG. 2A) is sent to the synchronization circuit 10 and input to the mixer 2. A local signal fL (FIG. 2B) is input to the other input of this mixer 2. The input data signals f and l are mixed with the local signal fL in the mixer 2, and then output and passed through the bandpass filter 4! F signal f, (Fig. 2 C)
becomes. The IF multiplied signal 1 is input to the phase comparator 5.

The signal output from this phase comparator 5 includes a modulation signal r,
4 (Fig. 2D) is added in amplifier 6 and VCO 7
This control signal causes the output signal of the VCO 7 to become f (FIG. 2E). This signal f2 is obtained by phase modulating the signal f. The output signal f2 of the VCO 7 is input to the phase comparator 5 and also to the mixer 8. The other input of mixer 8 is
Local signal fL same as the signal input to mixer 2
(FIG. 2B) is input. After f2 is mixed with fL in mixer 8, it is output and passes through low-pass filter 9 to become signal r3 (FIG. 2F). This signal r3 is a jittered clock signal having the same frequency as the fundamental frequency of the input data signal fR. By synchronizing the input data signal fR with this signal r in the synchronization circuit 10, the signal "4 (G in FIG. 2) can be obtained. This signal f4 is a waveform of one input data signal with jitter added. becomes.

Although the local signal fL is not particularly specified in the above embodiment, it is mixed with the local signal fL having a frequency N times that of the input data signal rR in the mixer 2 using a bandpass filter 4 having a high center frequency. After obtaining a high-frequency IF multiplied signal, the output of the mixer 8 may be reduced to 1/N to obtain a signal having the same frequency as the fundamental frequency of the input data signal fR.

"Effects of the Invention" □ The present invention having the above configuration can handle various input data signals with different signal speeds without providing a corresponding clock extractor for each input data signal speed. This makes it possible to extract the clock using a single circuit, which simplifies the circuit, and has the effect that the value of the degree of modulation becomes constant as long as the modulation signal has the same magnitude, regardless of the speed of the input data signal.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 2 shows a timing chart based on the block diagram of FIG. FIG. 3 shows a block diagram of a conventional thick adding device. FIG. 4 shows a timing chart based on the block diagram of FIG. 3. 1.11,12,20; Buffer amplifier. 2.8: Mixer. 3; Local oscillator. 4; Bandpass filter. 5.15a, 15b; Phase comparator. 6.16a, 16b;;amplifier. 7.17a, 17b; VCO. 9; Low pass filter. 10.19i synchronous circuit. 13a, 13b, 18a, 18b; switch. 14a, 14b; clock extractor.

Claims (2)

[Claims] (1) a first mixer for mixing an input data signal and a local signal to obtain an IF signal of a constant frequency;
A local oscillator for supplying a local signal with a frequency corresponding to the input data signal frequency to the first mixer and a phase locked loop (PLL) synchronize the phase with the IF signal, and add jitter by the modulation signal. a second mixer that mixes the signal output from the modulation oscillator and the local signal to output a signal having the same period as the fundamental period of the original input data signal, and the second mixer. A jitter adding device comprising a synchronization circuit for synchronizing the output signal of the above and the input data signal. (2) After the first mixer mixes the input data signal with N times the high frequency to obtain the IF signal, the output of the second mixer is set to I/N and the period is the same as the fundamental period of the original input data signal. 2. A jitter adding device according to claim 1, which obtains a signal of: