JPH0738577B2 - Jitter adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field of application" The present invention intentionally adds jitter to a digital input data signal such as PCM in a communication line in order to evaluate noise resistance characteristics of a communication line network. However, the present invention relates to a device for outputting to a communication line.

"Prior Art" Conventionally, for example, there is a device described in Japanese Patent Laid-Open No. 62-233953, and this device has a block configuration as shown in FIG. The operation of the conventional jitter adding apparatus will be described below with reference to the block diagram of FIG.

Actual input data signal (hereinafter referred to as input data signal) that passes through the buffer amplifier (1a) and has harmonic components
S _R is sent to the synchronization circuit (8) and at the same time the local signal S _L
And the first mixer (2
sent to a). A local oscillator (3) is connected to the other input of the first mixer (2a) in order to supply a local signal S _L corresponding to the nominal rate of the actually input data signal S _R. That is, the oscillation frequency of this local oscillator (3) is determined by the nominal rate of the data signal.

In this example, the input data signal in the first mixer (2a)
The fundamental wave and harmonics of S _R are mixed with the local signal S _L to extract the IF signal S _I of constant frequency. Therefore, even if the instantaneous input data is 1 / N of the fundamental frequency, the IF signal S _I can be obtained by mixing the N times higher harmonic and the local signal S _L by the first mixer (2a). Therefore, even if the input data signal S _R is discontinuous,
It becomes possible to obtain the IF signal S _I.

The signal output from the first mixer (2a) passes through the bandpass filter (4) to become the signal S _I , which is input to the phase comparator (5). The other input of this phase comparator (5) is connected to the signal S _I and the VCO that constitutes the phase synchronization circuit.
The output signal of (6) is input. The modulation signal S _M is added to the output signal of the phase comparator (5) and becomes the control signal of the VCO (6). Therefore, the output signal S _I of the VCO (6) undergoes phase modulation. The output signal S ₁ of the VCO (6) having the same frequency as the signal S _I and phase jitter is sent to the second mixer (2b). The other input of this second mixer (2b) has the same local signal S _L as the signal sent to the first mixer (2a) by the local oscillator (3) in the previous term.
Is supplied.

The signal output from the second mixer (2b) passes through the low pass filter (7) and becomes the signal S ₂ . This signal S ₂ is a clock signal that is purposely phase-modulated with the same frequency as the fundamental frequency of the original input data signal S _R. Synchronous circuit (8)
In this case, by synchronizing the input data signal S _R with the signal S ₂ , it is possible to obtain the signal S ₃ in which the input data signal is intentionally added with jitter.

FIG. 4 is a timing chart when it is assumed that the input data signal S _R does not have jitter and there is no frequency offset from the nominal rate of the data signal in the above device. .

[Problems to be Solved by the Invention] In the conventional jitter adding device configured as described above, the frequency of the local signal S _L output from the local oscillator (3) is changed according to the nominal rate of the data signal. It is set. For this reason, it is possible that a frequency offset T exists between the nominal rate signal S and the actually input input data signal S _R. When the offset value is large, the IF signal S _I cannot pass through the band pass filter (4), and the VCO (6) cannot be phase-locked. In such a case, the reproduced clock signal S _I becomes a signal having nothing to do with the input data signal S _R. If the band of the band pass filter (4) is widened in order to prevent this phenomenon, the jitter of the input data signal S _R is not reduced, and the reproduced clock signal S ₂ has other than the intentionally added jitter. The jitter that the original input data signal S _R has is present. FIG. 5 is a timing chart showing this state.

"Means for Solving Problems" An oscillator that outputs a signal in which an IF signal is phase-synchronized in an automatic frequency control circuit, a first mixer that mixes an input data signal and a local signal to obtain the IF signal, A local oscillator for supplying a local signal having a frequency corresponding to the input data signal to the first mixer, and a modulation in which a phase synchronization circuit synchronizes the phase with the output signal of the oscillator and adds a jitter by the modulation signal. Oscillator, a second mixer for mixing the signal output from the modulating oscillator and the local signal to output a signal having the same period as the fundamental period of the original input data signal, and the output of the second mixer By providing a synchronization circuit to synchronize the signal with the input data signal, low frequency jitter existing in the input data signal is reduced. In addition, even if there is a frequency offset between the actually input data signal and the nominal rate of that data signal, there is no irregular phase difference between the actually input data signal and the intention. A data signal with only the added jitter is obtained.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.

The input data signal S _R having the harmonic component that has passed through the buffer amplifier (1a) is sent to the synchronizing circuit (8) and is mixed with the local signal S _L to obtain the IF signal.
Sent to the mixer (2a). A local oscillator (3) is connected to another input of the first mixer (2a) to supply a local signal S _L corresponding to the frequency of the input data signal S _R. This local oscillator (3) can be obtained by switching a plurality of crystal oscillators or by using a synthesizer.

In this example, the input data signal in the first mixer (2a)
By mixing the fundamental wave and harmonics of S _R and the local signal S _L , the IF signal S _I having a constant frequency is taken out. Therefore, even if the instantaneous data has a frequency of 1 / N of the fundamental wave, the IF signal S _I can be obtained by mixing the N times higher harmonic and the local signal S _L by the first mixer (2a). Even if the input data signal S _R is discontinuous, a continuous IF signal S _I can be obtained.

The IF signal S _I output from the first mixer (2a) and passed through the bandpass filter (4) is the first phase comparator (5a).
Entered in. It is assumed here that the bandpass filter (4) is set to a relatively wide band. This allows the IF signal S _I to pass through the bandpass filter (4) even if there is a frequency offset between the nominal rate signal S and the input data signal S _R.

The output signal S _V of the first VCO (6a) whose frequency is always constant is input to the other input of the first phase comparator (5a). Therefore, the IF signal S _I is synchronized with the output signal S _V of the first VCO,
The output signal of the first phase comparator (5a) is input to the local oscillator (3) through the low pass filter (7a). As a result, the frequency of the IF signal S _I is controlled so that it is always constant. That is, when the actual input data signal S _R has a frequency offset with respect to the nominal rate, the frequency of the local signal S _L is automatically set according to the offset amount.

The output signal S _V of the first VCO (6a) is input to the first phase comparator (5a) and also to the second phase comparator (5b).
The other input of this second phase comparator (5b) is
The output signal S _V of CO (6a) and the output signal S ₁ of the second VCO (6b) forming the PLL are input. The modulation signal S _M is added to the output signal of the second phase comparator (5b) to become the control signal of the second VCO (6b), and the output signal S ₁ of the second VCO (6b) undergoes phase modulation.

The output signal S ₁ of the second VCO (6b) is sent to the second mixer (2b). The other input of this second mixer (2b)
The same local signal S _L as the signal input to the first mixer (2a) is supplied from the local oscillator (3). Second
The signal output from the mixer (2b) passes through the low pass filter (7b) and becomes the signal S ₂ . This signal S ₂ is a clock signal arbitrarily phase-modulated at the same frequency as the fundamental frequency of the original input data signal S _R. By synchronizing this signal S ₂ with the input data signal S _R in the synchronizing signal (8), the signal S ₃ in which only the intended jitter is added to the input data signal S _R can be obtained.

In the above synchronizing circuit (8), the signal S ₂ is adapted to be synchronized with the portion of the input data signal S _R where jitter is not present. This causes the modulation signal S _M forming the control signal of the second VCO (6b) to include a constant DC voltage E as an offset voltage, so that a steady phase is provided between the signal S ₂ and the input data signal S _R. It can be realized by making it exist.

The above operation will be described with reference to the timing chart shown in FIG. 2. The input data signal S _R sent to the synchronous circuit (8) and the first mixer (2a) after passing through the buffer amplifier (1a) is a nominal rate signal. There is a frequency offset T and jitter with respect to S. The input data signal S _R is mixed with the local signal S _L output from the local oscillator (3) in the first mixer (2a) and then passed through the bandpass filter (4) to become the IF signal S _I , which is the first phase. It is input to the comparator (5a). The other input of the first phase comparator (5a) has a first VCO (6
The output signal S _{V of} a) is input, and the signal S _V
Always frequency of the IF signal S _I by synchronizing the _I is constant. That is, the frequency of the local signal S _L is controlled according to the average frequency of the input data signal S _R.

The output signal S _V of the first VCO (6a) input to the first phase comparator (5a) is also input to the second phase comparator (5b). The modulation signal S _M is added to the signal output from the second phase comparator (5b) in the amplifier (1b) to become the control signal of the second VCO (6b), and the output signal of the second VCO (6b) is generated by this control signal. Is
It becomes S ₁ . The signal S ₁ has the same frequency as that of the signal S _I, and the influence of the low frequency jitter of the data signal S _R is reduced, and an arbitrary jitter is further added. The signal S ₁ is input to the second phase comparator (5b) and the second mixer (2b). The same local signal S _L as the signal input to the first mixer (2a) is input to the other input of the second mixer (2b).

The signal S ₁ is mixed with the local signal S _L in the second mixer (2b) and passes through the low pass filter (7b) to become the signal S ₂ . This signal S ₂ is a clock signal in which arbitrary jitter is added at the same frequency as the fundamental frequency of the actually input data signal, and low-frequency input jitter is reduced. By synchronizing this signal S ₂ with the input data signal S _R in the synchronizing circuit (8), the low frequency jitter existing in the signal S _R is reduced and it is synchronized with the average phase of the signal S _R. The resulting signal S ₃ has the added jitter.

In the above embodiments, the local signal S _L is not specified, but a bandpass filter (4) having a high center frequency is used to increase the N times the input data signal in the first mixer (2a). After mixing with the local signal S _L having a frequency to obtain a high frequency IF signal, the output of the second mixer (2b) is set to 1 / N and a signal having the same frequency as the fundamental frequency of the input data signal S _R is generated. It may be configured to obtain.

"Effect of the invention" The constant frequency jitter existing in the input data signal is reduced,
Moreover, it is possible to obtain a data signal which is synchronized with the average phase of the input data signal and to which an arbitrary jitter is added.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a timing chart in FIG. FIG. 3 shows a block diagram of a conventional jitter adding apparatus. Fourth
The figure shows a timing chart when it is assumed that there is no frequency offset between the input data signal and the nominal rate signal in the conventional jitter adding device and the input data signal does not have low frequency jitter. There is. FIG. 5 shows a timing chart in the case where a frequency offset exists between the nominal rate signal and the input data signal and the input data signal has low frequency jitter in the conventional jitter adding apparatus. 1a to 1c; Buffer amplifier 2a, 2b; Mixer 3; Local oscillator 4; Bandpass filter 5, 5a, 5b; Phase comparator 6, 6a, 6b; Voltage controlled oscillator (VCO) 7, 7a, 7b; Lowpass filter 8 ; synchronizing circuit T; frequency offset E; DC voltage S; nominal rate signal S _R; input data signal S _L; local signal S _I; IF signal S _V; output signal of the 1VCO S _M; modulated signal S _1; first 2VCO (Modulation oscillator) output signal S ₂ ; Regenerated clock signal S ₃ ; Synchronous circuit output signal

Claims (2)

[Claims] 1. A first oscillator for outputting a signal in which an IF signal is phase-synchronized in an automatic frequency control circuit, a first mixer for mixing an input data signal and a local signal to obtain the IF signal, A local oscillator for supplying a local signal of a frequency corresponding to the input data signal to the first mixer, and a phase synchronization circuit are phase-synchronized with the output signal of the first oscillator and jitter is added by the modulation signal. A modulation oscillator, a second mixer that mixes the signal output from the modulation oscillator with the local signal, and outputs a signal having the same cycle as the fundamental cycle of the original input data signal, and the second mixer A jitter adding device comprising a synchronizing circuit for synchronizing an output signal and the input data signal. 2. The first mixer, after mixing with an N times higher frequency of the input data signal to obtain an IF signal, makes the output of the second mixer 1 / N and has the same period as the fundamental period of the original input data signal. The jitter adding apparatus according to claim 1, which obtains a signal that becomes