JPS6193719A - Phase locked loop device - Google Patents

Abstract

PURPOSE:To keep a stable pull-in and a stable locking state by inserting a frequency detection loop in a phase locked loop as required. CONSTITUTION:A frequency comparator FC compares the oscillation frequency of a VCO with an oscillated frequency of a crystal control oscillator OSC and when they are parted for a prescribed value or over, an output is fed to an adder circuit MIX via a switch SW. Thus, when the oscillation frequency of the VCO is parted by, e.g., several % or over from the oscillated frequency of the OSC, the frequency comparison and phase comparison loops are provided and when the frequency deviation is within several %, the loop for phase comparison only is provided. Thus, stable pull-in and stable locking state are maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a phase-locked loop device having an improved synchronous clock extraction circuit.

[Prior art]

As a conventionally known phase aperture and loop device,
A configuration as shown in FIG. 1(A) or FIG. 1(B) is known. Here, PC is a phase comparator, LPF is a low-pass filter, vCO is a voltage controlled oscillator, and FC is a frequency comparator.

When the phase-locked loop is configured as shown in Fig. 1 (A), phase comparison is performed only at the inverted portion of the input signal IN, and the phase-locked loop circuit performs phase comparison at a frequency different from the actual transmission rate. This causes the inconvenience of locking up. In order to avoid such inconveniences, relatively complex control such as (1) limiting the oscillation range of the voltage controlled oscillator VCO; (2) controlling the pull-in so that it is pulled in from a certain direction at the time of pull-in is required.

Furthermore, when the phase-locked loop is configured as shown in Figure 1 (B), if a signal dropout occurs in the input signal IN for some reason, it will be caused by the insertion of the frequency comparator FC. As a result, an unnecessarily large voltage may be supplied to the voltage controlled oscillator vCO, and the synchronization clock may be disturbed. Thus, in the configuration shown in FIG. 1(B).

There is a problem in that signal loss due to dropout etc. has a large effect.

〔the purpose〕

In view of the above-mentioned points, an object of the present invention is to provide a simple phase-locked loop device that operates stably even during pull-in and maintains a stable phase-locked state even when signal loss occurs after locking. This is achieved through configuration.

In order to achieve this object, the present invention, as shown in FIG. 2, introduces the output signal of the variable frequency oscillation means 0 and a predetermined input signal IN, and transmits an output signal according to the phase difference. a detection means P; and a frequency comparison means F for transmitting an output signal according to the difference between the reference frequency and the output frequency when the output frequency of the variable frequency oscillation means 0 deviates from the reference frequency by a predetermined frequency or more; It is characterized by comprising a mixing means M for adding the output signal of the phase difference detection means P and the output signal of the frequency comparison means F and supplying the sum to the variable frequency oscillation means 0.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

Kokote ρC, LPF, VCO, FCt*Already shown in Figure 1 (A
) and CB), respectively, a phase comparator,
It shows a low pass filter, a voltage controlled oscillator, and a frequency comparator. Also, OSC is a crystal controlled oscillator and LC is a level detector. Furthermore, SW is a switching circuit for sending the output signal from the frequency comparator FC to the adder circuit MIX in accordance with the output signal from the level detector LC.

FIG. 4 is a circuit diagram illustrating the configuration shown in FIG. 2 in more detail.

In this figure, l is an innohake that inverts the output of the voltage controlled oscillator 9.

2 is a delay circuit (OL) that delays the input signal IN; 3 is an inverter connected to the output terminal of the d delay circuit 2; 4 is an AND circuit that introduces the output signal of this inverter 3 and the input signal IN; 5 and 6 7 is a DyE flip-flop which is connected to the input circuit 1 and ANDN0 to form a phase comparator, and 7 is a charge pump circuit (cp) connected to the flip-flop 5.6.

Resistor R, -R3, capacitor C+,) transistor TR
I and TR2 are filter circuits forming a loop filter together with charge pump circuit 7, and 8 is resistors R7 to R9.
an adder formed with the switch 19 and introducing the signal from the switch 19 and the output signal of the loop filter.

9 is a voltage controlled oscillator controlled by the output of the adder 8; 10 is a frequency divider that divides the output signal of the voltage controlled oscillator 9 by 1/N;

11 is a crystal controlled oscillator having a frequency that is an integral multiple of the transmission rate of the input signal IN; 12 is a frequency divider that divides the output signal of the crystal controlled oscillator 11 by 1/N; and 13 is an input signal for the output signal of the frequency divider 10. 14 is a charge pump circuit connected to the monostable multivibrator 13 and frequency divider 12, resistors R4 to R6, capacitor C2, and transistor TR.
3, TR4 is a filter circuit that forms a loop filter together with the charge pump circuit 14; 15 is an amplifier that determines the offset and gain together with the resistor RiolR4L, the capacitor C2, and the variable resistor VRI; 16 and 17 connect the output of the amplifier 15 to 2 18 is the AN connected to the output terminal of comparator 1B and 17.
The D circuit 18 is a switch circuit that switches the input terminal to the adder 8 to the ground side or to the amplifier 15 side according to the output of the AND circuit 18.

Next, the operation of FIG. 4 will be explained with reference to the timing diagrams shown in FIGS. 5(A) to 5(C).

In this embodiment shown in FIG. 4, an MFM (
Modified Frequency Mod
lation) A modulated information signal is input. When the transmission rate of this signal is M bits/second, the delay circuit 2 is used with a delay amount such that T=1/8 seconds including the delay of the inverter 3.

If the input signal is the signal shown by ■ in Figure 5 (A), the output signal of the inverter 3 will be as shown in Figure 5 (A),
+i L for the rising edge of the input signal
f″″/4 (7) It@(7)/<JL-X′I! 9
．． t'L6/human power signal IN is v shown in Fig. 5 (A) ■
Figure 5 (
A) When the phase is delayed as shown by the dotted line (2), the output of the AND gate 4 also becomes like the dotted line shown in (A) (2) in FIG. Therefore, when the output of the AND gate 4 becomes high level, the D input and clear input of the D type flip-flop 5 become high level, so if the output of the inverter l rises during this time, the output Q of the D type flip-flop 5 becomes After rising, the output of the AND gate 4 remains at a high level until it becomes a low level, and a pulse train with a pulse width proportional to the phase shift is obtained as shown in FIG. 5(A).

Considering the D-type flip-flop 6, if the input phase is delayed with respect to the clock as shown in FIG. 5(A), when the output of the AND gate 4 rises, the clock (see FIG. A) ■) is always at a high level, and since the vCO clock is introduced into the clear terminal of the D-type flip-flop 6 via the inverter 1, the clear terminal goes to a low level at the rising edge of the clock, and the D-type flip-flop 6 The output Q of does not become high level.

Next, as shown by the dotted line in Fig. 5(B) (■), if the input data is input with a phase lead relative to the vCO clock,
The clock input of the D5 flip-flop a+7 block 6, that is, the output of the AND gate 4 (Fig. 5 (B) ■), rises when the vCO clock is at a low level (that is, the clear terminal of the D-type flip-flop 6 is at a high level). occurs in The output Q of the D-type flip-flop 6 rises due to the rise of the AND gate 4, and remains at a high level until the next vCO clock edge occurs, and a pulse train with a pulse width proportional to the amount of phase advance is generated as shown in Fig. 5 (B) (■). obtained as shown.

Further, in the D-type flip-flop 5, since the clear terminal becomes low level at the rising edge of the clock, the output does not become high level but exhibits low level.

If the phases of the input signal and vCO clock match,
The outputs of each flip-flop are both high level, and there is a thin pulse force at the edge of the input signal? If you leave, you will stay.

Regarding the charge pump 7, when the input pu is at a low level, the output OF is at a high level, when the input Pu is at a high level, the output 11F is at a high impedance, and the input PDf is at a high level.
Output when J90- level [IF is low level, input P
When D is at a high level, the output OF operates to have a high impedance. In other words, when the input signal is in a delayed phase, the Q output of the D-type flip-flop 5 is introduced into the human power Pu of the charge pump 7, so the input PU becomes low level during the delay time, and during that time the output IF becomes high level, R, -R2, C,, TRI, TR2
Charges up the loop filter configured by Further, in the case of an advanced phase, the input PD becomes low level, and the charge pump 7 is discharged. Therefore, a DC voltage corresponding to the phase shift can be obtained from the loop filter. This output is applied to a voltage controlled oscillator 9 via an adder 8.

The output of the voltage controlled oscillator 9 has a period of 10 divided by 1/N (for example, N
= 2), and 1 as shown in Figure 5 (C) ■ and ■.
/N, and its falling edge triggers the monostable multivibrator 13. The output pulse width of the monostable multivibrator 13 is set in advance to a width of 1/2 by adjusting the RIZIC 3.

The oscillation frequency of the crystal controlled oscillator 11 is set to a frequency that is an integral multiple of the transmission rate of the input signal, and is divided by 1/N in the division period 12.
A large PD input is added.

When the oscillation frequency of the voltage-controlled oscillator 9 is lower than the oscillation frequency of the crystal-controlled oscillator 11, the oscillation waveform of the voltage-controlled oscillator 9 becomes as shown in FIG. (C) The number of pulses per unit time is reduced compared to the output of the crystal controlled oscillator 11.

On the other hand, the oscillation frequency of the voltage controlled oscillator 9 is crystal controlled.
When the oscillation frequency is higher than the oscillation frequency of the control oscillator 11, as shown in FIG.
C) As shown in ■ and ■, the number of pulses increases. This pulse is supplied to the input terminal of the charge pump 14, thereby charging and discharging the low-pass filter constituted by R4 to R, , C2, TR3, and TR4, and the voltage controlled oscillator 9.
generates a voltage proportional to the oscillation frequency. Then, using the next stage R50+RB+VR1 and the amplifier 15, the output is adjusted to be zero when the oscillation frequency difference between the voltage controlled oscillator 9 and the crystal controlled oscillator 11 is zero, and the output is changed to the differential comparator 16.1? Enter.

Differential comparator 113.1? The threshold values are set to 1 so that the oscillation frequency of the voltage-controlled oscillator 9 corresponds to approximately 1% of the oscillation frequency of the crystal-controlled oscillator 11, respectively, with respect to zero. AND game)
18, when the oscillation frequency of the voltage controlled oscillator 9 becomes within 10% of the oscillation frequency of the crystal controlled oscillator 11, the output of the AND gate 18 becomes high level, and the switch 18 is connected to the ground side. let In addition, when the oscillation frequencies of the voltage controlled oscillator 9 are different from each other by more than a few percent, the switch is turned upward in the figure, and the amplifier 15
is applied to one end of resistor R8.

By doing this, when the oscillation frequency of the voltage controlled oscillator 9 is far from the desired frequency, both frequency comparison and phase comparison loops are provided, and if the same wave number deviation is within a few percent, The loop consists only of phase comparison.

In addition, in the above-mentioned embodiment, only the case of an input signal subjected to MFM modulation was described, but other modulation methods (for example, FM, other group coding modulation methods) may be used.
But you can get the same effect.

〔effect〕

As described above, according to the present invention, a frequency detection loop can be incorporated into the phase lock loop as necessary, so that stable pull-in and stable locking can be maintained.

More specifically, when the output frequency of the voltage controlled oscillator is different from the oscillation frequency of the crystal oscillator by, for example, several percent or more, a frequency detection loop is added to the phase-locked loop.
Furthermore, when the deviation is within a few percent, it is possible to automatically switch to a phase lock loop that only includes phase comparison, so that stable pull-in and stable locking can be achieved.

[Brief explanation of the drawing]

FIGS. 1A and 1B are block diagrams explaining the prior art, and FIG. 2 is a schematic configuration diagram of the present invention. FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is a line diagram showing the embodiment shown in FIG. 3 in more detail, and FIGS. FIG. 2 is a waveform diagram for explaining. pc...phase comparator, MIX...addition circuit, LPF...low pass filter. VCO: Voltage controlled oscillator, FC: Frequency comparator. 0SC: Crystal controlled oscillator, LC: Level detector. SW...Switching circuit, 1...Inverter, 2...Delay circuit 3...Inverter, 4...AND circuit, 5.8...D type flip-flop (phase comparator), 7
...Charge pump circuit. 8... Adder, 9... Voltage controlled oscillator, 10... 1/N frequency divider, 11... Crystal controlled oscillator, 12... 1/N frequency divider, 13... Single Stable multi/haze regulator, 14...Charge pump circuit, 15...Amplifier, □! 16. s7... Differential comparator, 18... AND circuit, 18... Switch circuit. Figure 1 ○00■■■ ○O■■ < RO■■ OO■ ■O

Claims (1)

[Claims] 1) phase difference detection means for introducing an output signal of the variable frequency oscillation means and a predetermined input signal and sending out an output signal according to the phase difference thereof; frequency comparing means for sending out an output signal according to the difference between the reference frequency and the output frequency when the frequency deviates from the reference frequency by a predetermined frequency; and an output signal of the phase difference detecting means and an output of the frequency comparing means. 1. A phase-locked loop device comprising: mixing means for adding the signals to the variable frequency oscillation means and supplying the mixed signal to the variable frequency oscillation means. 2) The phase-locked loop device according to claim 1, wherein the variable frequency oscillation means is constructed using a low-pass filter and a voltage-controlled oscillator.