JPH0276418A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain the high stability of a PLL circuit for generating a clock phase-locked with an input clock in a digital video tape recorder or the like by providing the PLL circuit with a reference frequency oscillator. CONSTITUTION:Data indicating a reproducing mode are inputted to an input terminal 201 and the frequency dividing ratio of a frequency divider 203 is set up through a data conversion table 202. The frequency of an output from a voltage controlled oscillator 207 is divided by the frequency divider 203 on the basis of the frequency dividing ratio N set up in accordance with a mode, the phase-divided signal is compared with a horizontally synchronizing signal fH in a reproducing signal inputted to an input terminal 204 by a phase comparator 205 and a phase-compared voltage S20 is outputted. A high frequency component in the voltage S20 is cut out by a loop filter 206 and an error voltage S21 is outputted. The frequency of a clock S23 generated from the oscillator 207 is controlled by the voltage S21 and a reference clock with frequency corresponding to each mode is outputted to an output terminal 208 and supplied to a frequency phase comparator. The center frequency of the oscillator 207 is locked to the reference clock inputted to the terminal and high stability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit for generating a clock phase-synchronized with an input clock.

[Prior Art] PLL circuits are used for various purposes. For example, in a device that records and reproduces a digital signal, such as a digital video tape recorder (D-VTR), it is essential to generate a clock that is phase-synchronized with the reproduced signal when extracting data from the reproduced signal.

In this specification, the PLL applied to the VTR will be described as follows.
This will be explained using a circuit as an example. FIG. 3 is a diagram showing the configuration of a conventional general PLL circuit used in a D-VTR.

In the figure, a phase comparator (PC) 302 compares the phase of a clock obtained from a reproduced signal input to an input terminal 301 with a clock C1 output from a voltage controlled oscillator (VCO) 304, and outputs a phase comparison voltage S1. be done. The high frequency component of the phase comparison voltage Sl is cut by the loop filter 303, and an error voltage S2 is generated at the output of the loop filter 303. This error voltage S2 controls the frequency of the clock CI which is the output of the voltage controlled oscillator (VCO) 304 mentioned above.

With the above configuration, the PLL circuit outputs the clock CI phase-synchronized with the clock component of the reproduced signal to the output terminal 305.
data can be extracted from the reproduced signal according to this clock.

[Problem that the invention seeks to solve]

By the way, when the above-mentioned PLL circuit is used to form a clock for data extraction of a D-VTR, it is necessary to widen the lock range so that lock can be achieved over a wide frequency range. This occurs when playing back while transporting the tape at a speed different from that during standard recording and playback.
This is because the frequency of the clock component in the reproduced signal changes when performing playback in a long-time mode (cue, review, etc.) or in a long-time mode.

However, if the lock range is widened, the stability of the PLL deteriorates accordingly, so it is necessary to secure the lock range over a wide frequency range while ensuring stability against jitter, which is required for D-VTRs, etc. It was difficult to do so.

This invention was made in view of these points, and it is a PL that can be locked over a wide frequency range and has high stability.
The purpose is to provide an L circuit.

[Means for solving problems]

For this purpose, the present invention provides a PLL circuit that generates a clock that is phase-synchronized with an input clock, including a phase comparator that receives the input clock as one input, a reference oscillation circuit, and an output of the reference oscillation circuit that is connected to one of the input clocks. and a controlled oscillation circuit that is controlled based on the outputs of the phase comparator and the frequency phase comparator and provides the other input of the phase comparator and the frequency phase comparator. And so.

[For production]

By configuring as described above, if the output frequency of the reference oscillation circuit is changed even when the frequency of the input clock changes, the controlled oscillation circuit can be configured to have high stability with respect to the output of the phase comparator. Can be done. As a result, it was possible to configure a PLL circuit that is locked over a wide frequency range and has high stability.

〔Example〕

Examples of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of a PLL circuit as an embodiment of the present invention, which is used to form a clock for extracting data from a reproduced signal of a D-VTR.

In Fig. 1, input terminal 10]1 phase comparator (pc)
102, loop filter 103. Voltage controlled oscillator (VC
O) 105 and the output terminal 106 have the same configuration as a conventional PLL circuit, and the loop composed of these is hereinafter referred to as a data phase locked loop.

Also, a reference frequency oscillator (Ref, 08C) 107. Frequency phase comparator (FPC) 108 and loop filter 1
09 is a circuit for locking the center frequency of the VCO 105, and a loop including these is hereinafter referred to as a center frequency lock loop.

The PLL circuit shown in FIG. 1 includes a data phase locked loop having a similar configuration to the PLL circuit shown in FIG.
The configuration includes an additional center frequency lock loop that allows the center frequency of 5 to be controlled over a wide range. As mentioned above, the reference frequency oscillator 107 generates a clock signal with a frequency corresponding to each mode in which the frequency of the clock component in the reproduced signal is different, and generates a clock signal with a frequency corresponding to each mode in which the frequency of the clock component in the reproduction signal is different. (several percent or more). That is, by locking the center frequency of the VCO 105 near the clock frequency corresponding to each mode, high stability is achieved by narrowing the lock range determined by the time constant of the loop filter 103, and
The configuration is such that it can accommodate changes of about several percent in the frequency of the clock component in each mode.

The operation of the part shown in the first figure will be explained below.

I) A clock obtained from a reproduction signal from a reproduction head of a VTR is input to an input terminal 101. Here, the above reproduced signal is usually a continuous signal reproduced by switching multiple heads in an I)-VTR, so before and after the head switching timing, there are parts containing signals other than the original data pattern. Therefore, the reproduced signal is discontinuous at that part.

Therefore, a signal synchronized with this head switching timing signal is input to the input terminal 110, and during a predetermined period before and after the head switching timing (a period including a signal other than the original pattern), the switch 112. Close 113. Accordingly, during this period, the data phase lock loop is cut and only the center frequency lock loop is effectively operated.

At this time, the reference frequency oscillation circuit 107 generates a clock signal of a frequency corresponding to the frequency of the clock component in the signal reproduced in each mode. This will be explained in detail later. The output of the reference frequency oscillation circuit 107 is V
The frequency and phase are compared with the clock S15, which is the output of the CO 105, by a frequency phase comparator (FPC) 108,
A comparison voltage Sll is generated. High frequency components of this comparison voltage Sll are cut by a loop filter 109 composed of a resistor and a capacitor, and an error voltage S13 is generated at the output.

At this time, since the data phase lock loop side is cut, the error voltage S13 is input as is to the VCO 105, and the center frequency of the VCO 105 is
It will be locked to the output frequency of the reference frequency oscillation circuit 107.

Note that the FPC was used to lock all ranges of the VCO 105. Here, the loop filter 109 is assumed to have a sample and hold function, and is designed to hold the output voltage while the switch 113 is off (open).

As a result, the center frequency of the VCO 105 continues to be locked near the clock frequency generated by the comparison frequency oscillation circuit 107 even while the data phase lock loop is operating. Note that the VCO 105 used here has a wide range around the standard clock frequency (the frequency of the clock component in the reproduced signal during standard reproduction).

Now, in the portion of the input playback signal that includes the original data pattern, excluding the period before and after head switching, switches 112 and 113 are opened to turn off the center frequency lock loop and enable only the data phase lock loop to operate effectively. . The clock in the reproduced signal input to the input terminal 101 is phase-compared with the clock 815, which is the output of the VCO 105, in the phase comparator 102, and a phase comparison voltage SIO is output. The phase comparison voltage SIO is the loop filter 1
03, high frequency components are cut, and an error voltage S12 is generated at the output of the loop filter 103. This error voltage S12 is added by the adder circuit 104 to the output error voltage S13 of the center frequency locked loop held as described above, and the reproduced clock S1 which is the output of the VCO 105 is added.
5 frequencies will be controlled. Here, the time constant in the loop filter 103 is set relatively large so as to narrow the lock range in order to obtain desired stability. At this time, the amplitude of the output error voltage S12 of the loop filter 103 becomes small, but as mentioned above, the output error voltage S13 of the center frequency locked loop is added, and the VCO 105
(7) Since the input signal is S14, it is possible to sufficiently cope with the change in clock frequency in each mode as described above.

These loop filters 103. 109, addition circuit 1
04, VCO 105 constitutes a controlled oscillation circuit of the present invention. The switch 111 in the loop filter 103 is used to slightly widen the lock range during lock-in so as to quickly lock-in, and after lock-in, narrow the lock range to achieve high stability.

Next, the configuration of comparison frequency oscillation circuit 109 will be explained.

FIG. 2 is a diagram showing a specific example of the configuration of the reference frequency oscillation circuit 107 in FIG. 1. The input terminal 201 contains data indicating each mode during playback, for example, normal playback.

Data indicating modes such as fast forward playback and reverse playback is input. Data indicating this mode is supplied to the data conversion table 202, and the frequency division ratio of the frequency divider 203 is set according to the data output from the data conversion table 202. In this way, the output of the VCO 207 is divided by the frequency divider 203 according to the division ratio N set according to the mode, and the horizontal synchronization signal fH in the reproduced signal inputted to the input terminal 204 as a reference signal and the phase comparator 205 The phase is compared. Accordingly, the phase comparator 205 outputs a phase comparison voltage S
Outputs 20.

High frequency components of the phase comparison voltage S20 are cut by the loop filter 206, and an error voltage S21 is generated at the output of the loop filter 206.

The frequency of the clock 323, which is the output of the VCO 207, is controlled by this error voltage S21. As a result, a reference clock having a frequency corresponding to each mode is outputted to the output terminal 208. This reference clock will be supplied to the FPC 108 in FIG. 11.1.

According to the PLL circuit configured as described above, a stable lock signal is outputted from the output terminal 106 in FIG. 1 at a frequency corresponding to each mode and in phase synchronization with the clock component in the reproduced signal.

In the above embodiment, the controlled oscillation circuit has a configuration in which a loop filter for the data phase locked loop and a loop filter for the center frequency locked loop are separately provided, but the output of the PC 102 and the output of the FPC 108 are added. It is also possible to configure the signal to be supplied to VC0105 through a post-loop filter.

In addition, the center frequency of the VCO 105 is increased, and the output clock to the terminal 106 or the FPC 108 is output via a frequency divider.
, it is also possible to form an input clock to the PC 102.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to set a wide range of lockable input clock frequencies and to obtain a PLL circuit with high stability.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a PLL circuit as an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of the reference frequency oscillator in FIG. 1, and FIG. 3 is a conventional PLL circuit. It is a figure showing an example of composition. In the figure, 101 is a clock input terminal, 102 is a phase comparator,
103. 109 is a loop filter, 104 is an addition circuit, 105 is a voltage controlled oscillator, 106 is an output terminal, 107
is a reference frequency oscillator, 10B is a frequency phase comparator, 20
2 is a data conversion table, 203 is a frequency divider, 204 is a reference signal input terminal, 205 is a phase comparator, 206 is a loop filter, and 207 is a voltage controlled oscillator.

Claims (3)

[Claims] (1) A PLL circuit that generates a clock that is phase-synchronized with an input clock, including a phase comparator that uses the input clock as one input, a reference oscillation circuit, and one input that uses the output of the reference oscillation circuit. a frequency phase comparator; controlled based on the outputs of the phase comparator and the frequency phase comparator;
A PLL circuit comprising a controlled oscillation circuit that provides the other input of the phase comparator and the frequency phase comparator. (2) The reference oscillation circuit includes a controlled oscillator, a frequency divider that divides the output of the controlled oscillator, a frequency division ratio setting circuit that can switch the division ratio of the frequency divider, and the frequency divider. a phase comparator that compares the phase of the output of the controlled oscillator with a reference signal, and a loop filter that removes a high frequency component of the output of the phase comparator and supplies it to the controlled oscillator. The PLL circuit according to claim 1, wherein the PLL circuit is supplied to a device. (3) The controlled oscillation circuit includes a first loop filter that removes a high frequency component of the output of the phase comparator, a second loop filter that removes the high frequency component of the output of the frequency phase comparator, and a second loop filter that removes the high frequency component of the output of the frequency phase comparator. 1. Claim (1) or (2) comprising an adder circuit that adds the outputs of the second loop filter, and a voltage controlled oscillator that is controlled by the output of the adder circuit. PLL circuit described in ).