JPH08147898A - Pll - Google Patents

Abstract

PURPOSE: To keep the output of PLL at a constant frequency. CONSTITUTION: A clock signal CLK is supplied from an input terminal to a PLD. The PLD is consisting of a timing generating circuit and a switch and a control signal S2 is supplied from the timing generating circuit to which the clock signal CKL is supplied to the switch. The switch outputs an input signal S1 or the output signal S4 of a PLL 6 as an output signal S3 based on the control signal S2. The phase difference between the output signal S3 of the switch and the output of a voltage controlled oscillator 9 is detected in a phase comparator 7 and a voltage corresponding to the phase difference is supplied to a low-pass filter 8. Then, the component of a high frequency range is eliminated in the low-pass filter 8 and the output signal S4 of the PLL 6 is outputted in the voltage controlled oscillator 9 and also is supplied to the switch of the PLD via a frequency divider 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to use the output signal before change even after the input signal is converted by locking the output signal of the PLL which is converted based on the input signal. Regarding

[0002]

2. Description of the Related Art Conventionally, in a helical scan type recording / reproducing apparatus, control of PLL (Phase Locked Loop) or the like suppresses drum rotation and tape speed fluctuation as much as possible during recording, so that servo can be easily applied during reproduction, and a signal can be applied. Reduce the fluctuation of the time axis of. In particular, when the signal tracks are not continuous in time, the PLL is applied to the drum rotation (head) by the vertical synchronizing signal of the input signal, and one frame corresponds to one rotation of the drum, that is, the switching position in the recording screen. Not to move. This switching position adjusts the PG phase to the PLL phase comparison so that during playback, the A and B track signals can be switched before the leading edge of the vertical sync signal. in short,
The vertical synchronizing signal VS of the recording signal is set to be the same as that of the standard tape when the writing of the track is started.

During playback, the PLL stabilizes the drum rotation and tape speed (same as during recording).
It suppresses fluctuations in signal time axis (jitter) and stabilizes the screen. In the case of VTR, CTL (tape phase) and PG (head phase) are phase-locked with each other by PLL so that the head traces the same track as when recording.

Here, an example of a conventional PLL is shown in FIG. The input signal S11 is supplied from the input terminal 51, and the supplied input signal S11 is supplied to the phase comparator 52. The phase comparator 52 outputs a voltage corresponding to the phase difference between the signal S12 supplied from the voltage controlled oscillator 54 and the input signal 51. The voltage is integrated in the low-pass filter 53 to remove high frequency components in the voltage. A signal S12 is output from the voltage controlled oscillator 54 based on the voltage from which the high frequency component has been removed, and the signal S12 is output.
Is taken out from the frequency divider 55 and the output terminal 56 as a signal having a cycle twice that of the input signal S11.
The frequency divider 55 halves the supplied signal and supplies it to the phase comparator 52. The frequency divider 55 may be provided as needed.

Input signal S11 and output signal S1 at this time
An example of the timing chart of No. 2 is shown in FIG. This Figure 6
As shown in, the input of the signal S11 is started at time t0, and the input of the signal S11 is ended at time t1. When the input signal S11 is supplied, the output signal S12 of the voltage controlled oscillator 54, which has been oscillating regardless of the input, is compared with the input signal S11 by the phase comparator 52, and a signal close to the frequency of the input signal S11 is obtained. Output.
This phase comparison is repeated, and when both signals have the same phase, the phase lock is completed and a signal having the same frequency as the input signal S11 is output.

However, after the time t1, the input signal S
11 ends, the output signal S1 of the voltage controlled oscillator 54 is output.
2 oscillates independently of the input signal S11 and outputs the output signal S11.
The frequency of the voltage-controlled oscillator 54 changes after the time t1 of twelve. At this time, the output signal S after the time t1
The reason why 12 does not change rapidly is that the low-pass filter 53 has a function of keeping the signal for a short time. That is, when the input signal S11 changes, the output signal S12 also changes according to the input signal S11, so that the voltage controlled oscillator 54 cannot maintain the signal before the change of the input signal.

Here, a tracking servo system previously proposed will be briefly described as an example of an apparatus to which the present invention can be applied. The traveling servo head Hs shown in FIG.
Recording is performed in the area PS of 1. Next, the servo head H
The recorded pilot signal is reproduced by the recording head Hw following s. The waveform of this pilot signal during reproduction is shown in FIG. 7B. P this reproduced pilot signal
The same signal as the pilot signal formed by the PLL is supplied to the LL and is recorded in the area SS of the section T2 as the tracking servo signal by the recording head Hw. That is, by supplying the pilot signal reproduced by the recording head Hw to the phase comparator 52 as the input signal S11, the same signal can be recorded in the area SS of the section T2. At this time, the azimuth of the servo head Hs and the azimuth of the recording head Hw are at different angles.

In FIG. 8A, the area P of the pilot signal is shown.
When the three reproducing heads are located at the track positions indicated by the reproducing heads 61, 62, and 63 with respect to S and the area SS of the tracking servo signal, these reproducing heads 6
Assuming that P0 is a temporal reference position when 1, 62 and 63 pass on the track, the reproducing head 62 becomes a just track and the tracking servo signal shown in FIG. 8C is obtained. The reproducing head 62 reproduces the tracking servo signal reproduced by the reproducing head 61.
The tracking servo signal shown in FIG. 8B reproduced by means of the lead phase has a lead phase, and the tracking servo signal reproduced by the reproducing head 63 shown in FIG. 8D has a delay phase. At this time, the azimuth of the recording head Hw and the azimuth of the reproducing heads 61, 62, 63 are at the same angle. The tracking device can be detected from such a phase relationship of the tracking servo signal.

[0009]

However, since the input signal S11 is directly input to the PLL as shown in FIG. 6, when the input signal S11 disappears on the way, it oscillates regardless of the input signal S11. , Output signal S12
Could not maintain the frequency before the input signal S11 disappeared. Further, when the frequency changes from a certain time, the frequency of the output signal S12 also changes following the change of the input signal S11 due to the property of the PLL, and thus the output signal S12 changes the input signal S11. I was unable to maintain the previous frequency. In the example shown in FIG. 7, the same signal as the pilot signal is recorded in the area SS, but the input signal to the PLL is supplied only during the period in which the area PS is reproduced. Therefore, it is difficult to record the same signal as the pilot signal in the area SS.

Therefore, an object of the present invention is to provide a PLL capable of maintaining an output signal before change even if the input signal changes, by locking the output signal for the input signal once.

[0011]

SUMMARY OF THE INVENTION The present invention is a PLL comprising a phase comparator, a low pass filter and a voltage controlled oscillator.
, A switch means for selectively supplying the input signal and the output signal of the voltage controlled oscillator or its frequency-divided output to the phase comparator, and a control signal for switching the switch means when the input signal changes are generated. And a timing generation means for performing the PLL.

[0012]

By using the PLL according to the present invention, the frequency before the change can be used even after the change of the input signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the PLL according to the present invention will be described below. FIG. 1 is a block diagram showing a first embodiment of a PLL according to the present invention. From the input terminal 1
A clock signal CLK that serves as a reference for LL is supplied. As the clock signal CLK, for example, a clock signal synchronized with a switching pulse formed from a PG (Palse Generator) of the rotary head type VTR is used. In the following description, it is assumed that the input signal S1 to the PLL 6 is supplied only during a predetermined period during head rotation synchronization, as in the tracking servo of the rotary head type VTR.

The clock signal CLK is PLD (Programa
ble Logic Device) 3. The PLD 3 performs time management and switching operation, and includes a timing generation circuit 4 and a switch 5. In the timing generation circuit 4, time control is performed by the supplied clock signal CLK, and a control signal S2 for switching is generated in response to a period in which the input signal S1 to the PLL 6 is supplied and a period in which it is not. To be done. In the switch 5, the input signal S1 supplied from the input terminal 2 is supplied to one terminal of the switch 5, and the output signal S4 is supplied from the PLL 6 to the other terminal of the switch 5.

When the control signal S2 supplied from the timing generation circuit 4 is "L", the input signal S is supplied from the switch 5.
1 is supplied as the signal S3 to the phase comparator 7 of the PLL 6, and when the control signal S2 is "H", the output signal S4 from the switch 5 is supplied as the signal S3 to the PLL 6 phase comparator 7. This PLL 6 is composed of a phase comparator 7, a low-pass filter 8, a voltage controlled oscillator 9 and a frequency divider 10, and a signal S3 selected by the switch 5 of the PLD 3 is provided.
Are supplied to the phase comparator 7. The frequency divider 10 may be provided as needed.

An example of the timing chart of this PLL is shown in FIG. The input signal S1 starts to be input at time t0 and ends at time t1, that is, "L".
Becomes Here, the time t1 is the time when the phase lock of the PLL is sufficiently completed. The control signal S2 is a switching signal supplied from the timing generation circuit 4 to the switch 5, and becomes "L" when the input signal S1 exists,
It becomes "H" when the input signal S1 becomes "L". That is, the control signal S2 becomes "L" at time t0 and becomes "H" at time t1. The signal S3 is a signal selected by the PLD 3 and is supplied to the phase comparator 7. Output signal S4
Is an output signal of the PLL according to the present invention, and is time t0
After a free run for a predetermined time from, the frequency is locked based on the signal S3 selected by the PLD3, and the input signal S1
This lock state is maintained even after the break.

A second embodiment of the present invention is shown in FIG. In the above-described first embodiment, the time management and the switching operation are performed by one PLD, but in this embodiment, the time management is performed by the PLD and the switching operation is performed by the analog switch. The clock signal CLK is supplied via the input terminal 21 to the timing generation circuit 23 including a PLD. The timing generation circuit 23 generates a control signal for the switch circuit 24, which is an analog switch, and supplies the control signal to the switch circuit 24. In the switch circuit 24, the input signal supplied from the input terminal 22 and the output signal S4 of the PLL 6 are selected by the control signal and are supplied to the phase comparator 7.

A third embodiment of the present invention is shown in FIG. The clock signal CLK is supplied to the timing generation circuit 32 via the input terminal 31, and the timing generation circuit 32 supplies the voltage hold circuit 35 with the control signal for switching the switch. In the phase comparator 34, the input signal supplied from the input terminal 33 and the output signal of the voltage controlled oscillator 38 are supplied via the frequency divider 39, and a voltage corresponding to the phase difference is output. The output voltage is
It is supplied to the voltage hold circuit 35.

The voltage hold circuit 35 comprises a switch, a resistor R, a capacitor C and a buffer amplifier, and the output voltage of the phase comparator 34 is supplied to one terminal of the switch. This switch is switched by a control signal from the timing generation circuit 32 when there is no input signal. When the switch is switched, the voltage is supplied from the buffer amplifier through the other terminal for a predetermined time determined by the resistor R and the capacitor C. The voltage is supplied from the voltage hold circuit 35 to the low-pass filter 36, and the low-pass filter 36 removes the high frequency components in the supplied voltage. The voltage from which the high frequency component has been removed is supplied to the voltage controlled oscillator 38 via the buffer 37,
A signal of a frequency output from the voltage controlled oscillator 38 based on the supplied voltage is taken out from the output terminal 40.

In the circuit configuration of the third embodiment, when the input signal disappears, the control signal of the timing generation circuit 32 switches the switch of the voltage hold circuit 35,
The voltage before the input signal disappears is supplied from the buffer amplifier. The time for which this voltage is supplied is determined by the resistor R and the capacitor C of the voltage hold circuit 35. That is, when the input signal disappears, the frequency is output for the time determined by the resistor R and the capacitor C.

[0021]

According to the present invention, when the input signal disappears on the way, the input signal can be continuously output by providing a switch for selecting either the input signal or the PLL output on the way. .

Further, according to the present invention, when the input signal does not disappear but is present but the input signal changes in the middle, or when the input signal before the change is required, the input signal is similarly changed to the PLL. By switching to the output signal, the signal before change can be continuously output independently of the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL of the present invention.

FIG. 2 is a timing chart showing an example of signal changes of the PLL of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the PLL of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the PLL of the present invention.

FIG. 5 is a block diagram showing an example of a conventional PLL.

FIG. 6 is a timing chart showing an example of signal change of a conventional PLL.

FIG. 7 is a schematic diagram used to describe a pilot signal and a tracking servo signal.

FIG. 8 is a schematic diagram showing a relationship between a tracking servo signal and a reproducing head.

[Explanation of symbols]

 3 PLD 4 Timing generation circuit 5 Switch 6 PLL 7 Phase comparator 8 Low pass filter 9 Voltage controlled oscillator

Claims (4)

[Claims] 1. A PLL comprising a phase comparator, a low-pass filter and a voltage controlled oscillator, and a switch for selectively supplying an input signal and an output signal of the voltage controlled oscillator or a frequency-divided output thereof to the phase comparator. A PLL comprising: means and timing generation means for generating a control signal for switching the switch means when the input signal changes. 2. The PLL according to claim 1, wherein a voltage hold circuit is provided between the phase comparator of the PLL and the voltage controlled oscillator. 3. The PL according to claim 1 and claim 2.
In L, the timing generation means switches the switching means to generate the control signal when the input signal disappears. 4. The P according to claim 1 and claim 2.
In the LL, the timing generation means switches the switching means to generate the control signal when the frequency of the input signal significantly changes.