JPH0530478A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To always obtain a stable clock at the time when a video signal cannot be obtained and the video signal is restored. CONSTITUTION:The phase of the synchronizing signal in an input video signal and that of a feedback clock are compared with each other by a phase comparing means (second phase comparing circuit) 5 of a phase synchronizing circuit 3, and the output of this phase comparing means 5 is held at a certain value by a holding means (sampling and holding circuit) 12 at the time of drop-out, and the feedback clock is synchronized with the synchronizing signal by control means (an input signal detecting circuit 13 and a counter control circuit 14) at the time of restoration from drop-out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for generating a clock of a predetermined frequency that follows an input video signal in a video signal recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art Conventionally, a digital TBC (Time base co) has been used as a device for removing the jitter (Jitter: fluctuation without cohesion) included in the input video signal as described above.
A time base correction circuit called a rrector (time base collector) is known.

For example, a clock generating circuit generates a clock that follows a jitter contained in an input video signal, and the input video signal is sampled by this clock to write digital data into a memory circuit. Again, the data is read from the memory circuit at a stable and constant clock and converted into an analog signal to obtain an input video signal containing no jitter.

Here, the configuration of a conventional clock generation circuit is shown in FIG.

In the figure, 1 is an input terminal, and this input terminal 1
When a video signal containing jitter is input to the sync signal separation circuit 2, the horizontal sync signal and the burst signal included in the video signal are separated by the sync signal separation circuit 2, and the horizontal sync signal is phase-synchronized. Circuit (PLL: Phase lock
ed loop) 3 and the burst signal is input to the first phase comparison circuit 4.

The phase synchronizing circuit 3 includes a second phase comparing circuit (phase comparing means) 5 for comparing the phase of a feedback clock, which will be described later, with the horizontal synchronizing signal, a loop filter 6 for determining a response speed, and a second phase. An oscillator (VCO: Voltage controll) whose oscillation frequency is controlled according to the output of the comparison circuit 5
ed oscillator: voltage controlled oscillator 7 and an N frequency dividing counter 8 for generating a feedback clock whose frequency is equal to that of the horizontal synchronizing signal by using the clock, and is the same as the burst signal phase-locked to the horizontal synchronizing signal. Generates a clock of frequency.

The phase difference between the clock generated by the phase synchronization circuit 3 and the burst signal (however, 1
(± 180 ° within a cycle) is detected by the first phase comparison circuit 4, the phase of the clock is shifted by the phase shift circuit 9 by the phase difference, and the phase with the burst signal is matched. By generating a clock synchronized with the burst signal required for the D / D conversion, that is, a clock required for sampling the video signal, a clock that follows the jitter included in the video signal is obtained from the output terminal 11.

The clock generated by the oscillator 7 is input to the N-divider counter 8 and divided by N,
It is input to the second phase comparison circuit 5 of the phase synchronization circuit 3.

[0009]

However, in the above-described conventional clock generation circuit, when the video signal input is temporarily cut off for some reason (for example, VTR: video tape recorder, laser disk, etc., is generated at the time of reproduction). (Eg dropout), the sync signal separation circuit 2 cannot output the sync signal, and the phase sync circuit 3 that generates a clock having the same frequency as the burst signal phase locked to the horizontal sync signal is disturbed.

Further, even when the video signal input is restored,
The internal counter value of the N frequency division counter 8 is not guaranteed, and it takes time for the phase synchronization circuit 3 to lock the phase.

Therefore, there is a drawback that the clock output becomes unstable when the input video signal is cut off and immediately after the input video signal is restored.

The present invention has been made in view of the above circumstances, and is always stable when a video signal cannot be obtained or the video signal is restored, such as a dropout that occurs during reproduction of a VTR. It is an object of the present invention to provide a clock generation circuit capable of obtaining a clock.

[0013]

In order to achieve the above-mentioned object, a clock generating circuit of the present invention is a clock generating circuit for generating a clock of a predetermined frequency that follows an input video signal. A phase synchronization circuit having a phase comparison means for comparing the phase of a synchronization signal with a feedback clock corresponding to the clock, a holding means for holding the output of the phase comparison means at a constant value, and the feedback clock as the synchronization signal. It is characterized by comprising a control means for synchronizing.

[0014]

The synchronizing signal in the input video signal and the feedback clock are phase-compared by the phase comparison means of the phase synchronization circuit, and at the time of dropout, the output of the phase comparison means is held at a constant value by the holding means and the dropout is restored. At the same time, the feedback clock is synchronized with the synchronization signal by the control means in synchronization with the operation of the holding means.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In this embodiment, the same components as those of the conventional clock generating circuit shown in FIG. 3 described above will be described with the same reference numerals in the drawings.

FIG. 1 is a block diagram of a clock generation circuit according to the present invention. This clock generation circuit is different from the conventional clock generation circuit shown in FIG. 3 in that it has a sample-and-hold (S / H) as a holding means. ) Circuit 12, input signal detection circuit 13 and counter control circuit 14 which are control means
And are added.

The sample and hold circuit 12 is
It is interposed between the second phase comparison circuit 5 of the phase synchronization circuit 3 and the loop filter 6. The sample-and-hold circuit 12 is controlled by the output signal from the input signal detection circuit 13, and the output of the second phase comparison circuit 5, that is,
Hold the control input of the oscillator 7 at a constant value,
It stabilizes the operation of.

The input signal detection circuit 13 is connected to the input terminal 1, and its output line is connected to the sample and hold circuit 12 and the counter control circuit 14, respectively. The input signal detection circuit 13 detects a loss of the horizontal synchronization signal included in the video signal input from the input terminal 1.

The counter control circuit 14 constitutes a control means for synchronizing the feedback clock with the horizontal synchronizing signal in synchronization with the operation of the sample and hold circuit 12 together with the input signal detecting circuit 13. This counter control circuit 1
Reference numeral 4 is connected to the output line of the sync signal separation circuit 2, and the output line of the counter control circuit 14 is connected to the N frequency division counter 8.

The counter control circuit 14 includes a horizontal sync signal from the sync signal separation circuit 2 and an input signal detection circuit 13.
A signal for controlling the N frequency division counter 8 is output when the horizontal synchronizing signal is restored by the detection signal from the.

Next, the operation of the clock generating circuit having the above configuration will be described with reference to FIGS. FIG. 2 is a timing chart showing the output timing of each signal in the clock generation circuit of the present invention.

First, when the video signal input from the input terminal 1 is lost due to dropout or the like, the horizontal synchronizing signal contained in this is in the state of (A) in FIG. The lack of the horizontal synchronizing signal (a) is detected by the input signal detecting circuit 13 in FIG. 1 to obtain the input signal detecting circuit output signal (c) in FIG.

This output signal (c) controls the sample-and-hold circuit 12 of FIG. 1 so that the normal operation value of the second phase comparison circuit 5 (normal error value before the loss of the horizontal synchronizing signal A) is obtained. The oscillator 7 is held to stabilize the operation of the oscillator 7 when the horizontal synchronizing signal is lost.

Further, the counter control circuit 14 controls the output timing of the N frequency dividing counter 8 in accordance with the horizontal synchronizing signal (a) and the input signal detecting circuit output signal (c) in FIG. The output signal (D) is output when the horizontal synchronization signal (A) is restored. This output signal (d) causes the N frequency division counter output signal (a) and the horizontal synchronizing signal (a) in FIG. 2 to have a constant phase when the horizontal synchronizing signal (a) is restored, as indicated by point A in FIG. Guaranteed to.

As a result, even if the output of the oscillator 7 slightly fluctuates when the horizontal synchronizing signal (a) is missing, the output signal (a) of the N frequency dividing counter 8 follows this fluctuation, so that the second phase The output of the comparison circuit 5 is the horizontal synchronization signal (a)
The phase-locked loop 3 can quickly lock the phase without abrupt change at the time of the recovery of, and a stable clock can be obtained.

In the above embodiment, the input signal detection circuit 13 detects the loss of the horizontal synchronizing signal based on the video signal input from the input terminal 1. However, in the case of VTR or the like, RF (Radio frequency) is used. : Of course, the same effect can be obtained even if it is obtained from a radio frequency signal.

[0028]

As described above, according to the present invention, a stable clock is always obtained when a video signal cannot be obtained or when the video signal is restored, such as a dropout that occurs during reproduction of a VTR. be able to.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a clock generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the output timing of each signal in the same circuit.

FIG. 3 is a block configuration diagram of a conventional clock generation circuit.

[Explanation of symbols]

5 phase comparison circuit (phase comparison means) 12 sample and hold (S / H) circuit (holding means) 13 input signal detection circuit (control means) 14 counter control circuit (control means)

Claims (2)

[Claims] 1. A clock generation circuit for generating a clock of a predetermined frequency following an input video signal, comprising phase comparison means for phase-comparing a synchronization signal in the input video signal and a feedback clock corresponding to the clock. A clock generation circuit comprising: a phase synchronization circuit having the same; holding means for holding the output of the phase comparison means at a constant value; and control means for synchronizing the feedback clock with the synchronization signal. 2. The holding means comprises a sample-and-hold circuit, and the sample-and-hold circuit operates according to a detection output for detecting a loss of the input video signal. The described clock generation circuit.