JPH05327491A - Frquency synthesizere - Google Patents

Abstract

PURPOSE:To suppress the spurious component included in the control voltage of a voltage control oscillator and to speed up the pull-in time, for example, concerning the frequency synthesizer to be used in performing, a mobile communication. CONSTITUTION:This frequency synthesizer is provided with a voltage regulating oscillator 2 transmitting the high frequency signal corresponding to an inputting control signal and a frequency divider/phase comparator section 1 comparing the phase between the frequency-divider signal obtained by dividing the frequency of the high frequency signal and the reference signal with the reference frequency to be applied, generating phase difference pulse having pulse width corresponding to the obtained phase difference and outputting them through a built-ion loop filter. It is provided with a spurious component suppression section 3 suppressing the spurious component included in the output of the frequency-divider/phase comparator section 1 to be transmitted as a control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for mobile communication, for example.

In recent years, digital mobile communication has become popular, but one method for making it available to more people is to increase the number of channels that a radio base station can use. Is.

However, when the number of channels increases, the frequency range in which transmission / reception is required becomes wider, and when switching from one channel to another, the pull-in time of the phase locked loop may become longer and the channel switching time may be delayed. ..

Therefore, it is necessary not to delay the pull-in time even if the number of channels increases.

[0005]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. In the figure, a voltage controlled oscillator (hereinafter abbreviated as VCO) 2 sends an oscillation output of frequency f _{VCO to} the outside as a high frequency signal and adds it to a prescaler 13.

Since the prescaler divides the frequency of the applied oscillation output by M (M is a positive integer) and sends it to the frequency divider 14,
The frequency divider further divides the frequency by N (N is a positive integer) and sends the oscillation output of frequency f _{V to} the phase comparator 11 as a frequency division output.

Since the reference signal of the reference frequency f _R is also applied to the phase comparator, the phases of the divided output and the reference signal are compared and a phase difference pulse having a pulse width corresponding to the phase difference is taken out. This pulse is frequency f _R
It becomes H level or L level depending on whether the phase of f _V is advanced or delayed.

Now, the phase difference pulse is a low-pass filter.
The DC voltage is smoothed via 12 (hereinafter abbreviated as LPF), and this DC voltage is used as the VCO control signal.
Added to.

Where VCO 2, prescaler 13, frequency divider
14, Phase comparator 11, LPF 12, VCO 2 form a phase-locked loop (hereinafter abbreviated as PLL), but since it is a negative feedback loop, the VCO oscillation frequency is controlled and f
_v = f _R.

Even when the oscillation output of the VCO is in synchronization with the reference signal of frequency f _R (even when the PLL is in lock), the phase comparator performs phase comparison at intervals of frequency f _R and The DC voltage is applied to the VCO as the VCO control signal as shown in Fig. 2, but since the spurious component (narrow pulse: beard) is superimposed on this DC voltage at the interval of frequency f _R , the FM component is included by this component. The VCO sends out a high frequency signal.

Therefore, the LPF that determines the pull-in time of the PLL
Although this spurious component is suppressed by 12, the spurious component becomes large when the pull-in time is short, and the pull-in time becomes long when the spurious component is small. Therefore, the LPF bandwidth had to be set so as to satisfy both the pull-in time and the requirements for spurious components.

[0012]

As described above, when the oscillation output of VCO becomes in synchronization with the reference signal of frequency f _V ,
The phase comparator generates a DC voltage corresponding to the phase difference and a spurious component at the reference frequency interval.
The VCO is frequency modulated.

Therefore, the LPF is designed to satisfy the requirements for the PLL pull-in time and spurious component suppression at the same time.
Since the bandwidth is set, there is a problem that there is a limit to satisfy both the shortening of the pull-in time and the suppression of spurious components.

An object of the present invention is to suppress spurious components contained in the control voltage of the voltage controlled oscillator and speed up the lead-in time.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 2 is a voltage controlled oscillator for sending out a high frequency signal having a frequency corresponding to an input control signal, and 1 is a divided signal obtained by dividing the high frequency signal and a reference signal having a reference frequency to be applied. It is a frequency division / phase comparison unit that compares phases and generates a phase difference pulse having a pulse width corresponding to the phase difference, and outputs the phase difference pulse via a built-in loop filter.

Reference numeral 3 is a spurious component suppressing unit that suppresses a spurious component contained in the output of the frequency dividing / phase comparing unit and sends it as the control signal.

[0017]

According to the present invention, the spurious component suppressing section is provided between the frequency dividing / phase comparing section and the voltage controlled oscillator.

As mentioned above, when the PLL is in the synchronous state,
The frequency dividing / phase comparing unit sends the DC voltage and the spurious component corresponding to the phase difference to the spurious component suppressing unit. The spurious component suppressor divides the DC voltage and the spurious component into two,
After inverting and inverting one, add it to the delayed one, and use the DC voltage containing the suppressed spurious component as the VCO control signal.
Apply to VCO.

As a result, since the spurious component is suppressed more than in the conventional example, it becomes possible to widen the LPF bandwidth by the amount of the suppression, and it is possible to shorten the lead-in time.

[0020]

2 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 4 is a block diagram of the logic inverting circuit in FIG.

Here, the symbols on the left side of FIG. 4 indicate the waveforms of the portions having the same symbols in FIG. Further, the phase comparator 11, the low-pass filter 12, the prescaler 13, and the frequency divider 14 are the components of the frequency division / phase comparison unit 1, and the logic inversion circuit 31, the delay circuit 32, and the addition circuit 33 are the spurious component suppression unit 3. Is a constituent part of.

The operation of FIG. 2 will be described below with reference to FIGS. 3 and 4. The parts described in detail above will be briefly described, and the part of the present invention will be described in detail. First, VCO 2 has frequency f
The oscillation output of the _VCO is output as a high frequency signal and is also applied to the prescaler 13. Since the prescaler divides the oscillation output by M and adds it to the divider 14, this divider 14
The frequency is _{divided and} the divided output of frequency f _v is sent to the phase comparator 11.

Since the reference signal of the frequency f _R is added to the phase comparator 11, the phase difference pulse of H level or L level is output from the phase comparator as shown in FIGS.
Send it to F12, and smooth the DC voltage obtained here.
The oscillation output of the VCO is synchronized with the reference signal by adding it as a control voltage to VCO 2 via the adder circuit 33 and the resistor R ₄ .

Now, when the synchronous state is established as described above, the LPF 12
Since the spurious component with the frequency f _R interval is superimposed on the DC voltage output by, the DC voltage on which the spurious component is superimposed is divided into two parts, some through the delay circuit 32, and the other part in FIG.
The phase is inverted by the logic inversion circuit using the operational amplifier 311 shown in FIG.

Therefore, the adder circuit 33 sends the DC voltage on which the suppressed spurious component is superimposed to the VCO via the resistor R ₄ as a VCO control signal (see FIGS. 4A and 4B). That is, after inverting the output waveform of the phase comparator by the logic inverting circuit, by adding the output waveform and the inverted waveform by the adding circuit,
A VCO control signal with suppressed spurious components is obtained.
Further, by suppressing the spurious component, the bandwidth of the LPF is widened by the amount of suppression, so that the lead-in time can be shortened.

[0026]

As described above in detail, according to the present invention, it is possible to suppress spurious components contained in the control voltage of the voltage controlled oscillator and speed up the lead-in time.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a logic inverting circuit in FIG.

FIG. 4 is an operation explanatory diagram of FIG. 2;

FIG. 5 is a configuration diagram of a conventional example.

[Explanation of symbols]

1 Frequency divider / phase comparator 2 Voltage controlled oscillator 3 Spurious component suppressor

Claims (1)

[Claims] 1. A voltage-controlled oscillator (2) for transmitting a high frequency signal having a frequency corresponding to an input control signal, and a reference signal having a frequency division signal obtained by dividing the high frequency signal and a reference frequency to be applied. In the frequency synthesizer that has a frequency division / phase comparison unit (1) that compares the phase of the phase difference pulse and the phase difference pulse with the pulse width corresponding to the phase difference and outputs it via the built-in loop filter. A frequency synthesizer characterized in that a spurious component suppression unit (3) for suppressing a spurious component contained in the output of the phase comparison unit and transmitting it as the control signal is provided.