JPH01154626A - Phase locked oscillation circuit - Google Patents

Phase locked oscillation circuit

Info

Publication number
JPH01154626A
JPH01154626A JP62312262A JP31226287A JPH01154626A JP H01154626 A JPH01154626 A JP H01154626A JP 62312262 A JP62312262 A JP 62312262A JP 31226287 A JP31226287 A JP 31226287A JP H01154626 A JPH01154626 A JP H01154626A
Authority
JP
Japan
Prior art keywords
phase
output
frequency
locked loop
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62312262A
Other languages
Japanese (ja)
Inventor
Minoru Hirata
実 平田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62312262A priority Critical patent/JPH01154626A/en
Publication of JPH01154626A publication Critical patent/JPH01154626A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain an output frequency other than a frequency being an integral number of multiple and to eliminate a spurious wave completely by mixing an output signal of a 1st phase locked loop obtained by a 1st reference signal with a 2nd reference signal at a mixer, giving it through a band pass filter, using it at a 2nd phase locked loop to obtain an output signal. CONSTITUTION:An output signal from a 1st voltage controlled oscillator 1 of the 1st phase locked loop L1 is an integral number of multiple of the 1st reference signal I in the phase comparator 3 and mixed by the 2nd reference signal II by a mixer 5 to obtain a signal of a desired frequency. The spurious wave generated in this case is attenuated to some degree by a band pass filter 6. The output signal is frequency-divided by a frequency divider 7 and fed to the 2nd phase locked loop L2 and it is phase-compared with a frequency division output by the frequency divider of the 2nd voltage controlled oscillator 8 at a phase comparator 10 and its output is fed back to the 2nd voltage controlled oscillator 8 through the amplifier 11. Thus, the spurious wave is eliminated to obtain a frequency other than the integral number of multiple.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は局部発振器等に用いられる位相同期発振回路に
関し、特に任意の周波数に設定でき、かつ不要波が混入
されることのない出力信号を得ることができる位相同期
発振回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked oscillation circuit used in a local oscillator, etc., and particularly to a phase-locked oscillation circuit that can be set to an arbitrary frequency and that produces an output signal that does not contain unnecessary waves. The present invention relates to a phase-locked oscillation circuit that can be obtained.

〔従来の技術〕[Conventional technology]

従来、電圧制御発振器を用いた位相同期発振回路として
、第2図に示す構成のものがある。即ち、電圧制御発振
器l9分周器21位相比較器3及び増幅器4で構成され
、電圧制御発振器1からの出力を分周器2において分周
し、この分周出力と基準信号Iとを位相比較器3にて位
相比較し、その比較出力を増幅器4を通じ電圧制御発振
器1に帰還することにより、位相同期ループを構成して
いる。
2. Description of the Related Art Conventionally, there is a phase synchronized oscillation circuit using a voltage controlled oscillator having a configuration shown in FIG. That is, it is composed of a voltage controlled oscillator 19, a frequency divider 21, a phase comparator 3, and an amplifier 4, and the output from the voltage controlled oscillator 1 is divided by the frequency divider 2, and the phase of this divided output and the reference signal I is compared. A phase locked loop is constructed by comparing the phases in the device 3 and feeding back the comparison output to the voltage controlled oscillator 1 through the amplifier 4.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の位相同期発振回路においては、電圧制御
発振器の分周出力と基準信号とを位相比較して得た比較
電圧を電圧制御発振器に帰還して位相同期発振器の出力
を得ているため、出力周波数は位相比較周波数の整数倍
のみの周波数となり、位相比較周波数の整数倍以外の出
力周波数は得ることができない。
In the conventional phase-locked oscillator circuit described above, the comparison voltage obtained by comparing the phases of the frequency-divided output of the voltage-controlled oscillator and the reference signal is fed back to the voltage-controlled oscillator to obtain the output of the phase-locked oscillator. The output frequency is only an integral multiple of the phase comparison frequency, and it is not possible to obtain an output frequency other than an integral multiple of the phase comparison frequency.

このため、整数倍以外の出力周波数を得るためにミキサ
を付設し、このミキサで基準信号と混合して得た信号を
帯域通過フィルタを通すことにより整数倍以外の出力周
波数を得る構成も提案されてはいるが、ミキサより発生
する不要波を完全には取り除くことができないという問
題がある。
For this reason, a configuration has also been proposed in which a mixer is attached to obtain an output frequency other than an integer multiple, and the signal mixed with a reference signal by this mixer is passed through a bandpass filter to obtain an output frequency other than an integer multiple. However, there is a problem in that the unnecessary waves generated by the mixer cannot be completely removed.

本発明は、整数倍以外の出力周波数を得ることができ、
しかも不要波を完全に除去することができる位相同期発
振回路を提供することを、目的としている。
The present invention can obtain an output frequency other than an integer multiple,
Moreover, it is an object of the present invention to provide a phase-locked oscillation circuit that can completely eliminate unnecessary waves.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の位相同期発振回路は、第1電圧制御発振器の出
力と第1基準信号とを位相比較して出力を得る第1位相
同期ループと、この第1位相同期ループの出力信号を第
2基準信号と混合するミキサと、このミキサに接続され
た帯域通過フィルタと、この帯域通過フィルタの通過出
力と第2電圧制御発振器の出力とを位相比較して出力を
得る第2位相同期ループとを有している。
The phase-locked oscillator circuit of the present invention includes a first phase-locked loop that obtains an output by comparing the phases of the output of the first voltage-controlled oscillator and a first reference signal, and a second phase-locked loop that uses the output signal of the first phase-locked loop as a second reference signal. It has a mixer for mixing with the signal, a bandpass filter connected to the mixer, and a second phase-locked loop that compares the phases of the passed output of the bandpass filter and the output of the second voltage-controlled oscillator to obtain an output. are doing.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

図において、第1電圧制御発振器1からの出力信号を分
周器2により分周し、その出力信号と第1基準信号Iと
を位相比較器3において位相比較し、その位相比較出力
を増幅器4を通じて電圧制御発振器1に帰還することに
より第1位相同期ループL1を構成している。この位相
同期動作から得られる第1電圧制御発振器1の出力信号
は、第2基準信号■とミキサ5により混合する。そして
、混合された信号は帯域通過フィルタ6を通して得たい
出力信号のみを取り出し、更に分周する。この分周信号
は、第2の電圧制御発振器89分周器9゜位相比較器1
0.増幅器11で構成される第2位相同期ループL2の
基準信号として用いられる。
In the figure, the output signal from the first voltage controlled oscillator 1 is frequency-divided by a frequency divider 2, the output signal and the first reference signal I are phase-compared in a phase comparator 3, and the phase comparison output is sent to an amplifier 4. The first phase-locked loop L1 is configured by feeding back to the voltage-controlled oscillator 1 through the voltage-controlled oscillator 1. The output signal of the first voltage controlled oscillator 1 obtained from this phase synchronization operation is mixed with the second reference signal 2 by the mixer 5. Then, the mixed signal is passed through a bandpass filter 6 to extract only the desired output signal and further frequency-divided. This frequency divided signal is sent to the second voltage controlled oscillator 89, frequency divider 9° phase comparator 1
0. It is used as a reference signal for the second phase-locked loop L2 composed of the amplifier 11.

この構成によれば、第1位相同期ループL1の第1電圧
制御発振器1からの出力信号は、位相比較器3における
第1基準信号■の整数倍となるが、その後にミキサ5に
おいて第2基準信号■と混合されることにより、得たい
周波数の信号を得ることができる。ところが、このとき
不要波が発生される。この不要波は帯域通過フィルタ6
によりある程度減衰されるが、完全に除去することは困
難である。
According to this configuration, the output signal from the first voltage-controlled oscillator 1 of the first phase-locked loop L1 becomes an integral multiple of the first reference signal ■ in the phase comparator 3, and then the second reference signal By mixing with the signal (2), a signal of the desired frequency can be obtained. However, at this time, unnecessary waves are generated. This unnecessary wave is filtered by the band pass filter 6.
Although it is attenuated to some extent, it is difficult to completely eliminate it.

このため、この出力信号を分周器7で分周した上で第2
位相同期ループL2に供給し、これを第2電圧制御発振
器8の分周器9による分周出力と位相比較器10におい
て位相比較し、その出力を増幅器11を通じて第2電圧
制御発振器8に帰還している。これにより、第2電圧制
御発振器8の出力周波数は不要波が除去され、かつ位相
比較器3の比較周波数の整数倍以外の周波数の出力信号
を得ることができる。
Therefore, after dividing this output signal by the frequency divider 7, the second
The phase-locked loop L2 is supplied to the phase-locked loop L2, and the phase is compared with the frequency-divided output from the frequency divider 9 of the second voltage-controlled oscillator 8 in the phase comparator 10, and the output is fed back to the second voltage-controlled oscillator 8 through the amplifier 11. ing. As a result, unnecessary waves are removed from the output frequency of the second voltage controlled oscillator 8, and an output signal having a frequency other than an integral multiple of the comparison frequency of the phase comparator 3 can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、第1基準信号を用いて得
た第1位相同期ループの出力信号を第2基準信号とミキ
サで混合し、これを帯域通過フィルタを通した上で第2
位相同期ループで位相比較して出力信号を得ているので
、各位相同期ループやその間における分周数、基準信号
周波数を任意に選ぶことにより、任意の周波数を得るこ
とができ、かつ第2位相同期ループの作用により帯域通
過フィルタでは減衰できない不要波をも完全に除去した
出力信号を得る効果がある。
As explained above, the present invention mixes the output signal of the first phase-locked loop obtained using the first reference signal with the second reference signal in a mixer, passes this through a bandpass filter, and then mixes the output signal of the first phase-locked loop obtained using the first reference signal.
Since the output signal is obtained by comparing the phases in the phase-locked loop, any frequency can be obtained by arbitrarily selecting each phase-locked loop, the frequency division number between them, and the reference signal frequency. The action of the locked loop has the effect of obtaining an output signal that completely eliminates unnecessary waves that cannot be attenuated by a bandpass filter.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の位相同期発振回路の一実施例のブロッ
ク図、第2図は従来の位相同期発振回路のブロック図で
ある。 ■・・・第1電圧制御発振器、2・・・分周器、3・・
・位相比較器、4・・・増幅器、5・・・ミキサ、6・
・・帯域通過フィルタ、7・・・分周器、8・・・第2
電圧制御発振器、9・・・分周器、10・・・位相比較
器、11・・・増幅器、Ll・・・第1位相同期ループ
、L2・・・第2位相同期ループ、■・・・第1基準信
号、■・・・第2基準信号。
FIG. 1 is a block diagram of an embodiment of the phase-locked oscillation circuit of the present invention, and FIG. 2 is a block diagram of a conventional phase-locked oscillation circuit. ■...First voltage controlled oscillator, 2...Frequency divider, 3...
・Phase comparator, 4... Amplifier, 5... Mixer, 6.
...bandpass filter, 7...frequency divider, 8...second
Voltage controlled oscillator, 9... Frequency divider, 10... Phase comparator, 11... Amplifier, Ll... First phase locked loop, L2... Second phase locked loop, ■... 1st reference signal, ■...2nd reference signal.

Claims (1)

【特許請求の範囲】[Claims] (1)第1電圧制御発振器の出力と第1基準信号とを位
相比較して出力を得る第1位相同期ループと、この第1
位相同期ループの出力信号を第2基準信号と混合するミ
キサと、このミキサに接続された帯域通過フィルタと、
この帯域通過フィルタの通過出力と第2電圧制御発振器
の出力とを位相比較して出力を得る第2位相同期ループ
とを備えることを特徴とする位相同期発振回路。
(1) A first phase-locked loop that obtains an output by comparing the phases of the output of the first voltage controlled oscillator and the first reference signal;
a mixer for mixing the output signal of the phase-locked loop with a second reference signal; a bandpass filter connected to the mixer;
A phase-locked oscillation circuit characterized by comprising a second phase-locked loop that compares the phases of the passed output of the band-pass filter and the output of the second voltage-controlled oscillator to obtain an output.
JP62312262A 1987-12-11 1987-12-11 Phase locked oscillation circuit Pending JPH01154626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62312262A JPH01154626A (en) 1987-12-11 1987-12-11 Phase locked oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62312262A JPH01154626A (en) 1987-12-11 1987-12-11 Phase locked oscillation circuit

Publications (1)

Publication Number Publication Date
JPH01154626A true JPH01154626A (en) 1989-06-16

Family

ID=18027122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62312262A Pending JPH01154626A (en) 1987-12-11 1987-12-11 Phase locked oscillation circuit

Country Status (1)

Country Link
JP (1) JPH01154626A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008135460A (en) * 2006-11-27 2008-06-12 Nichicon Corp Chip solid electrolytic capacitor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5484960A (en) * 1977-12-20 1979-07-06 Toyo Communication Equip Phase synchronizing digital frequency synthesizer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5484960A (en) * 1977-12-20 1979-07-06 Toyo Communication Equip Phase synchronizing digital frequency synthesizer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008135460A (en) * 2006-11-27 2008-06-12 Nichicon Corp Chip solid electrolytic capacitor

Similar Documents

Publication Publication Date Title
JPS60134633A (en) Controller for double conversion tuner
JPS62260429A (en) High-frequency synthesizer
US3202930A (en) Apparatus for frequency synthesis
JPH01154626A (en) Phase locked oscillation circuit
JPH0659031B2 (en) Phase locked oscillator
JPS6348997Y2 (en)
JPH08265046A (en) Frequency demultiplier
JP2848156B2 (en) Variable frequency high frequency oscillation circuit
JPS61216529A (en) Inductive radio frequency synthesizer device
JPS6238352Y2 (en)
SU794730A2 (en) Phase-lock loop
JPS62233953A (en) Jitter adding device
JPH01215124A (en) Sweep frequency generating circuit
JPS60197015A (en) Phase locked oscillator
JP3248453B2 (en) Oscillator
JPH0345936B2 (en)
JPS61163719A (en) Frequency synthesizing system
SU389608A1 (en) FREQUENCY SYNTHESIZER
JPS6336688B2 (en)
JPH0520431U (en) Oscillator
JPH0349320A (en) Frequency synthesizer
JPS6384320A (en) Microwave band frequency synthesizer
JPH01181307A (en) High frequency divider
JPS60241338A (en) Encoder and decoder
JPS62171228A (en) Digital pll circuit