JPH0453048Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a frequency synthesizer suitable for use as a signal source of a local oscillation signal in a radio device that needs to be miniaturized.

(Prior Art) Conventionally, a frequency synthesizer using a phase synchronization circuit is often used as an oscillation source of a local oscillation signal of a radio device that performs multi-channel switching or as an oscillation source of a transmission wave signal. In particular, when a frequency synthesizer is used as the oscillation source of the transmitted wave signal, a modulation signal is added to the voltage controlled oscillator, and the frequency synthesizer is used as a modulator, the modulation sensitivity changes depending on the oscillation frequency of the voltage controlled oscillator. There's a problem. To solve this problem, conventionally, an analog switch or the like is used to change the modulation level depending on the oscillation frequency.

FIG. 4 is a block diagram of a conventional device with the above-mentioned improvement, and FIG. 5 is a signal waveform diagram of each part of the conventional example shown in FIG.

A conventional example will be described below with reference to the drawings. Fourth
In the figure, the output of voltage controlled oscillator 4 is input to variable frequency divider 5. The output of variable frequency divider 5 is sent to comparator 2. This comparator 2 compares the output of the variable frequency divider 5 and the output of the oscillator 1, and outputs a signal voltage according to the phase difference between the two. The output of this comparator 2 passes through a loop filter 3 and is fed back to a voltage controlled oscillator 4.

The input terminal P1 is a terminal to which a data signal 22 is inputted, the input terminal P2 is a terminal to which a clock signal 23 is inputted, and the input terminal P3 is a terminal to which a strobe signal 24 is inputted. The variable frequency divider 5 includes a shift register and a data latch circuit, and each pulse forming the data signal 22 is shifted at the rising edge of the clock signal 23, and each pulse forming the data signal 22 is latched at the rising edge of the strobe signal 24. be done. The input terminal P4 is a terminal into which the modulated wave signal 21 is input, and the input terminals P5 and P6 are terminals into which control signals 26 and 27 for switching and controlling the signal level of the modulated wave signal 21 are input. Each control signal 26, 27 is a 2-bit parallel signal that switches the signal level of the modulated wave signal 21 in four stages.

FIG. 6 is a block diagram showing a conventional example often used in radio equipment capable of simultaneous transmission and reception, such as a car telephone. This configuration has separate synthesizers for the receiving station and for transmitting. The phase-locked circuit 30 is used for transmission, and the phase-locked circuit 31 is used for the reception station, and the operation of each phase-locked circuit is as described above. The two synthesizers share the reference frequency oscillator 1, the input terminal P2 for the clock signal 23, and the input terminal P3 for the strobe signal 24.

(Problems to be solved by the invention) As mentioned above, in the past, since the control signal for switching the modulation level was newly received from the control unit, the number of interfaces between the control unit and the frequency synthesizer unit, such as the number of connector terminals, was The disadvantage is that the number of control signals increases. For example, the control signal is 2 bits
If the signal was , the number of connector terminals would have increased by two. In addition, in general radio equipment, the radio section including the frequency synthesizer and the control section are often configured on separate panels, and as the number of interfaces increases, the connector becomes larger. For miniaturization, it is essential to reduce the number of interfaces by even one.

The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a frequency synthesizer that can reduce the size of a radio device.

(Means for Solving the Problems) The means provided by the present invention to solve the above-mentioned problems and achieve the above objectives include a voltage controlled oscillator whose oscillation frequency changes according to the input voltage, and a plurality of a variable frequency divider having a frequency division ratio specified by a data signal consisting of a pulse and a strobe signal input after the data signal, and dividing the output of the voltage controlled oscillator by the specified frequency division ratio; a phase synchronized circuit comprising a comparison means for comparing the output of the oscillator oscillating with the output of the variable frequency divider and outputting a signal voltage corresponding to the phase difference between the two to the voltage controlled oscillator; modulated signal output means for changing and outputting the signal level of the modulated signal according to a control signal input later; outputting the modulated signal of the modulated signal output means to the voltage controlled oscillator to output the modulated signal according to the modulated signal; The frequency synthesizer performs frequency modulation, and is characterized in that the signal line for the data signal and the signal line for the control signal are a common signal line.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is an oscillator, 2 is a comparator, 3 is a filter, 4 is a voltage controlled oscillator, 5 is a variable frequency divider, 10 is a switching circuit, and 30 is a phase locked circuit. The operation of each circuit section is similar to the conventional example shown in FIG.

Here, the data signal 22 input to the variable frequency divider 5
The control signal 27 input to the signal line and the switching circuit 10
The same signal line is used. Therefore, as is clear from a comparison between FIG. 1 and FIG.
Since only terminals 1, P2, P3, P4, and P5 are used, the total number of terminals can be reduced.

FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a signal waveform diagram of each part of the embodiment of FIG.

In the embodiment shown in FIG. 2, two phase locking circuits 30, 31 are provided, and each phase locking circuit 30, 31
Data signals 22, 25 and control signal 2 input to
7 and 26 are each made into a common signal line. That is, as shown in FIG. 2, the signal line for the data signal 22 and the control signal 27 is made a common signal line, and the signal line for the data signal 25 and the control signal 26 is made a common signal line. As a result, only five terminals P1, P2, P3, P4, and P7 are used, reducing the total number of terminals.

Next, the operation of the present invention will be explained with reference to FIG. The shift means built into the variable frequency divider 5 converts a plurality of data pulses 22 forming the data signal 22.
a, 22b, ... 22n are the respective clock pulses 23a, 23b, 23 of the corresponding clock signal 23.
c, . . . 23n. Similarly, in the shift means built in the variable frequency divider 9, a plurality of data pulses 25a, 2 forming the data signal 23 are
5b, . . . are sequentially shifted by each clock pulse 23a, 23b, 23c, . This data signal 22 and 25
is latched at the rising edge of the strobe signal 24. That is, it is designated as a predetermined channel. Therefore, the variable frequency dividers 5 and 9 are configured so that the corresponding data signal 2
2 and 25 are designated as respective frequency division ratios according to the data contents. Here, as shown in FIG. 3, each of the shift means receives control signals 26 and 27 after inputting the strobe signal 24, and each data signal 2
Since the data contents of 2 and 25 have been latched, the setting values of the frequency division ratios of the variable frequency dividers 5 and 9 are not changed. Therefore, the variable frequency dividers 5 and 9 do not have any trouble depending on the control signals 26 and 27.

Next, the switching circuit 10 side will be explained. In the switching circuit 10, the modulation level is switched using the data signals 22 and 25, but the level cannot be switched because the modulation wave is not needed until the aforementioned channel designation is completed and the synthesizer is locked. There will be no effect if it is done.

In addition, the pull-in operation of the synthesizer, in other words, ensures a stable output signal that is phase-locked to a predetermined frequency.
In order to obtain a stable signal, it is desirable to prohibit the input of the modulation signal 21 to the switching circuit 10 during the output timing period of each data signal 22, 25.

(Effects of the invention) As explained above, according to the invention, the control signal line of the modulation level switching circuit and the data signal line that specifies the frequency division number of the variable frequency divider are shared, and the number of interfaces, that is, the number of terminals is You can get a frequency synthesizer with less. By reducing the number of interfaces or terminals, the connector can be made smaller. Furthermore, if the number of output ports of the control section is limited, modulation level switching control can be performed without increasing the number of ICs (integrated circuits).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, FIG. 3 is a signal waveform diagram of each part of the embodiment shown in FIG. FIG. 4 is a block diagram showing a conventional example, FIG. 5 is a signal waveform diagram of each part of the conventional example shown in FIG. 4, and FIG. 6 is a block diagram showing another conventional example. 1... Reference frequency oscillator, 2, 6... Phase in-phase comparator, 3, 7... Loop filter, 4, 8... Voltage controlled oscillator, 5, 9... Variable frequency divider, 10...
Modulation level switching circuit, 21...modulation input terminal,
22, 25...Data signal input terminal, 23...Clock signal input terminal, 24...Strobe signal input terminal, 26, 27...Switching control signal input terminal, 30, 31...Phase synchronization circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A voltage controlled oscillator whose oscillation frequency changes according to the input voltage, a data signal consisting of a plurality of pulses, and a strobe signal input after the data signal with a frequency division ratio specified. and a variable frequency divider that divides the output of the voltage controlled oscillator by the specified frequency division ratio, and compares the output of the oscillator that oscillates at a predetermined frequency with the output of the variable frequency divider, depending on the phase difference between the two. and a comparison means for outputting a signal voltage to the voltage controlled oscillator; and a modulation signal output means for changing the signal level of the modulation signal according to a control signal input after the strobe signal and outputting the modulated signal. a frequency synthesizer that outputs a modulation signal of the modulation signal output means to the voltage controlled oscillator and performs frequency modulation in accordance with the modulation signal; a signal line for the data signal and a signal line for the control signal; A frequency synthesizer characterized by using a common signal line. (2) A plurality of the phase-locked circuits are provided, and a signal line for the data signal inputted to each phase-locked circuit and the control signal is a common signal line. Frequency synthesizer described in section.