JPS63194417A - Phase shifting circuit - Google Patents

Abstract

PURPOSE:To make the component of a circuit large in scale such as an arithmetic circuit unnecessary and to simplify the circuit, by selecting a data generated at a shift register corresponding to a phase difference, and delaying it with a delay means. CONSTITUTION:When a signal representing the delay of more than 45 deg. of the phase of an output signal is supplied to a first counter 14, a switching signal is supplied from the first counter 14 to a data selector so as to output the signal whose phase is led. And phase adjustment within 45 deg. is performed by a first-a fifth delay circuits 21-25 and a first-a fifth change-over switches 31-35. In other words, by performing the phase adjustment at every 45 deg. and fine phase adjustment within a range of 45 deg. by the data selector 15, a pulse signal having the same phase as that of a color burst signal obtained at an input terminal 11 is outputted from an output terminal 19. Also, since a shift circuit is constituted of a comparatively simple components such as a gate circuit, etc., and requires no components such as the arithmetic circuit, etc., it is possible to simplify circuit constitution.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Summary of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example G1. Structure of phase shift circuit G.2 Phase Shift operation by shift circuit 03 Effects of the circuit of this example H Effects of the invention A Field of industrial application The present invention relates to a phase shift circuit suitable for use in, for example, a phase control circuit of a color television receiver.

B. 1. Existing Summary of the Invention The present invention provides a phase shift circuit suitable for use in, for example, a phase control circuit of a color television receiver, which includes a shift register that creates a plurality of data based on an oscillation signal, an input signal, and an output. A phase difference detection means for detecting a phase difference with a signal, a selection means for selecting data to be output from the shift register according to a detection signal of the phase difference detection means, and a selection means according to a detection signal of the phase difference detection means. By providing a delay means for delaying the output signal of the circuit, the frequency of the oscillation signal required by the circuit can be lowered, and a phase shift circuit that outputs a pulse signal with a simple configuration that does not require large circuit components can be realized. It was made so that it could be obtained.

C. Prior Art Conventionally, as a phase control circuit for performing digital signal processing used in color television receivers, etc., for example, a fifth phase control circuit is used.
A digital PLL (needs-locked loop) circuit as shown in the figure has been proposed.

This digital PLL circuit supplies a pulse signal supplied to an input terminal (1) to one comparison signal input terminal of a phase comparator (2). This phase comparator (2) compares the phase difference between a pulse signal supplied to the other comparison signal input terminal from a frequency divider (4), which will be described later, and a pulse signal obtained at the input terminal (1). The signal is converted into a frequency switching gate circuit (3
). In this case, the phase comparator (2) is constituted by an exclusive OR (Ex OR) circuit. Then, the frequency switching gate circuit (3) converts the first frequency signal obtained at the terminal (3a) and the terminal (3b
) of a lower frequency than the first frequency signal obtained at
The frequency signal is switched and supplied to the frequency divider (4). And this frequency divider (4) is a frequency switching gate circuit (3)
The frequency of the signal supplied from the converter is divided by a predetermined number and is supplied to the phase comparator (2) and the output terminal (5).

With this configuration, for example, if a pulse signal as shown in FIG. 6A is obtained at the input terminal (1), and a pulse signal as shown in FIG. 6B is output from the frequency divider (4). , the phase comparator (2), which is an ExOR circuit, outputs a phase comparison signal (FIG. 6C) that becomes high level when only the pulse signal obtained at one of the comparison signal input terminals is high level. When this phase comparison signal is supplied to the frequency switching gate circuit (3), when this phase comparison signal is at a high level, the first frequency signal obtained at the terminal (3a) is supplied to the frequency divider (4). , when the phase comparison signal is at a low level, the second frequency signal obtained at the terminal (3b) is supplied to the frequency divider (4). For this reason, the frequency divider (4) uses the changes in the pulse signal as shown in FIG.
frequency signals are alternately supplied, and the frequency of the pulse signal obtained at the output terminal (5) is determined by the ratio of the time during which the first frequency signal is output and the time during which the second frequency signal is output.

With this configuration, a digital PLL circuit using pulse signals as input and output signals can be obtained.

D. Problem to be Solved by the Invention However, the digital PLL circuit as shown in FIG. 5 makes the first and second frequency signals several hundred times higher in frequency than the input signal obtained at the input terminal (1). Otherwise, a good output signal will not be output from the output terminal (5) and the frequency divider (
4) has the disadvantage that it requires a complex configuration with a high frequency division ratio.

Further, as shown in FIG. 7, a phase comparator (7) performs digital signal processing on the pulse signal obtained at the input terminal (6).
), the comparison signal of this phase comparator (7) is supplied to a digital voltage controlled oscillator (9) via a digital filter (8) that performs digital signal processing, and the output signal of this oscillator (9) is Comparator (7) and output terminal (1
0) so that each component of a normal PLL circuit can handle digital signals. However, even in this case, the digital voltage controlled oscillator (9) needs to have a complicated configuration including a multiplication circuit, resulting in the disadvantage that the circuit configuration becomes complicated.

In view of the above, an object of the present invention is to provide a phase shift circuit that can perform phase control with a simple configuration.

E. Means for Solving the Problems The phase shift circuit of the present invention has, for example, as shown in FIG.
A shift register (16) that creates a plurality of data based on an oscillation signal, and a phase difference detection means that detects a phase difference between an input signal obtained at the input terminal (11) and an output signal obtained at the output terminal (19). (12).

(13) and this phase difference detection means (12), (13
) selection means (15) for selecting data to be output from the shift register (6) in response to detection signals from the phase difference detection means (12) and (13); Delay means (21) to (21) for delaying the output signal
25) and (31) to (35) are provided.

F Function The phase shift circuit of the present invention is a shift register (16)
The selection means (14) selects the data created in accordance with the phase difference, and the delay means (21) to (25).

It can be configured by simply delaying steps (31) to (35), resulting in a simple configuration that does not require large circuit components such as an arithmetic circuit.

G Example Hereinafter, an example of the phase shift circuit of the present invention will be described in Figs.
Let's explain with reference to FIG.

Configuration of Gr phase shift circuit FIG. 1 is a block diagram showing the phase shift circuit of this example.

The phase shift circuit shown in FIG. 1 is a circuit built into a television receiver, and (11) in the figure indicates an input terminal.
This input terminal (11) is a terminal to which a color burst signal of the video signal is supplied, and the color burst signal obtained at this input terminal (11) is passed to the first and second phase comparators (1
2) and (13). The first and second phase comparators (12) and (13) detect the phase difference between this input color burst signal and an output signal obtained at an output terminal (19), which will be described later. The phase difference detection signal detected by the comparator (12) is supplied to the tenth counter (14) every horizontal scanning period <l11). The phase difference detection signal supplied to the first counter (14) is a signal indicating whether the phase is ahead or behind by a predetermined value, for example, 45°, and when a phase lead or lag of 45° or more is detected. , supplies a switching signal to the data selector (15). This data selector (15) is configured to be supplied with a bit signal from a linear feedback shift register (16), and this linear feedback shift register (1G) creates a bit signal using an oscillation signal from an oscillator (17). That's how it is. That is, the oscillator (17) outputs a fixed frequency signal approximately 8 times the burst signal obtained at the input terminal (1), and the oscillation signal of this oscillator (17) is transferred to the linear feedback shift register (16). supply to. In the case of this example, the linear feedback shift register (16) is composed of four (4) D flip-flops (16d), and each flip-flop (1
The 2-pin signal outputted by 6a) to 16d is directly supplied to the data signal input terminal of the data selector (15) for a total of 8 bits. With this configuration, the bit signal supplied to the data selector (15) changes periodically in the following order in conjunction with the oscillation signal of the oscillator (17).

00001111-...-A 00011110--B 00111100--- C 01111000---D 11110000----E 11100001------F llooooll--m---・G 1 0 0 0 0 1 1 1 -------
---H Figure 3A-
A state as shown in H is reached, and the rising and falling edges of the pulse signal shift sequentially at equal intervals.

Further, when the shift amount of the pulse signal is expressed in terms of angle, as shown by arrows A-H in FIG. 4, the pulse signal is sequentially shifted by 45 degrees.

The data selector (15) is a circuit that selects one of the supplied signals, converts it into a serial signal, and outputs it as shown in FIG. 3, and a switching signal is supplied from the first counter (14). The signals to be output are sequentially switched. The data selector (15) outputs the first and second signals.

Third, fourth and fifth delay circuits (21), (22)
, (23).

(24) and (25) and the first, second, third, fourth and fifth changeover switches (31), (32), (33)
), (34) and (35) are supplied to the output terminal (19) through a combined circuit.

That is, the output terminals of the data selector (15) are the first, second, . Third. fourth and fifth changeover switches (31),
(32), (33), (34) and (35) first fixed contacts (31a), (32a),
(33a), (34a), and (35a) and are connected to the input side of the first delay circuit (21).

Then, the output side of the first delay circuit (21) is connected to the second fixed contact (31b) of the first changeover switch (31), and the movable contact (31c) of the first changeover switch (31) is connected to the second fixed contact (31b) of the first changeover switch (31).
) is connected to the second fixed contact (32b) of the second changeover switch (32) via the second delay circuit (22), and the movable contact (32c) of this second changeover switch (32) is connected to the second fixed contact (32b) of the second changeover switch (32). The third changeover switch (3) is connected via the third delay circuit (23).
3), and the movable contact (33c) of this third changeover switch (33) is connected to the fourth changeover switch (34) via the fourth delay circuit (24). The movable contact (34c) of the fourth changeover switch (34) is connected to the second fixed contact (34b) of the fourth changeover switch (34) through the fifth delay circuit (25). Connect to the No. 2 fixed contact (35b). Then, the movable contact (35c) of this fifth changeover switch (35) is connected to the output terminal (
19) and first and second phase comparators (12) and (13)
).

The first to fifth delay circuits (21) configured in this way
(25) and the first to fifth changeover switches (31) to (35
) is constituted by a gate circuit as shown in FIG. 2 in this example. This FIG. 2 is a diagram showing a specific configuration of the first delay circuit (21) and the first changeover switch (31), which correspond to part a in FIG. 1, and (41) in the figure will be described later. The switch switching signal input terminal (42) is the data selector (
15) and shows the output signal input terminals of the respective input terminals (4).
1) and (42) to inverter circuits (43) and (44)
) to the input side of the NAND circuit (45).

Connect directly to the input side of the NAND circuit (46). In this case, a plurality of inverter circuits (44) (an even number) are connected in series to obtain a predetermined delay time.

Then, the output sides of the NAND circuits (45) and (46) are connected to the input side of the NAND circuit (47), and the NAND circuits (45) and (46) are connected to the input side of the NAND circuit (47).
The output side of the AND circuit (47) is connected to the first changeover switch (
The output terminal (4) corresponds to the movable contact (31c) of
8). By configuring it in this way,
First delay circuit (21) and first changeover switch (31)
are configured by gate circuits, second to fifth delay circuits (22) to (25) and second to fifth changeover switches (32).
) to (35) are similarly constructed of gate circuits.

The second phase comparator (13) has an input terminal (11
) and the input color burst signal obtained at the output terminal (19
) are compared, and a phase difference detection signal indicating whether the phase is ahead or behind is supplied to the second counter (18). In this case, the second phase comparator (13) detects a finer phase difference than the first phase comparator (12). Then, the second counter (1
8) sequentially supplies a switching signal to the first to fifth changeover switches (31) to (35) every horizontal scanning period by supplying the phase difference detection signal.

02 Shift Operation by Phase Shift Circuit The phase shift circuit of this example is constructed as described above, and its operation will be explained below.

First, when a color burst signal of a video signal is supplied to the input terminal (11), this color burst signal is supplied to the first and second phase comparators (12) and (13). ), (13) connects the output terminal (19
) is compared with the phase difference, and phase difference detection signals are supplied from the respective phase comparators (12) and (13) to the first and twentieth counters (14) and (18). When a detection signal indicating a phase lead or lag of 45 degrees or more is supplied to the first counter (14), the output of the signal supplied from the linear feedback shift register (16) is sent to the data selector (15). , the output will advance one unit at a time or be delayed. That is, the data selector (1
5) The signal output from the linear feedback shift register (
45 as shown in Figure 3A-)1 based on the signal from 16).
For example, in a state where one of the pulse signals whose phase is shifted by ° is selected, for example, Fig. 3A (the phase is indicated by arrow A in Fig. 4)
Assume that a pulse signal as shown in is output. At this time, if the first counter (14) is supplied with a signal indicating a delay in the output signal phase by 45° or more, the first counter (14) outputs a signal whose phase is advanced to the data selector (15). A switching signal is supplied so that the Therefore, a pulse signal as shown in FIG. 3H, which is <45 degrees in phase as shown in FIG. 4, is output from the data selector (15).

Even in this state, if there is a phase delay, when the detection signal is supplied, the pulse signal shown in Fig. 3G, the pulse signal shown in Fig. 3H, etc. will proceed in this order, but if the delay is within 45 degrees, then , the data selector (15) continues to output the pulse signal shown in FIG. 3H.

Phase adjustment within 45 degrees is achieved by using the first to fifth delay circuits (21) to (25) and the first to fifth changeover switches (3).
1) to (35). For example, if the movable contact (35c) of the fifth changeover switch (35) is now connected to the first fixed contact (35a), the output signal from the data selector (15) is not delayed at all and is output directly to the output terminal. (19) is output. In this state, when the second phase comparator (13) detects no phase lead or lag, this state is defined as a state in which the phase matches the input signal, and a pulse signal of this phase is output from the output terminal (19). .

When the movable contact (35c) of the fifth changeover switch (35) is connected to the first fixed contact (35a) and the second phase comparator (13) detects a phase shift, , a switching signal is supplied from the second counter (18) to the fifth switch (35), and the movable contact (35c)
is connected to the second fixed contact (35b). In addition, at this time, the first to fourth changeover switches (31) to (3
It is assumed that the movable contacts (31c) to (34c) of 4) are connected to the first fixed contacts (31a) to (34a). By doing this, the output signal of the data selector (15) is sent to the output terminal (19) via the fifth delay circuit (25).
The phase is slightly delayed as shown by the arrow H2 in FIG. 4. Even in this state, when the second phase comparator (13) detects a phase shift in the next horizontal scanning period, the fourth... Third. Second. First changeover switch (34), (33), (32), (3
1) Movable contact (34c), ($3°).

(32c) and (31c) to the second fixed contact (34b
), (33b), (32b).

(31b) side, and 4. Third. Second. 1st
delay circuits (24), (23), (22),
(21) is connected to increase the amount of delay. By increasing the delay amount and shifting in this way, the phase shifts as shown by the arrows H3°H-+, Hs, Hs in Fig. 4, and the second phase comparator (13) detects the phase shift. This phase shift is carried out until it no longer occurs. In this way,
The phases match in the range from arrow H to arrow A in FIG.

When the in-phase state is within the range from arrow G to arrow H, that is, when the pulse signal shown in FIG.
If the phase leads within a range of 5° (phase from arrow G2 to G6 in Figure 4) and the same phase occurs, the first
~ When any of the fifth delay circuits (21) to (25) is connected and the phase is set to one of the arrows H2 to H6 in FIG. 4, the phase difference is approximately 45° or more, so The signal output from the data selector (15) becomes a signal advanced by 45° as shown in FIG. 3G. In this state, the delay circuits (21) to (2) are detected by the second phase comparator (13).
5), the phases become as shown by arrows G2 to 66 in FIG. 4, and the phases having the same phase are selected.

G3 Effects of the circuit of this example As described above, according to the phase shift circuit of this example, the data selector (15) adjusts the phase every 45 degrees and the connection of the plurality of delay circuits (21) to (25) allows for a 45 degree range. Input terminal (11) by adjusting the fine phase of the
A pulse signal having the same phase as the color burst signal obtained is output from the output terminal (19).

In this example, since the oscillation signal of the oscillator (17) required by this phase shift circuit is a signal with a frequency approximately eight times that of the input signal, the oscillation frequency of the oscillator (17) is
It can be significantly lower than the conventional circuit shown in the figure. Furthermore, since the phase shift circuit of this example is configured as shown in Fig. 1, it is composed of relatively simple parts such as gate circuits, does not require large-scale parts such as arithmetic circuits, and has a simple circuit configuration. It gets easier.

Note that in the above embodiment, the delay circuits (21) to (25)
) were used to change the phase in 6 ways within a 45° range, but the more delay circuits you use, the more finely the phase can be shifted. 1 within 45° using 11 pieces
If the phase can be changed in two ways, the phase can be changed every 3.8 degrees, assuming equal intervals. Also,
In the above embodiment, the phase shift circuit of a television receiver is used, but it goes without saying that the present invention can be applied to various other phase shift circuits. Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various other configurations without departing from the gist of the present invention.

H Effects of the Invention According to the phase shift circuit of the present invention, the frequency of the oscillation signal required by the circuit can be lowered, and the phase shift circuit outputs a pulse signal with a simple configuration that does not require large circuit components. There are benefits to the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the phase shift circuit of the present invention, FIG. 2 is a block diagram showing the main parts of the example in FIG. 1, and FIGS. 3 and 4 are explanations of the example in FIG. 1, respectively. 5 and 7 are block diagrams showing examples of conventional phase shift circuits, respectively.
FIG. 6 is a diagram for explaining the example in FIG. (11) is the input terminal, (12) is the first phase comparator, (
13) is the second phase comparator, (14) is the first counter, (15) is the data selector, (16) is the linear feedback shift register, (17) is the oscillator, and (1) is the second counter. , (19) is the output terminal, (21) , (22)
. (23), (24) and (25) are the first. Second. Third. 4th and 5th delay circuits, (31), (32
), (33), (34) and (35) are the first.
Second. Third. These are fourth and fifth changeover switches. Fig. 4 An example of a conventional digital pLL circuit &amp;
figure

Claims (1)

[Claims] A shift register that creates a plurality of data based on an oscillation signal, a phase difference detection device that detects a phase difference between an input signal and an output signal, and a shift register that generates a plurality of data based on an oscillation signal; A phase shift circuit comprising: selection means for selecting data output from the shift register; and delay means for delaying the output signal of the selection means in accordance with the detection signal of the phase difference detection means.