JPH05227024A - Pll oscillation device - Google Patents

Abstract

PURPOSE:To stabilize the output frequency of a PLL oscillation device over a wide band. CONSTITUTION:The device is provided with the 1st and 2nd PLL oscillators 12, 14 and a multiplexer 16 receives outputs from both the PLL oscillators 12, 14, selects one of the outputs and outputs the selected result. A CPU 20 controls the oscillation frequency of these PLL oscillators 12, 14 and controls also PLL oscillator output selection executed by the multiplexer 6. The CPU 20 previously sets up the oscillator which is not selected by the multiplexer 16 to a value close to oscillation frequency to be used next. Thereby even if the current oscillator is switched when the output frequency (fo) is changed, the lock-in-time of the oscillator can be shortened because the oscillation frequency has been previously set up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL oscillator capable of obtaining a stable output frequency in a wide band.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional phase locked loop (PL).
It is a basic block diagram of the PLL oscillator using L). In the circuit of the PLL oscillator, a voltage controlled oscillator (VC
O) is provided. Since there is a limit to the oscillation frequency band obtained by one VCO, in a wide band PLL oscillator, the oscillation frequency band is widened by switching and using a plurality of VCOs or dividing by a frequency divider. ..

[0003]

A PLL oscillator requires a certain period of time for its oscillation frequency to stabilize (lock). Lock in the time it takes to lock
Call it time. If the frequency change is large, lock-in
The time gets bigger. That is, when the oscillation frequency is changed significantly, it takes more time until the oscillation stabilizes at that frequency. Further, when the oscillation frequency band is wide, loop gain and the like decrease, and frequency stability and jitter components increase, so that the cost for producing a stable VCO increases.

Lock-in time and frequency stability are in a trade-off relationship. PLL as a device operation reference clock
When using an oscillator, frequency stability is often given priority. However, although it is good when the PLL oscillator is used at a constant frequency, when the frequency is changed and used, the response time becomes a problem due to the lock-in time. That is, the frequency does not change immediately even if the PLL oscillator is changed greatly.

Therefore, an object of the present invention is to provide a PLL oscillation device having a stable output frequency over a wide band by reducing the lock-in time of the oscillation frequency of the PLL oscillator with an inexpensive structure. ..

[0006]

A PLL oscillator according to the present invention has a plurality of at least two PLL oscillators. The multiplexer receives, selects, and outputs the outputs of these PLL oscillators. Further, it comprises a control means for controlling the oscillation frequency of these PLL oscillators and controlling the output selection of the PLL oscillator performed by the multiplexer. This control means presets the oscillation frequency to be used next to the PLL oscillator not selected by the multiplexer. As a result, even if the PLL oscillator is switched when the output frequency fo changes, the lock-in time until the oscillation frequency becomes stable can be short.

[0007]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the first and second PLL oscillators 12 and 14 oscillate at frequencies f1 and f2, respectively. This output signal is selected by the multiplexer 16 and the frequency divider 18 is selected.
Supply to. The frequency divider 18 divides the frequency of the output from the multiplexer 16 by a predetermined frequency division ratio and outputs an output signal of frequency fo. The CPU 20, which is a control unit, controls the operations of the first and second PLL oscillators, the multiplexer, and the frequency divider described above.

The first and second embodiments of the present invention are as follows:
Oscillation frequencies f1 and f2 of the PLL oscillators 12 and 14
110MHz-200MHz and 180M respectively
It is assumed that it has a frequency band of Hz to 260 MHz. Therefore, with 190 MHz as the boundary, the first PLL oscillator is used for the lower frequency and the second PLL oscillator is used for the upper frequency.
Use the LL oscillator.

In the first embodiment, when the oscillation frequency is gradually changed to approach the upper limit or the lower limit of the oscillation frequency band of the currently used PLL oscillator, the P of the one not in use is changed.
The multiplexer 16 selects the output signal of the LL oscillator. At this time, the lock-in time can be shortened by presetting the latter PLL oscillator near the switching frequency. According to this, since the oscillation frequency band of each VCO may be relatively narrow, the stability of the oscillation frequency is improved and the jitter is reduced.

FIGS. 3 to 5 show flowcharts for setting the output frequency fo of the frequency divider 18 to the frequency F according to the first embodiment of the present invention. In step 31, it is determined whether or not the set frequency F can be set, and in steps 33 and 34, the product F * i of the division ratio i and the set frequency F is 125M.
I is set so that it falls within the range of Hz to 250 MHz.
If F * i is 190 MHz or less in step 35, FIG.
, The frequency F * i is set in the first PLL oscillator, and in the second PLL oscillator, as shown in FIG. 5, the multiplexer 16 selects the output signal, and the frequency divider 18 divides the frequency. Set the ratio i. further,
The oscillation frequency of the PLL oscillator not selected by the multiplexer 16 is set according to the value of F * i.

As a concrete example of the first embodiment, the output frequency f
Consider the case of changing o from 63 MHz to 62 MHz. This is because the frequency division ratio i is 2 and the output frequency fo is 63.
When the frequency is lowered to MHz, the oscillation frequency f1 of the first PLL oscillator approaches its lower limit, but at this time, the output frequency f1
It is assumed that o is set to a lower frequency.

When the output frequency fo is set to 63 MHz, the division ratio i = 2 in steps 33 and 34. Since F * i = 126 MHz, step 35 advances to step 36 in FIG. 4, and the first PLL oscillator is selected. In step 37, the second PLL oscillator is set to the oscillating frequency of 250 MHz and the process ends. Next, fo is set to 62 MHz. When the division ratio i is 2,
Since F * i = 124 MHz in step 33, i = 4 in step 34. Therefore, F * i = 24
Since the frequency is 8 MHz, step 35 advances to step 39 in FIG. 5 to select the second PLL oscillator. At this time, since the oscillation frequency f2 of the second PLL oscillator is 250 MHz when fo is set to 63 MHz, the lock-in time can be short even if the frequency is changed to 248 MHz.

FIG. 6 is a flow chart of the second embodiment of the present invention. Oscillation frequency f of the first and second PLL oscillators
Bands 1 and f2 are both 110 MHz to 260 M
Hz. This example assumes continuous adjustment of the output frequency fo. Since the two oscillators have the same oscillation frequency band, the lock-in time can be shortened by alternately using the oscillators when the output frequency fo continuously changes. In FIG. 6, the set frequency of the next oscillation frequency f1 or f2 is predicted from the rate of change of the output frequency fo.

As a concrete example of the second embodiment, the output frequency f
Consider the case where o changes from 100 MHz at a substantially constant rate. First, when fo is set to 100 MHz, the frequency division ratio i becomes 2 in steps 53 and 54. At this time,
Since neither the first nor the second PLL oscillator is used,
From step 55 to step 56, the first PLL oscillator is selected and its oscillation frequency f1 is set to the value of F * i, here 200 MHz. Next, the output frequency fo
Is set to 90 MHz, the frequency division ratio i becomes 2 in steps 53 and 54, the second PLL oscillator is selected in step 57, and its oscillation frequency f2 is set to 180 MHz. The amount of change of the output frequency fo from 100 MHz to 90 MHz is −10 MHz. When the output frequency fo is continuously adjusted, the next output frequency fo is 80
Since it can be expected to be MHz, in step 57, 160 MHz is set as the expected oscillation frequency in the first PLL oscillator by the same steps as steps 51 to 55.
Therefore, even when the output frequency fo changes and the second PLL oscillator is switched to the first PLL oscillator,
The lock-in time of the L oscillator is short.

In the second embodiment, since the next set value is predicted from the change rate, when the output frequency fo is changed at a constant rate, a frequency change with a small lock-in time will occur. can get. Further, by using another prediction method, it is possible to change the output frequency suitable for the control method. Furthermore, if the oscillation frequency band is divided by using more PLL oscillators, a high-performance oscillator can be configured over a wider band.

[0016]

According to the present invention, at least two PLs are used.
Since the L oscillator is used and the PLL oscillator not currently used is set near the oscillation frequency to be used next, even if the PLL oscillator is switched when the output frequency changes,
The lock-in time of the L oscillator is short. Therefore, even if a plurality of PLL oscillators are used, the stability of the output frequency is improved over a wide band and the jitter is reduced. Also,
Since the structure is simple, it can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL oscillator according to the present invention.

FIG. 2 is a block diagram of a conventional basic PLL oscillator.

FIG. 3 is a flowchart according to the first embodiment of the present invention.

FIG. 4 is a flowchart according to the first embodiment of the present invention.

FIG. 5 is a flowchart according to the first embodiment of the present invention.

FIG. 6 is a flowchart according to a second embodiment of the present invention.

[Explanation of symbols]

 10 PLL Oscillator 12 First PLL Oscillator 14 Second PLL Oscillator 16 Multiplexer 18 Frequency Divider 20 CPU

Claims (1)

[Claims] 1. At least two PLL oscillators, a multiplexer that receives, selects, and outputs the outputs of the PLL oscillators, and a control unit that controls the oscillation frequency of the PLL oscillators and the output selection of the PLL oscillators performed by the multiplexers. The PLL oscillating device, wherein the control means presets a predetermined oscillation frequency to be used next to the PLL oscillator not selected by the multiplexer.